Author: claimsbot

1. An apparatus for calibrating gain of a radio receiver (\u201cRx\u201d) path in a radio frequency (\u201cRF\u201d) integrated circuit comprising:
a thermal noise generator configured to generate thermal noise as a calibrating signal into an input of said Rx path; and
a calibrator configured to:
measure an output signal from an output of said Rx path, and
adjust a gain of said Rx path based on said thermal noise.
2. The apparatus of claim 1 wherein said thermal noise generator further comprises a termination resistance or impedance, wherein said thermal noise generated therefrom is constant over frequencies useable by said RF integrated circuit.
3. The apparatus of claim 2 wherein said calibrator adjusts said gain by an amount derived from a noise figure (\u201cNF\u201d) of said Rx path, said noise figure being less susceptible to variations over process and temperature than is said gain.
4. The apparatus of claim 1 further comprising a temperature sensor coupled to said calibrator for adjusting a value of said noise figure in accordance with a measured ambient temperature to improve calibration accuracy.
5. The apparatus of claim 1 wherein said calibrator is an in-situ calibrator configured to automatically calibrate said gain while said RF integrated circuit remains configured to receive RF communication signals.
6. The apparatus of claim 1 wherein said calibrator further comprises:
a gain evaluator configured to determine a gain differential between a calculated gain that is based on said output signal and an expected gain; and
a gain adjuster configured to adjust said gain of said Rx path by an amount equivalent to said gain differential, said Rx path including an adjustable amplifier.
7. The apparatus of claim 6 wherein said gain evaluator further comprises:
an output quantifier configured to quantify an output noise power signal as said output signal to determine a measured output noise power signal value; and
a parametric generator configured to provide a plurality of parameters associated with said Rx path, at least one parameter being an input noise power signal value representative of said thermal noise,
wherein said gain evaluator determines said calculated gain as a function of said measured output noise power signal value and said input noise power signal value.
8. The apparatus of claim 7 wherein said plurality of parameters associated with said Rx path further comprises one or more of the following:
a noise figure value representing an equivalent noise figure for said Rx path, and
an equivalent noise bandwidth value representing an equivalent noise bandwidth of said Rx path,
wherein said gain evaluator determines said calculated gain as a difference between said measured output noise power signal value and a collective value representative of contributions by said input noise power signal value, said noise figure value, and said equivalent noise bandwidth value.
9. The apparatus of claim 7 further comprising an analog-to-digital converter for digitizing said output noise power signal to form said measured output noise power signal value.
10. The apparatus of claim 9 wherein said plurality of parameters associated with said Rx path further comprises one or more of the following:
an upper limit of operation of said analog-to-digital converter associated with a first error value representing a clipping error,
a lower limit of operation of said analog-to-digital converter associated with a second error value representing a quantization error, and
a sample size value associated with a sample size for maintaining an estimation error during measurement of said measured output noise power signal value,
wherein said gain evaluator determines said gain differential so that during calibration said output noise power signal does not surpass either said upper limit of operation or lower upper limit of operation,
wherein said gain evaluator quantifies said output noise power signal using said sample size value.
11. A method for calibrating a radio frequency (\u201cRF\u201d) integrated circuit comprising:
modeling an effective input noise power signal value from at least one noise figure (\u201cNF\u201d) value associated with an RF radio receiver as an input thereto;
measuring an output noise power signal from said RF radio receiver to form a measured output noise power signal value; and
calibrating a gain of said RF radio receiver as a function of said effective input noise power signal value and said measured output noise power signal value.
12. The method of claim 11 wherein measuring said output noise power signal comprises:
generating thermal noise; and
applying said thermal noise as a calibrating signal into said RF radio receiver,
wherein generating thermal noise and applying said thermal noise are repeatable for performing in-situ calibration of said gain.
13. The method of claim 11 further comprising:
measuring ambient temperature to determine a measured temperature for improving calibration accuracy;
modifying a value of said at least one noise figure to form a modified noise figure value based on said measured temperature; and
adjusting said gain in accordance with said modified noise figure value.
14. The method of claim 11 wherein modeling said effective input noise power signal comprises:
determining a first noise figure value for an estimated thermal noise value;
determining a second noise figure value for an Rx path of said RF radio receiver;
determining an equivalent noise bandwidth for said Rx path; and
deriving said effective input noise power signal value from said first noise figure value, said second noise figure value and said equivalent noise bandwidth.
15. The method of claim 11 wherein calibrating said gain comprises:
calculating a calculated gain based on said measured output noise power signal value and said effective input noise power signal value;
determining a gain differential between said calculated gain and a desired gain; and
adjusting said gain of said RF radio receiver by an amount equivalent to said gain differential.
16. The method of claim 11 wherein measuring said output noise power signal comprises:
determining an upper limit of operation associated with a clipping error;
determining a lower limit of operation associated with a quantization error;
determining a sample size value representing a sample size for maintaining an estimation error during measurement of said measured output noise power signal value;
adjusting said gain so that during calibration said output noise power signal does not surpass either said upper limit of operation or lower upper limit of operation; and
using said sample size value during measurement of said measured output noise power signal value.
17. A bi-modal radio receiver (\u201cRx\u201d) integrated circuit formed on a substrate and configured to operate in a receiver mode to receive radio communication signals and to operate in a calibration mode to perform in-situ gain calibration, the bi-modal radio Rx integrated circuit comprising:
an antenna port configured to receive radio communication signals from an antenna;
an in-situ calibration signal generator configured to internally generate a calibration signal;
a mode selector configured to select a signal source from either said antenna port or said in-situ calibration signal generator; and
an amplification path including an amplifier having a gain that is adjustable, said amplifier path coupled to said mode selector for amplifying radio communication signals in said receiver mode and for amplifying said calibration signal in said calibration mode,
wherein said amplifier is configured to receive an adjustment signal representative of an amount to adjust said gain.
18. The bi-modal radio Rx integrated circuit of claim 17 wherein said calibration signal is thermally generated and said amplifier is a radio frequency (\u201cRF\u201d) amplifier.
19. The bi-modal radio Rx integrated circuit of claim 17 wherein said adjustment signal is based on a noise figure value of at least a portion of said amplification path.
20. The bi-modal radio Rx integrated circuit of claim 17 wherein said Rx amplification further comprises an analog-to-digital converter, whereby said adjustment signal is configured to modify said gain to minimize measurement errors due to said analog-to-digital converter including clipping errors, quantization noise floor errors, and estimation errors due to sample size.
21. A system for calibrating gain of a radio receiver (\u201cRx\u201d) path comprising:
a radio receiver subsystem having:
a thermal noise source configured to provide a calibration signal,
an Rx path, and
one or more filters, each being modeled to respectively have a thermal noise source value, an Rx path noise figure value, and an equivalent noise bandwidth for said one or more filters, and
a gain adjuster to adjust a gain of said radio receiver subsystem; and

a processor configured to communicate with a central processing unit (\u201cCPU\u201d) of a networked computing device, said processor comprising a gain calibrator including:
parameter generator to provide parameter values for deriving an effective input noise power signal value, said parameter values including said thermal noise source value, said Rx path noise figure value, andor said equivalent noise bandwidth,
an output quantifier to measure an output noise power signal from said Rx path to form a measured output noise power signal value,
a gain evaluator configured to determine a gain differential between a calculated gain and an expected gain, said calculated gain being a function of said measured output noise power signal value and said effective input noise power signal value,

wherein said gain differential is passed to said gain adjuster for calibrating said gain.
22. The system of claim 21 further comprising a temperature sensor coupled to said gain calibrator for modifying either said thermal noise source value or said Rx path noise figure value, or both, based on a measured ambient temperature to improve calibration accuracy.
23. The system of claim 21 wherein said radio receiver is a constituent element of an RF integrated circuit manufactured using a complementary metal oxide semiconductor (\u201cCMOS\u201d) processing technology, and said processor is a base band processor including a medium access controller (\u201cMAC\u201d) module for operating said system in a wireless local area network (\u201cWLAN\u201d).
24. The system of claim 21 wherein said Rx path further comprises an analog-to-digital converter, whereby said gain calibrator is configured to modify said gain differential to minimize measurement errors due to said analog-to-digital converter including clipping errors, quantization noise floor errors, and estimation errors due to sample size.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A substrate processing system, comprising:
a processing module to process a substrate;
a factory interface module configured to accommodate at least one cassette for holding the substrate;
a spectrographic monitoring system positioned in or adjoining the factory interface module;
a substrate handler to transfer the substrate between the at least one cassette, the spectrographic monitoring system and the processing module; and
a controller to control the substrate handler, wherein the controller is configured to cause the substrate handler to move such that spectra are measured in a plurality of positions that form a non-linear path on the substrate.
2. The substrate processing system of claim 1, wherein the spectrographic monitoring system includes an optical probe and is configured to measure spectra at a plurality of positions on the substrate while the substrate is moving relative to the optical probe.
3. The substrate processing system of claim 2, wherein the controller is configured to cause the substrate handler to move the substrate past the optical probe while the spectrographic monitoring system measures spectra at the plurality of positions.
4. The substrate processing system of claim 3, the optical probe remains stationary while the spectrographic monitoring system measures spectra at the plurality of positions.
5. The substrate processing system of claim 4, wherein the optical probe is fixed relative to the factory interface module.
6. The substrate processing system of claim 3, wherein the controller and substrate handler are configured such that a same substrate gripper removes the substrate from a cassette and moves the substrate past the optical probe.
7. The substrate processing system of claim 1, wherein the controller is configured to cause the substrate handler to move the substrate handler such that spectra are measured in a plurality of positions that span a diameter of the substrate in less than ten seconds.
8. The substrate processing system of claim 1, wherein the non-linear path is a figure-eight shape.
9. The substrate processing system of claim 1, wherein the non-linear path includes a plurality of straight segments and a plurality of curved segments.
10. The substrate processing system of claim 9, wherein at least one of the plurality of curved segments extend along an edge of the substrate.
11. The substrate processing system of claim 2, wherein the monitoring system and controller are configured to operate in a first mode in which the monitoring system measures a first plurality spectra from a first plurality of locations on a reference substrate and generates a library associating the first plurality of spectra with measured substrate characteristics, and a second mode in which the monitoring system measures a second spectra from a second location on a product substrate and determines a substrate characteristic for the second location from the second spectra and the library.
12. A substrate processing system according to claim 11, wherein the controller is configured to cause the substrate handler to move the reference substrate such that the optical probe scans a first path on the reference substrate and is configured to cause the substrate handler to move the product substrate such that the optical probe scans a different second path on the product substrate.
13. The substrate processing system of claim 12, wherein the second path is shorter than the first path.
14. The substrate processing system of claim 1, wherein the controller is configured to cause the substrate handler to transfer the substrate to the processing module after the substrate is measured at a spectrographic monitoring system.
15. The substrate processing system of claim 1, wherein the controller is configured to cause the substrate handler to transfer the substrate to the processing module before the substrate is measured at a spectrographic monitoring system.
16. The substrate processing system of claim 1, wherein the spectrographic monitoring system includes an optical probe and is configured to measure spectra at a plurality of positions on the substrate without aligning the optical probe to well-defined locations on the substrate.
17. The substrate processing system of claim 1, wherein the spectrographic monitoring system is positioned in the factory interface module.
18. The substrate processing system of claim 1, further comprising a notch alignment system to position a notch of the substrate in a determined orientation.
19. A method of operating a substrate processing system, comprising:
picking a substrate from a cassette and moving the substrate into a factory interface module with a substrate handler;
obtaining spectra of the substrate at a plurality of positions on the substrate with a spectrographic monitoring system positioned in or adjoining the factory interface module;
moving the substrate from the factory interface module to a processing module with the substrate handler, wherein obtaining spectra at the plurality of positions on the substrate occurs while the substrate is moving relative to an optical probe in the spectrographic monitoring system and wherein the substrate moves relative to the optical probe such that the plurality of positions form a non-linear path on the substrate; and
processing the substrate in a processing module.
20. The method of claim 19, further comprising holding the optical probe fixed during the step of obtaining spectra.
21. A computer program product, tangibly stored on a machine readable storage device, the product comprising instructions operable to cause a processor to operate a substrate processing system to:
pick a substrate from a cassette and move the substrate into a factory interface module with a substrate handler;
obtain spectra of the substrate at a plurality of positions on the substrate with a spectrographic monitoring system positioned in or adjoining the factory interface module;
cause the substrate handler to move such that the plurality of positions form a non-linear path on the substrate;
move the substrate from the factory interface module to a processing module with the substrate handler; and
process the substrate in a processing module.

What is claimed is:

1. A semiconductor device, comprising:
a first node which is provided a first voltage;
a second node which is provided a second voltage, wherein said second voltage is lower than said first voltage;
a first current mirror circuit which has an input terminal and an output terminal, wherein said first current mirror circuit is coupled with said first node;
a second current mirror circuit which has an input terminal and an output terminal, wherein said input terminal of said second current mirror circuit is coupled with said output terminal of said first current mirror circuit, wherein said output terminal of said second current mirror circuit is coupled with said input terminal of said first current mirror circuit and wherein said second current mirror circuit is coupled with said second node;
a start-up circuit which supplies current to said input terminal of said second current mirror circuit based on voltage on said input terminal of said first current mirror circuit.
2. The semiconductor device in accordance with claim 1, wherein said start-up circuit comprises;
a third node;
a capacitance element which is coupled between said third node and said second node;
a first switch which has an ON state and an OFF state, and which is coupled between said first node and said input terminal of said second current mirror circuit; and
a second switch which has an ON state and an OFF state, and which is coupled between said first node and said third node.
3. The semiconductor device in accordance with claim 2, wherein said first switch comprises a first transistor which has a control electrode coupling with said third node, a first electrode coupling with said first node and a second electrode coupling with said input terminal of said second current mirror circuit, and wherein said second switch comprises a second transistor which has a control electrode coupling with said input terminal of said first current mirror circuit, a first electrode coupling with said first node and a second electrode coupling with said third node.
4. The semiconductor device in accordance with claim 3, wherein first current mirror circuit has a third transistor which has a first electrode coupling with said first node and a control and a second electrodes coupling with said input terminal thereof, and a fourth transistor which has a first electrode coupling with said first node, a control electrode coupling with said control electrode of said third transistor and a second electrode coupling with said output terminal thereof; and wherein said second current mirror circuit has a fifth transistor which has a first electrode coupling with said second node and a control and a second electrodes coupling with said input terminal thereof, and a sixth transistor which has a first electrode coupling with said second node through a resistor, a control electrode coupling with said control electrode of said fifth transistor and a second electrode coupling with said output terminal thereof.
5. The semiconductor device in accordance with claim 3, wherein first current mirror circuit has a third transistor which has a first electrode coupling with said first node and a control and a second electrodes coupling with said input terminal thereof, and a fourth transistor which has a first electrode coupling with said first node through a resistor, a control electrode coupling with said control electrode of said third transistor and a second electrode coupling with said output terminal thereof; and
wherein said second current mirror circuit has a fifth transistor which has a first electrode coupling with said second node and a control and a second electrodes coupling with said input terminal thereof, and a sixth transistor which has a first electrode coupling with said second node, a control electrode coupling with said control electrode of said fifth transistor and a second electrode coupling with said output terminal thereof.
6. The semiconductor device in accordance with claim 1, wherein said start-up circuit comprises;
a third node;
a capacitance element which is coupled between said third node and said second node;
a resistor which is coupled with said first node;
a first switch which has an ON state and an OFF state, and which is coupled between said first node and said input terminal of said second current mirror circuit; and
a second switch which has an ON state and an OFF state, and which is coupled between said resistor and said third node.
7. The semiconductor device in accordance with claim 6, wherein said first switch comprises a first transistor which has a control electrode coupling with said third node, a first electrode coupling with said first node and a second electrode coupling with said input terminal of said second current mirror circuit, and wherein said second switch comprises a second transistor which has a control electrode coupling with said input terminal of said first current mirror circuit, a first electrode coupling with said resistor and a second electrode coupling with said third node.
8. The semiconductor device in accordance with claim 7, wherein first current mirror circuit has a third transistor which has a first electrode coupling with said first node and a control and a second electrodes coupling with said input terminal thereof, and a fourth transistor which has a first electrode coupling with said first node, a control electrode coupling with said control electrode of said third transistor and a second electrode coupling with said output terminal thereof; and wherein said second current mirror circuit has a fifth transistor which has a first electrode coupling with said second node and a control and a second electrodes coupling with said input terminal thereof, and a sixth transistor which has a first electrode coupling with said second node through a resistor, a control electrode coupling with said control electrode of said fifth transistor and a second electrode coupling with said output terminal thereof.
9. The semiconductor device in accordance with claim 7, wherein first current mirror circuit has a third transistor which has a first electrode coupling with said first node and a control and a second electrodes coupling with said input terminal thereof, and a fourth transistor which has a first electrode coupling with said first node through a resistor, a control electrode coupling with said control electrode of said third transistor and a second electrode coupling with said output terminal thereof; and
wherein said second current mirror circuit has a fifth transistor which has a first electrode coupling with said second node and a control and a second electrodes coupling with said input terminal thereof, and a sixth transistor which has a first electrode coupling with said second node, a control electrode coupling with said control electrode of said fifth transistor and a second electrode coupling with said output terminal thereof.
10. A semiconductor device, comprising:
a first node which is provided a first voltage;
a second node which is provided a second voltage, wherein said second voltage is lower than said first voltage;
a first current mirror circuit which has an input terminal and an output terminal, wherein said first current mirror circuit is coupled with said first node;
a second current mirror circuit which has an input terminal and an output terminal, wherein said input terminal of said second current mirror circuit is coupled with said output terminal of said first current mirror circuit, wherein said output terminal of said second current mirror circuit is coupled with said input terminal of said first current mirror circuit and wherein said second current mirror circuit is coupled with said second node;
a start-up circuit which supplies current to said input terminal of said first current mirror circuit based on voltage on said input terminal of said second current mirror circuit.
11. The semiconductor device in accordance with claim 10, wherein said start-up circuit comprises;
a third node;
a capacitance element which is coupled between said first node and said third node;
a first switch which has an ON state and an OFF state, and which is coupled between said second node and said input terminal of said first current mirror circuit; and
a second switch which has an ON state and an OFF state, and which is coupled between said second node and said third node.
12. The semiconductor device in accordance with claim 11, wherein said first switch comprises a first transistor which has a control electrode coupling with said third node, a first electrode coupling with said second node and a second electrode coupling with said input terminal of said first current mirror circuit, and wherein said second switch comprises a second transistor which has a control electrode coupling with said input terminal of said second current mirror circuit, a first electrode coupling with said second node and a second electrode coupling with said third node.
13. The semiconductor device in accordance with claim 12, wherein first current mirror circuit has a third transistor which has a first electrode coupling with said first node and a control and a second electrodes coupling with said input terminal thereof, and a fourth transistor which has a first electrode coupling with said first node, a control electrode coupling with said control electrode of said third transistor and a second electrode coupling with said output terminal thereof; and wherein said second current mirror circuit has a fifth transistor which has a first electrode coupling with said second node and a control and a second electrodes coupling with said input terminal thereof, and a sixth transistor which has a first electrode coupling with said second node through a resistor, a control electrode coupling with said control electrode of said fifth transistor and a second electrode coupling with said output terminal thereof.
14. The semiconductor device in accordance with claim 12, wherein first current mirror circuit has a third transistor which has a first electrode coupling with said first node and a control and a second electrodes coupling with said input terminal thereof, and a fourth transistor which has a first electrode coupling with said first node through a resistor, a control electrode coupling with said control electrode of said third transistor and a second electrode coupling with said output terminal thereof; and
wherein said second current mirror circuit has a fifth transistor which has a first electrode coupling with said second node and a control and a second electrodes coupling with said input terminal thereof, and a sixth transistor which has a first electrode coupling with said second node, a control electrode coupling with said control electrode of said fifth transistor and a second electrode coupling with said output terminal thereof.
15. A semiconductor device, comprising:
a first node which is provided a first voltage;
a second node which is provided a second voltage, wherein said second voltage is lower than said first voltage;
a first current mirror circuit which is coupled with said first node;
a second current mirror circuit which is coupled with said second node, wherein said second current mirror circuit is coupled with said first current mirror circuit through a third node and a fourth node;
a start-up circuit which supplies current to said fourth node based on voltage on said third node.
16. The semiconductor device in accordance with claim 15, wherein said start-up circuit comprises;
a fifth node;
a capacitance element which is coupled between said fifth node and said second node;
a first switch which has an ON state and an OFF state, and which is coupled between said first node and said fourth node; and
a second switch which has an ON state and an OFF state, and which is coupled between said first node and said fifth node.
17. The semiconductor device in accordance with claim 16, wherein said first switch comprises a first transistor which has a control electrode coupling with said fifth node, a first electrode coupling with said first node and a second electrode coupling with said fourth node, and
wherein said second switch comprises a second transistor which has a control electrode coupling with said third node, a first electrode coupling with said first node and a second electrode coupling with said fifth node.
18. The semiconductor device in accordance with claim 17, wherein first current mirror circuit has a third transistor which has a first electrode coupling with said first node and a control and a second electrodes coupling with said third node, and a fourth transistor which has a first electrode coupling with said first node, a control electrode coupling with said control electrode of said third transistor and a second electrode coupling with said fourth node; and
wherein said second current mirror circuit has a fifth transistor which has a first electrode coupling with said second node and a control and a second electrodes coupling with said fourth node, and a sixth transistor which has a first electrode coupling with said second node through a resistor, a control electrode coupling with said control electrode of said fifth transistor and a second electrode coupling with said third node.
19. The semiconductor device in accordance with claim 17, wherein first current mirror circuit has a third transistor which has a first electrode coupling with said first node and a control and a second electrodes coupling with said third node, and a fourth transistor which has a first electrode coupling with said first node through a resistor, a control electrode coupling with said control electrode of said third transistor and a second electrode coupling with said fourth node; and wherein said second current mirror circuit has a fifth transistor which has a first electrode coupling with said second node and a control and a second electrodes coupling with said fourth node, and a sixth transistor which has a first electrode coupling with said second node, a control electrode coupling with said control electrode of said fifth transistor and a second electrode coupling with said third node.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for estimating error in measured data from a controlled-source electromagnetic survey of a subsurface region, comprising:
(a) selecting data from the electric or magnetic field survey data, said selected data corresponding to a plurality of different offsets (source-receiver spacings) and to a selected single frequency in the source’s signal’s frequency spectrum;
(b) generating a geo-electric model of the subsurface region, said model including at least resistivity or conductivity as a function of position in the region;
(c) solving electromagnetic field equations to simulate the survey’s electromagnetic responses for said selected frequency and for source and receiver locations corresponding to said selected data, using the geo-electric model of the subsurface region and survey source parameters;
(d) selecting a near-zero offset range; and
(e) estimating data error at all offsets by comparing measured survey data to simulated data at least one offset within said selected range of near-zero offsets, said estimated error providing a means for correcting measured data.
2. The method of claim 1, wherein the survey data obtained are phase data.
3. The method of claim 1, wherein the survey data obtained are amplitude data.
4. The method of claim 1, wherein the error is estimated by data fitting in a selected norm such as least-squares for at least one offset within said selected range of near-zero offsets.
5. The method of claim 1, wherein said geo-electric model also includes at least one of a group consisting of complex conductivity, permeability and permittivity, each as a function of position in the subsurface region.
6. The method of claim 2, wherein the estimating data error step results in a single phase shift which can be applied to correct measured phase data.
7. The method of claim 3, wherein the estimating data error step results in a single amplitude scale factor which can be applied to correct measured amplitude data.
8. The method of claim 1, further comprising repeating steps (a)-(e) for all source and receiver locations in the survey and for all frequencies in the source’s frequency spectrum having associated amplitude within a pre-selected range.
9. The method of claim 8, wherein the same geo-electric model is used for each repetition of steps (a)-(e).
10. The method of claim 1, further comprising plotting measured and simulated data vs. offset and using the plot to select the near-zero offset range and to estimate the data error over said range.
11. The method of claim 1, wherein the near-zero offset range is from about \u22122 km to about +2 km but excluding a near-zero sub-range determined based on observation of receiver saturation effects within said sub-range.
12. The method of claim 1, wherein said geo-electric model and said simulation of electromagnetic responses are three dimensional.
13. The method of claim 1, wherein said selected survey data are recorded at a single receiver location.
14. The method of claim 1, wherein said selected survey data correspond to a single source location.
15. A method for producing hydrocarbons from a subsurface region, comprising:
(a) performing a controlled-source electromagnetic survey of the subsurface region;
(b) obtaining data from said survey, corrected for error by the method of claim 1;
(c) using the corrected data to identify a layer showing a resistivity anomaly indicating presence of hydrocarbons; and
(d) drilling a well into said anomalous layer and producing hydrocarbons.
16. The method of claim 15, wherein the survey data corrected are phase data.
17. The method of claim 15, wherein the survey data corrected are amplitude data.