Author: claimsbot

1. An electromagnetic relay, comprising:
a fixing contact;
a movable contact configured to be moved to or from the fixing contact in an approaching and separating direction;
a fixed part having a surface, facing the movable contact in the approaching and separating direction, onto which the fixing contact is attached;
a movable part;
a driving part configured to drive the movable part;
a pressing part configured to press the movable contact based on the driving of the movable part; and
a magnetic body having one portion being covered and held and another portion being uncovered, not contacting the fixing contact and directly exposed to an external periphery side of at least one of the fixing contact, the movable contact, and an air space between the fixing contact and the movable contact,
wherein the magnetic body is sandwiched between the fixed part and the movable part.
2. The electromagnetic relay as claimed in claim 1,
wherein the magnetic body includes a fixing side magnetic body positioned at the external periphery side of the fixing contact.
3. The electromagnetic relay as claimed in claim 1,
wherein the magnetic body includes an air space side magnetic body positioned at the external periphery side of the air space.
4. The electromagnetic relay as claimed in claim 1,
wherein the magnetic body overlaps a portion of the surface of the fixed part onto which the fixing contact is attached and a portion of a surface of the movable part onto which the movable contact is attached.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A circuit arrangement, comprising:
first, second and third semiconductor dies physically and electrically coupled to one another in a stack, each semiconductor die including opposing faces, wherein at least one face of each semiconductor die includes circuit logic integrated thereon and defining a circuit layer, and each semiconductor die including an array of conductive through vias extending through such semiconductor die;
a first electricalphysical interconnect physically and electrically coupling the first and second semiconductor dies with one another using a wafer-wafer bonding process; and
a second electricalphysical interconnect physically and electrically coupling the second and third semiconductor dies with one another.
2. The circuit arrangement of claim 1, wherein a first subset of the conductive through vias in each semiconductor die are configured as data-carrying through vias that communicate data between the circuit layer on such semiconductor die and another circuit layer disposed on another semiconductor die in the stack, and wherein a second subset of the conductive through vias are configured as power-carrying through vias that are coupled to a power distribution network for the circuit layer on such semiconductor die.
3. The circuit arrangement of claim 1, wherein the circuit layer in each semiconductor die includes at least one functional unit, wherein at least one face of each semiconductor die includes an inter-layer interface region disposed thereon, wherein each inter-layer interface region on each semiconductor die is disposed at substantially the same topographic location when the respective semiconductor die is disposed within the stack, and wherein the circuit arrangement further comprises an inter-layer bus electrically coupling the functional units on the plurality of semiconductor dies to one another, the inter-layer bus comprising a plurality of electrical conductors disposed within the inter-layer interface region of each semiconductor die and extending between the opposing faces of each semiconductor die, wherein respective electrical conductors disposed in the inter-layer interface regions of adjacent semiconductor dies in the stack are electrically coupled to one another when the plurality of circuit layers are physically and electrically coupled to one another in the stack.
4. The circuit arrangement of claim 1, wherein each semiconductor die includes an array of contact pads disposed on at least one face of such semiconductor die and topographically aligned with the array of conductive through vias, wherein the first electricalphysical interconnect includes a first array of electrical conductors extending between topographically aligned contact pads on the first and second semiconductor dies, and wherein the second electricalphysical interconnect includes a second array of electrical conductors extending between topographically aligned contact pads on the second and third semiconductor dies.
5. The circuit arrangement of claim 4, wherein the plurality of electrical conductors in each of the first and second electricalphysical interconnects comprise a plurality of micro C? interconnects.
6. The circuit arrangement of claim 4, wherein the array of contact pads disposed on each semiconductor die is a regular array, wherein a first subset of the contact pads in the array of contact pads on each semiconductor die are configured as data-carrying contact pads that are electrically coupled to data-carrying through vias, wherein a second subset of the contact pads in the array of contact pads on each semiconductor die are configured as power-carrying contact pads that are electrically coupled to power-carrying through vias, and wherein a third subset of the contact pads are dummy contact pads that are not topographically aligned with any of the conductive through vias.
7. The circuit arrangement of claim 4, wherein the first electricalphysical interconnect has a higher interconnect density than the second electricalphysical interconnect.
8. The circuit arrangement of claim 1, wherein the first electricalphysical interconnect is formed while the first and second semiconductor dies are disposed on first and second semiconductor wafers, and wherein the first and second semiconductor dies are separated from the first and second wafers after the first electricalphysical interconnect is formed.
9. The circuit arrangement of claim 8, wherein the first and second semiconductor dies are separated from the first and second semiconductor wafers before the second electricalphysical interconnect is formed, and wherein the second electricalphysical interconnect is formed using a chip-chip bonding process.
10. The circuit arrangement of claim 8, wherein the first and second semiconductor dies are separated from the first and second semiconductor wafers after the second electricalphysical interconnect is formed, and wherein the second electricalphysical interconnect is formed using a chip-wafer bonding process.
11. The circuit arrangement of claim 8, wherein the first and second semiconductor dies each include an array of through silicon vias (TSVs) formed therein by partially etching a regular array of holes in the first and second semiconductor wafers from the first surface thereof, thinning the first and second semiconductor wafers to expose the regular array of holes on a second surface of the first and second semiconductor wafers, and forming the TSVs in the regular array of holes in the first and second semiconductor wafers.
12. The circuit arrangement of claim 1, wherein the first and third semiconductor dies differ from one another by at least one of size, thickness and aspect ratio.
13. A program product, comprising at least one hardware design file defining the plurality of circuit layers of claim 1, and a non-transitory computer readable storage medium storing the at least one hardware design file.

1. A flying disc toy formed from plastic resin comprising,
a circular central body portion,
a circular downturned rim surrounding the body portion,
the rim having a stair-step cross-sectional configuration to rigidify the rim and maintain flight characteristics,
said rim including an upper step and a lower step peripherally thereof each having a circular tread portion and an upright annular riser portion that are at right angles to one another,
an inner surface of the lower riser is dimensioned to form a sliding fit over an outer surface of the upper riser of a similar disc stacked beneath said disc,
both risers have about the same height such that the discs form a stack when the discs are slid telescopically into one another
a lower edge of the rim is configured and dimensioned to fit into a right angle intersection that is positioned between an outer surface of an upper riser and an upper surface of a lower tread of each disc and
an outer surface of the lower riser is inclined so as to taper centrally proceeding toward a lower edge of the rim.
2. The disc of claim 1 wherein the circular central body portion is engraved on its upper surface with alphanumeric information or other indicia.
3. The disc of claim 1 wherein the disc is provided with indicia in the shape of a molding die having a removable insert that is engraved with said indicia.
4. A flying disc toy formed from plastic resin comprising,
a circular central body portion,
a circular downturned rim surrounding the body portion,
the rim having a stair-step cross-sectional configuration to rigidify the rim and maintain flight characteristics,

said rim including an upper step and a lower step peripherally of the upper step, each such step having a circular tread portion and an upwardly extending annular riser portion that have an angular intersection with one another,
an inner surface of the lower riser is dimensioned to form a sliding fit over an outer surface of the upper riser of a similar disc stacked beneath said disc
each riser having a height that enables the discs to form a stack when the discs are slid telescopically into one another,
an outer surface of a lower riser is inclined so as to taper centrally proceeding toward a lower edge of the rim and
a lower edge of the rim is configured and dimensioned to fit into said angular intersection that is positioned between an outer surface of an upper riser and an upper surface of a lower tread of each disc.
5. The disc of claim 4 wherein the central body portion has a flat circular center section surrounded by a frustoconical downwardly inclined apron that extends outwardly to the tread of said upper step.
6. The disc of claim 4 wherein a lower edge of the rim is configured and dimensioned to fit into a right angle intersection that is located between an outer surface of an upper riser and an upper surface of a lower tread of said disc.
7. The disc of claim 4 wherein the circular central body portion is engraved on its upper surface with alphanumeric information or other indicia.
8. The disc of claim 7 wherein the disc is provided with indicia in the shape of a molding die having a removable insert that is engraved with said indicia.
9. The disc of claim 1 wherein the body portion has a circular center surrounded by a frustoconical downwardly inclined apron that extends outwardly to the tread of said upper step.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A CMOS pixel, comprising:
epitaxial silicon;
at least one transfer gate formed overlying the epitaxial silicon;
a pinned-photodiode formed in the epitaxial silicon adjacent to the at least one transfer gate;
a multi-pinned (MP) implant layer implanted in the epitaxial silicon, wherein the pinned-photodiode comprises a portion of the MP implant layer and another portion of the MP implant layer is under the at least one transfer gate; and
a sense node at least partially extending into the MP implant layer proximal to at least one of the at least one transfer gate.
2. The CMOS pixel of claim 1, wherein the MP implant layer facilitates passivating dark current in the MP implant layer beneath the at least one transfer gate when the at least one transfer gate is in an inverted state and promotes charge transfer conditions when in a transfer state.
3. The CMOS pixel of claim 1, wherein the MP implant layer is operable to pin the surface of the epitaxial silicon to a pinning potential established by the MP implant layer at multiple locations within the CMOS pixel.
4. The CMOS pixel of claim 3 wherein the multiple locations are at least the pinned photodiode and the at least one transfer gate.
5. The CMOS pixel of claim 1, wherein the at least one transfer gate comprises a first gate and a second gate and:
the second gate, proximate the pinned photodiode, has a portion of the MP implant layer beneath the second gate.
6. The CMOS pixel of claim 5, further comprising a drain formed at least partially extending into the MP implant layer proximal to the second gate.
7. The CMOS pixel of claim 5, further comprising a control circuit for applying a potential to at least one of the at least one transfer gates, wherein the potential drives at least one of the at least one transfer gates into inversion to passivate dark current.
8. The CMOS pixel of claim 7, wherein the potential is within about 0.5 volts of a potential of the epitaxial silicon.
9. A CMOS pixel, comprising:
epitaxial silicon;
at least one transfer gate formed overlying the epitaxial silicon;
a pinned-photodiode formed in the epitaxial silicon adjacent to the at least one transfer gate; and
a multi-pinned (MP) implant layer implanted in the epitaxial silicon, wherein the pinned-photodiode comprises a portion of the MP implant layer and another portion of the MP implant layer is under the at least one transfer gate, wherein the MP implant layer extends substantially across the entire CMOS pixel.
10. The CMOS pixel of claim 1 wherein the MP implant layer is implanted to a depth of about at least 450 Angstroms.
11. The CMOS pixel of claim 1 wherein the MP implant layer is implanted to a dose of about 1\xd71012 ionscm2 using about an energy of 20 keV to about 30 keV.
12. The CMOS pixel of claim 1, further comprising a barrier implant formed in the epitaxial silicon, wherein the barrier implant extends at least partially underlying the at least one transfer gate for providing additional charge collection capability to the pinned photodiode.
13. The CMOS pixel of claim 1 wherein the MP implant layer extends only partially into the pinned photodiode and beneath the at least one transfer gate.
14. The CMOS pixel of claim 1 wherein the CMOS pixel is either a PMOS pixel or an NMOS pixel.
15. A method of fabricating a CMOS pixel comprising:
implanting a multi-pinned (MP) implant layer into epitaxial silicon, wherein the implanting of the MP implant layer occurs substantially across the entire CMOS pixel; and
forming a five transistor pinned-photodiode pixel into the epitaxial silicon, wherein the five transistor pinned-photodiode pixel comprises a pinned photo-diode and at least one transfer gate, wherein the MP implant layer provides a pinning potential to pin elements of the CMOS pixel at multiple locations, and wherein a portion of the MP implant layer is comprised in the pinned-photodiode and another portion of the MP implant layer is under the at least one transfer gate.
16. The method claim 15 wherein implanting of the MP implant layer is to a depth of about at least 450 Angstroms.
17. The method of claim 15 wherein implanting of the MP implant is to a dose of about 1\xd71012 ionscm2 using about an energy of 20 keV to about 30 keV.
18. The method of claim 15 wherein the elements of the CMOS pixel comprise at least a pinned photodiode and a transfer gate, the MP implant layer facilitates passivating dark current in the MP implant layer beneath the transfer gate when the transfer gate is in an accumulation state and promotes charge transfer when the transfer gate is in a transfer state.
19. The method of claim 15 wherein the CMOS pixel is either a PMOS pixel or NMOS pixel.
20. The CMOS pixel of claim 1, wherein the pinned-photodiode comprises a pinning layer, and wherein the pinning layer is mixed with the portion of the MP implant layer comprised in the pinned-photodiode.
21. The CMOS pixel of claim 9, wherein the MP implant layer facilitates passivating dark current in the MP implant layer beneath the at least one transfer gate when the at least one transfer gate is in an inverted state and promotes charge transfer conditions when in a transfer state.
22. The CMOS pixel of claim 9, wherein the MP implant layer is operable to pin a surface of the epitaxial silicon to a pinning potential established by the MP implant layer at multiple locations within the CMOS pixel.
23. The CMOS pixel of claim 10, wherein the at least one transfer gate comprises a first gate and a second gate, and wherein the second gate, proximate the pinned photodiode, has a portion of the MP implant layer beneath the second gate.
24. The CMOS pixel of claim 23, further comprising a drain formed at least partially extending into the MP implant layer proximal to the second gate.
25. The CMOS pixel of claim 24, further comprising a control circuit for applying a potential to at least one of the at least one transfer gates, wherein the potential drives at least one of the at least one transfer gates into inversion to passivate dark current.
26. The CMOS pixel of claim 11, wherein the MP implant layer is implanted to a depth of about at least 450 Angstroms.
27. The CMOS pixel of claim 12, wherein the MP implant layer is implanted to a dose of about 1\xd71012 ionscm2 using about an energy of 20 keV to about 30 keV.
28. The CMOS pixel of claim 13, further comprising a barrier implant formed in the epitaxial silicon, wherein the barrier implant extends at least partially underlying the at least one transfer gate for providing additional charge collection capability to the pinned photodiode.
29. The CMOS pixel of claim 14, wherein the pinned-photodiode comprises a pinning layer, and wherein the pinning layer is mixed with the portion of the MP implant layer comprised in the pinned-photodiode.