Author: claimsbot

1. A packet memory system comprising:
a memory cell array for storing a predefined number of packets; each packet including a predetermined number of segments; each of said segments for defining a starting point of a readwrite memory access;
a packet decoder coupled to said memory cell array and receiving packet select inputs for selecting a packet;
a segment decoder coupled to said memory cell array and receiving segment select inputs for selecting a segment of said selected packet;
a data flow multiplexer coupled to said memory cell array for transferring data between a data bus and said memory cell array for said readwrite memory access;
command and mode registers receiving command, readwrite (RW) and chip select (CS) inputs for opening said selected packet for said readwrite memory access; and
responsive to said selected packet being opened, a readwrite segment command being issued for said selected segment of said selected packet for said readwrite memory access, and on said packet select inputs a length of said readwrite memory access being inputted.
2. A packet memory system as recited in claim 1 wherein each of said segments has a preprogrammed length.
3. A packet memory system as recited in claim 1 wherein each of said segments is defined for a cache line.
4. A packet memory system as recited in claim 1 wherein said memory cell array includes an array of dynamic random access memory (DRAM) cells.
5. A packet memory system as recited in claim 1 wherein said packet has a predetermined total packet length and each of said segments has a preprogrammed length from zero to said total packet length, and where the sum of each of said segments can not be greater than said total packet length.
6. A packet memory system as recited in claim 1 wherein said packet includes four segments and said segment decoder coupled to said memory cell array receives two segment select inputs for selecting one of said four segments.
7. A packet memory system as recited in claim 1 wherein said packet decoder coupled to said memory cell array receives said predefined number of packet select inputs for selecting one of said predefined number of packets.
8. A packet memory system as recited in claim 1 wherein said command inputs include a first command type and a second command type.
9. A packet memory system as recited in claim 8 wherein said first command type includes said open packet command, a close packet command, a refresh command and a self-refresh command.
10. A packet memory system as recited in claim 8 wherein said second command type includes said readwrite (RW) segment command, an open packet command, a close packet command, and a segment stop command.
11. A packet memory system as recited in claim 1 wherein said data flow multiplexer coupled to said memory cell array for transferring data between a data bus and said memory cell array includes a predetermined number of buses, each said bus connected between said data flow multiplexer and a respective one of said predetermined number of segments within said memory cell array.
12. A packet memory system as recited in claim 1 wherein a latency between said memory cell array and said data bus coupled to said data flow multiplexer is less than or equal to one clock cycle.
13. A packet memory system comprising:
a memory cell array including an array of dynamic random access memory (DRAM) cells for storing a predefined number of packets; each packet including a predetermined number of segments; each of said segments having a preprogrammed length; each of said segments for defining a starting point of a readwrite memory access;
a packet decoder coupled to said memory cell array and receiving packet select inputs for selecting a packet;
a segment decoder coupled to said memory cell array and receiving segment select inputs for selecting a segment of said selected packet;
a data flow multiplexer coupled to said memory cell array for transferring data between a data bus and said memory cell array for said readwrite memory access;
command and mode registers receiving command, readwrite (RW) and chip select (CS) inputs for opening said selected packet for said readwrite memory access; and
responsive to said selected packet being opened, a readwrite segment command being issued for said selected segment of said selected packet for said readwrite memory access, and on said packet select inputs a length of said readwrite memory access being inputted.
14. A packet memory system as recited in claim 13 wherein each of said segments is defined for a cache line.
15. A packet memory system as recited in claim 13 wherein said packet has a predetermined total packet length and each of said segments has a preprogrammed length from zero to said total packet length, and where the sum of each of said segments can not be greater than said total packet length.
16. A packet memory system as recited in claim 13 wherein said data flow multiplexer coupled to said memory cell array for transferring data between a data bus and said memory cell array includes a predetermined number of buses, each said bus connected between said data flow multiplexer and a respective one of said predetermined number of segments within said memory cell array.
17. A packet memory system as recited in claim 13 wherein a latency between said memory cell array and said data bus coupled to said data flow multiplexer is less than or equal to one clock cycle.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A composition comprising: one or more triboelectrically charged pigment particles dispersed in a polymer matrix.
2. The composition of claim 1 wherein the pigment particles comprise one or more of the following: TiO2, ZrO2, ZnO, Al2O3, BaSO4, CaCO3, an organic pigment, and an organometallic.
3. The composition of claim 1 wherein the particles are used in an electrophoretic display device.
4. The composition of claim 1 wherein the particles have an electrophoretic mobility and density for use in an electrochromic display.
5. The composition of claim 1 further including a dielectric fluid.
6. The composition of claim 1 wherein the composition comprises at least two groups of particles having different electrophoretic properties.
7. A method comprising:
charging pigment particles in a melted polymer matrix by movement of the pigment particles and polymer matrix across a substrate; and
cooling droplets released from the substrate to form electrophoretic particles with charged pigment particles dispersed in the polymer matrix.
8. The method of claim 7 where the electrophoretic particles have a shape that can be used in an electrophoretic display device.
9. The method of claim 7 where the pigment particles are charged by triboelectric charging.
10. The method of claim 7 where the electrophoretic particles comprise substantially spherical balls less than about 250 microns in diameter.
11. The method of claim 7 where the electrophoretic particles provide a switching speed in an electrophoretic cell with an about 300 micrometer average spacing between the electrodes of the cell of less than about 200 microseconds when the spherical balls are dispersed in an about 1 centistoke dielectric fluid and a square wave of about +300 to about \u2212300 volts is applied to the cell electrodes.
12. The method of claim 7 where the substrate is a heated spinning disk.
13. The method of claim 7 where the polymeric matrix has a melt viscosity less than about 50 centipoise.
14. The method of claim 7 where the polymeric matrix includes an additive that improves the tribocharging characteristics of the pigment.
15. An electrophoretic display comprising:
a cell having two opposed conductive plates separated from each other by an insulator to form a sealed cavity between the plates;
each plate having one or more electrodes and where at least one of the plates and the one or more electrodes are transparent;
wherein the cavity includes a suspension of an inert dielectric fluid mixed with electrophoretic particles;
wherein the electrophoretic particles are nearly neutrally buoyant in the dielectric fluid and include triboelectrically charged pigment particles dispersed in a polymeric matrix; and;
wherein the electrophoretic particles move in response to an electric field applied to the electrodes.
16. The device of claim 15 where the pigment particles are dispersed in a thermoplastic that has a viscosity of less than about 50 centipoise when heated to about 150\xb0 C.
17. The device of claim 15 where the dielectric fluid includes a dye.
18. The device of claim 15 where the dielectric fluid includes a first color or first achromatic color of electrophoretic particle that is positively charged and a second color or second achromatic color of electrophoretic particle that is negatively charged.
19. The device of claim 15 having a contrast ratio of 4.5 or more and a switching time of 200 milliseconds or less.
20. The device of claim 18 where the positively and negatively charged electrophoretic particles are suspended in a second dielectric fluid and encapsulated by a polymer shell to form one or more capsules, the capsules positioned between the cell plates.

1. A wiring structure for semiconductor device, comprising:
a wiring layer that includes copper as main component; and
a crystal grain promotion layer that contacts said wiring layer and promotes enlargement in a crystal grain of the wiring layer.
2. The wiring structure for semiconductor device according to claim 1, wherein the crystal grain of the wiring layer satisfies a relation of D>10\xd7L where D is an average grain diameter of crystal grain to be enlarged finally in the wiring layer and L is mean free path of electrons.
3. The wiring structure for semiconductor device according to claim 1, wherein the crystal grain promotion layer is disposed between the wiring layer and one of a semiconductor and a dielectric film.
4. The wiring structure for semiconductor device according to claim 3, wherein the crystal grain promotion layer has a good contact with the one of a semiconductor and dielectric film and the wiring layer and is of a material that has a low reactivity to the semiconductor or dielectric film and the wiring layer.
5. The wiring structure for semiconductor device according to claim 1, wherein the crystal grain promotion layer comprises one of a high melting point metal, a nitride of the high melting point metal, and a carbide of the high melting point metal.
6. A wiring structure for semiconductor device, comprising:
a wiring layer that includes copper as main component; and
a crystal grain promotion layer that contacts said wiring layer and promotes enlargement in a crystal grain of the wiring layer,
wherein the crystal grain promotion layer comprises a material selected from the group of titanium, tantalum, titanium nitrides, titanium carbides, tantalum nitrides and tantalum carbides.
7. The wiring structure for semiconductor device according to claim 1, wherein said crystal grain promotion layer comprises a metal with a melting point of at least 150\xb0 C.
8. The wiring structure for semiconductor device according to claim 1, wherein said crystal grain promotion layer comprises one of titanium, tantalum, zirconium, hafnium, vanadium, tungsten, niobium, molybdenum, a nitride of any of these and a carbide of any of these.
9. The wiring structure for semiconductor device according to claim 1, wherein an average grain diameter (D) of said crystal grain of said wiring layer is in a range from 7 to 8 times a width (W) of said wiring layer.
10. The wiring structure for semiconductor device according to claim 1, wherein said copper in said wiring layer comprises a (111) copper face.
11. The wiring structure for semiconductor device according to claim 1, wherein said copper comprises approximately a single crystal.
12. The wiring structure for semiconductor device according to claim 1, wherein said wiring layer is formed directly on said crystal grain promotion layer.
13. The wiring structure for semiconductor device according to claim 1, wherein said crystal grain promotion layer is formed on one of silicon, silicon nitride, silicon oxide, impurity-doped silicon, and an organic dielectric material.
14. The wiring structure for semiconductor device according to claim 1, wherein an average grain diameter of said crystal grain is at least 390 nm.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An integrated circuit comprising:
an electrical circuit layer; and
optical circuitry disposed over said electrical circuit layer, said optical circuitry comprising:
a layer of dielectric material deposited on a top surface of the electrical circuit layer;
a plurality of recesses disposed within said layer of dielectric material;
a layer of waveguide material deposited within each of said plurality of recesses, said waveguide material operable to propagate light;
a lens disposed over a first surface of at least one layer of waveguide material within at least one of said plurality of recesses;
a second layer of dielectric material having a plurality of second recesses, wherein one or more of said second recesses are disposed over said lens;
a second layer of waveguide material deposited within one or more of said plurality of second recesses; and
a second lens disposed over one or more of said second layers of waveguide material.
2. The integrated circuit as set forth in claim 1, wherein said optical circuitry further comprises a cladding layer deposited between the waveguide material and a sidewall of each recess, said cladding layer operable to enhance light propagation through the waveguide material.
3. The integrated circuit as set forth in claim 2, wherein said dielectric material comprises a material having a first refractive index, said waveguide material comprises a material having a second refractive index, and said cladding layer comprises a material having a third refractive index less than said first and second refractive indexes.
4. The integrated circuit as set forth in claim 2, wherein said dielectric material comprises a material having a first refractive index, said waveguide material comprises a material having a second refractive index, and said cladding layer comprises a material having a third refractive index greater than said first and second refractive indexes.
5. The integrated circuit as set forth in claim 2, wherein said cladding layer comprises at least one of silicon oxide or poly silicon.
6. The integrated circuit as set forth in claim 2, wherein said cladding layer comprises one or more alternating layers of a first cladding material having a first refractive index and a second cladding material having a second refractive index.
7. The integrated circuit as set forth in claim 6, wherein a first layer of said first cladding material is deposited directly over said sidewall.
8. The integrated circuit as set forth in claim 6, wherein said first refractive index is less than said second refractive index.
9. The integrated circuit as set forth in claim 6, wherein said first cladding material comprises at least one of dielectric material, Silica, silicon nitride, or silicon oxide.
10. The integrated circuit as set forth in claim 6, wherein said second cladding material comprises a Bragg cladding material.
11. The integrated circuit as set forth in claim 6, wherein said second cladding material comprises at least one of poly silicon, silicon oxide, or titanium dioxide.
12. The integrated circuit as set forth in claim 6, wherein said first and second cladding materials are deposited via a low pressure chemical vapor deposition process.
13. The integrated circuit as set forth in claim 1, wherein said optical circuitry further comprises a photonic source vertically aligned with one of said plurality of recesses, the layer of waveguide material deposited within said one of said plurality of recesses, and the lens disposed over the first surface of the layer of waveguide material deposited within said one of said plurality of recesses.
14. The integrated circuit as set forth in claim 1, wherein said optical circuitry further comprises a photonic drain vertically aligned with one of said plurality of recesses, the layer of waveguide material deposited within said one of said plurality of recesses, and the lens disposed over the first surface of the layer of waveguide material deposited within said one of said plurality of recesses.
15. The integrated circuit as set forth in claim 1, wherein said optical circuitry further comprises a light source vertically aligned with one of said plurality of recesses, the layer of waveguide material deposited within said one of said plurality of recesses, and the lens disposed over the first surface of the layer of waveguide material deposited within said one of said plurality of recesses.
16. The integrated circuit as set forth in claim 1, wherein said optical circuitry further comprises a photodetector vertically aligned with one of said plurality of recesses, the layer of waveguide material deposited within said one of said plurality of recesses, and the lens disposed over the first surface of the layer of waveguide material deposited within said one of said plurality of recesses.
17. The integrated circuit as set forth in claim 1, said first surface having a first curvature dishing, said first curvature dishing defining at least a partial curvature for said lens deposited on said first surface.
18. The integrated circuit as set forth in claim 1, wherein said lens has a curvature selected from the group consisting essentially of concave, convex, plano-convex, plano-concave, biconvex, biconcave, bi-planar, positive meniscus, and negative meniscus.
19. The integrated circuit as set forth in claim 1, wherein said electrical circuit layer comprises circuitry formed during front end of line semiconductor manufacturing.
20. The integrated circuit as set forth in claim 1, wherein said electrical circuit layer comprises circuitry formed during back end of line semiconductor manufacturing.
21. The integrated circuit as set forth in claim 1, wherein said optical circuitry is formed during back end of line semiconductor manufacturing.
22. The integrated circuit as set forth in claim 1, wherein said dielectric material comprises a material having a first refractive index and said waveguide material comprises a material having a second refractive index greater than said first refractive index.
23. The integrated circuit as set forth in claim 1, wherein said dielectric material comprises a material having a first refractive index and said waveguide material comprises a material having a second refractive index less than said first refractive index.
24. The integrated circuit as set forth in claim 1, wherein said dielectric material comprises silicon nitride or silicon oxide.
25. The integrated circuit as set forth in claim 1, wherein said waveguide material comprises poly silicon or silicon oxide.
26. The integrated circuit as set forth in claim 1, wherein said lens material comprises silicon nitride.
27. The integrated circuit as set forth in claim 1, wherein said optical circuitry further comprises a cladding layer deposited between said second layer of waveguide material and a sidewall of one or more of said second recesses.
28. The integrated circuit as set forth in claim 1, wherein one or more of said plurality of recesses, said layer of waveguide material, said lens, one or more of said second recesses, said second layer of waveguide material, and said second lens are vertically aligned to form a vertical waveguide.
29. An integrated circuit comprising:
first circuitry; and
optical circuitry disposed over said first circuitry, said optical circuitry comprising:
a first layer of dielectric material;
one or more first recesses disposed within said first layer of dielectric material;
a first layer of waveguide material deposited within each of said one or more first recesses, said waveguide material operable to propagate light;
a first lens disposed over a first surface of at least one first layer of waveguide material within at least one of said one or more first recesses;
a second layer of dielectric material having a plurality of second recesses, wherein one or more of said second recesses are disposed over said first lens;
a second layer of waveguide material deposited within one or more of said plurality of second recesses; and
a second lens disposed over one or more of said second layers of waveguide material.
30. The integrated circuit as set forth in claim 29, wherein said optical circuitry further comprises a cladding layer deposited between said second layer of waveguide material and a sidewall of one of said second recesses.
31. The integrated circuit as set forth in claim 29, wherein one or more of said first recesses, said first layer of waveguide material, said first lens, one or more of said second recesses, said second layer of waveguide material, and said second lens are vertically aligned to form a vertical waveguide.
32. An integrated circuit comprising:
an electrical circuit layer; and
optical circuitry disposed over said electrical circuit layer, said optical circuitry comprising:
a layer of dielectric material deposited on a top surface of the electrical circuit layer;
one or more recesses disposed within said layer of dielectric material;
a layer of waveguide material deposited within each of said one or more recesses, said waveguide material operable to propagate light;
a lens disposed over a first surface of at least one layer of waveguide material within at least one of said one or more recesses;
a second layer of dielectric material having one or more second recesses, wherein one or more of said one or more second recesses are disposed over said lens;
a second layer of waveguide material deposited within one or more of said one or more second recesses; and
a second lens disposed over one or more of said second layers of waveguide material.
33. The integrated circuit as set forth in claim 32, wherein said optical circuitry further comprises a cladding layer deposited between the waveguide material and a sidewall of each recess, said cladding layer operable to enhance light propagation through the waveguide material.
34. The integrated circuit as set forth in claim 33, wherein said dielectric material comprises a material having a first refractive index, said waveguide material comprises a material having a second refractive index, and said cladding layer comprises a material having a third refractive index less than said first and second refractive indexes.
35. The integrated circuit as set forth in claim 33, wherein said dielectric material comprises a material having a first refractive index, said waveguide material comprises a material having a second refractive index, and said cladding layer comprises a material having a third refractive index greater than said first and second refractive indexes.
36. The integrated circuit as set forth in claim 33, wherein said cladding layer comprises at least one of silicon oxide or poly silicon.
37. The integrated circuit as set forth in claim 33, wherein said cladding layer comprises one or more alternating layers of a first cladding material having a first refractive index and a second cladding material having a second refractive index.
38. The integrated circuit as set forth in claim 37, wherein a first layer of said first cladding material is deposited directly over said sidewall.
39. The integrated circuit as set forth in claim 37, wherein said first refractive index is less than said second refractive index.
40. The integrated circuit as set forth in claim 37, wherein said first cladding material comprises at least one of dielectric material, Silica, silicon nitride, or silicon oxide.
41. The integrated circuit as set forth in claim 37, wherein said second cladding material comprises a Bragg cladding material.
42. The integrated circuit as set forth in claim 37, wherein said second cladding material comprises at least one of poly silicon, silicon oxide, or titanium dioxide.
43. The integrated circuit as set forth in claim 32, wherein said optical circuitry further comprises a photonic source vertically aligned with one of said recesses, the layer of waveguide material deposited within said one of said recesses, and the lens disposed over the first surface of the layer of waveguide material deposited within said one of said recesses.
44. The integrated circuit as set forth in claim 32, wherein said optical circuitry further comprises a photonic drain vertically aligned with one of said recesses, the layer of waveguide material deposited within said one of said recesses, and the lens disposed over the first surface of the layer of waveguide material deposited within said one of said recesses.
45. The integrated circuit as set forth in claim 32, wherein said optical circuitry further comprises a light source vertically aligned with one of said recesses, the layer of waveguide material deposited within said one of said recesses, and the lens disposed over the first surface of the layer of waveguide material deposited within said one of said recesses.
46. The integrated circuit as set forth in claim 32, wherein said optical circuitry further comprises a photodetector vertically aligned with one of said recesses, the layer of waveguide material deposited within said one of said recesses, and the lens disposed over the first surface of the layer of waveguide material deposited within said one of said recesses.
47. The integrated circuit as set forth in claim 32, said first surface having a first curvature dishing, said first curvature dishing defining at least a partial curvature for said lens deposited on said first surface.
48. The integrated circuit as set forth in claim 32, wherein said dielectric material comprises a material having a first refractive index and said waveguide material comprises a material having a second refractive index greater than said first refractive index.
49. The integrated circuit as set forth in claim 32, wherein said dielectric material comprises a material having a first refractive index and said waveguide material comprises a material having a second refractive index less than said first refractive index.
50. The integrated circuit as set forth in claim 32, wherein said optical circuitry further comprises a cladding layer deposited between said second layer of waveguide material and a sidewall of one or more of said one or more second recesses.
51. The integrated circuit as set forth in claim 32, wherein one or more of said one or more recesses, said layer of waveguide material, said lens, one or more of said one or more second recesses, said second layer of waveguide material, and said second lens are vertically aligned to form a vertical waveguide.