Author: claimsbot

What is claimed is:

1. A polished glass disk medium substrate formed of a mixture of glass forming raw materials comprising
about 35% to about 50% by weight SiO2;
about 13% to about 15.5% by weight Al2O3;
about 10% to about 30% by weight MgO; and
about 5% to about 20% by weight TiO2.
2. The polished glass disk medium substrate according to claim 1, wherein the raw materials further comprise about 0.1% to about 8% by weight Li2O.
3. The polished glass disk medium substrate according to claim 1, wherein the raw materials further comprise about 0.1% to about 22% by weight ZnO.
4. The polished glass disk medium substrate according to claim 1, wherein the raw materials further comprise about 0.1% to about 5% by weight P2O5.
5. The polished glass disk medium substrate according to claim 1, wherein the raw materials further comprise about 0.1% to about 12% by weight ZrO2.
6. The polished glass disk medium substrate according to claim 1, wherein the raw materials further comprise about 0.1% to about 9% by weight CaO.
7. The polished glass disk medium substrate according to claim 1, wherein the raw materials further comprise about 0.1% to about 9% by weight Nb2O5.
8. The polished glass disk medium substrate according to claim 1, wherein the raw materials further comprise about 0.1% to about 9% by weight Ta2O5.
9. The polished glass disk medium substrate according to claim 1, wherein the raw materials further comprise about 0.1% to about 9% by weight K2O.
10. The polished glass disk medium substrate according to claim 1, wherein the raw materials further comprise about 0.1% to about 9% by weight B2O3.
11. The polished glass disk medium substrate according to claim 1, wherein the raw materials further comprise about 0.1% to about 9% by weight Y2O3.
12. The polished glass disk medium substrate according to claim 1, wherein the raw materials further comprise about 0.1% to about 9% by weight Sb2O3.
13. The polished glass disk medium substrate according to claim 1, wherein the raw materials further comprise about 0.1% to about 9% by weight As2O3.
14. The polished glass disk medium substrate according to claim 1, said raw materials consisting essentially of
about 35% to about 50% by weight SiO2;
about 13% to about 15.5% by weight Al2O3;
about 10% to about 30% by weight MgO;
about 5% to about 20% by weight TiO2.
15. The polished glass disk medium substrate according to claim 14, further containing one or more of the following:
about 0.1% to about 8% by weight Li2O;
about 0.1% to about 22% by weight ZnO;
about 0.1% to about 5% by weight P2O5;
about 0.1% to about 12% by weight ZrO2;
about 0.1% to about 9% by weight CaO;
about 0.1% to about 9% by weight Nb2O5;
about 0.1% to about 9% by weight Ta2O5;
about 0.1% to about 9% by weight K2O;
about 0.1% to about 9% by weight B2O3;
about 0.1% to about 9% by weight Y2O3;
about 0.1% to about 9% by weight Sb2O3; and
about 0.1% to about 9% by weight As2O3.
16. The polished glass disk medium substrate according to claim 14, wherein said substrate is essentially free of BaO, ZrO2, B2O3 and NiO.
17. The polished glass disk medium substrate according to claim 1, comprising crystalline phases and amorphous phases.
18. The polished glass disk medium substrate according to claim 17, wherein the crystalline phases represent about 50 to about 60 percent by weight of the total glass composition.
19. The polished glass disk medium substrate according to claim 17, comprising a crystalline phase of clinoenstatite.
20. The polished glass disk medium substrate according to claim 19, wherein the crystalline phase of clinoenstatite represents at least about 80 percent by weight of the crystalline phases.
21. The polished glass disk medium substrate according to claim 17, comprising a crystalline phase of enstatite.
22. The polished glass disk medium substrate according to claim 22, wherein the crystalline phase of enstatite represents less than or equal to about 20 percent by weight of the crystalline phases.
23. The polished glass disk medium substrate according to claim 17, comprising a crystalline phase of magnesium aluminum silicate.
24. The polished glass disk medium substrate according to claim 23, wherein the crystaline phase of magnesium aluminum silicate represents less than or equal to about 20 percent by weight of the crystalline phases.
25. The polished glass disk medium substrate according to claim 17, comprising a crystalline phase of Zn2Ti3O8.
26. The polished glass disk medium substrate according to claim 25, wherein the crystalline phase of Zn2Ti3O8 represents less than or equal to about 20 percent by weight of the crystalline phases.
27. The polished glass disk medium substrate according to claim 17, comprising a crystalline phase of Zn2TiO4.
28. The polished glass disk medium substrate according to claim 27, wherein the crystalline phase of Zn2TiO4 represents less than or equal to about 20 percent by weight of the crystalline phase.
29. The polished glass disk medium substrate according to claim 1, comprising a main crystalline phase of clinoenstatite and a secondary crystalline phase of enstatite.
30. The polished glass disk medium substrate according to claim 29, further comprising one or more of a crystalline phase of magnesium aluminum silicate, a crystalline phase of zinc titanium oxide, and a crystalline phase of zinc titanium oxide.
31. The polished glass disk medium substrate according to claim 1, wherein said glass substrate has a Young’s modulus of 110 or higher.
32. The polished glass disk medium substrate according to claim 1, wherein said substrate is prepared by heating glass forming raw materials to a temperature, T1, between about 500 and 680 C. to generate crystal nuclei; heating at a temperature, T2, between about 680 and abot 800 C. to grow crystal nuclei; and cooling to obtain crystallized glass.
33. A recording disk comprising the polished glass disk medium substrate defined in claim 1.
34. The recording disk according to claim 33, wherein said recording disk is a hard disk.
35. The recording disk according to claim 33, wherein said recording disk is a magnetic disk.
36. The recording disk according to claim 33, wherein said recording disk is an optical disk.
37. The recording disk according to claim 33, wherein said recording disk is a magnetic-optical disk.
38. A method of making a glass disk medium substrate comprising:
heating glass forming raw materials to a temperature sufficiently high to melt the raw materials;
forming a disk medium substrate; and
crystallizing the disk medium substrate, wherein said crystallizing comprises heating the disk medium substrate to a temperature, T1, between about 500 and 680 C. to generate crystal nuclei; heating at a temperature, T2, between about 680 and about 800 C. to grow crystal nuclei; and cooling to obtain crystalized glass.
39. The method according to claim 38, further comprising polishing said glass disk medium substrate.
40. The method according to claim 38, wherein said glass disk medium substrate formed has a Young’s modulus of 110 or higher.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A sense amplifier, comprising
a bias circuit configured to provide a bias voltage having a magnitude responsive to maintaining a substantially constant loop gain; and
an amplifier stage coupled to the bias circuit to receive the bias voltage and configured to amplify a input current at an input-output node, the current amplifier stage having a loop gain controlled at least in part to the bias voltage.
2. The sense amplifier of claim 1 wherein the bias circuit comprises a beta multiplier reference circuit.
3. The sense amplifier of claim 1 wherein the bias circuit comprises:
a first pair of transistors having gates coupled together, one of the transistors having a gate coupled to its source;
a second pair of transistors having gates coupled together, one of the transistors having a gate coupled to its drain and a bias voltage output node from which the bias voltage is provided; and
a resistance coupled to the transistor of the second pair not having a gate coupled to its drain.
4. The sense amplifier of claim 1, wherein the current amplifier stage comprises:
a pair of transistors having gates cross-coupled to a drain of the other transistor;
a pair of bias transistors, each coupled to a source of a respective one of the pair of transistors and further coupled to receive the bias voltage from the bias circuit;
a pair of resistances, each coupled to the drain of a respective one of the pair of transistors, the loop gain of the current amplifier stage matching a loop gain of the bias voltage circuit.
5. The sense amplifier of claim 4 where having a magnitude and each of the resistance of the amplifier stage comprises a resistance having a magnitude equal to the magnitude of the resistance of the bias circuit.
6. The sense amplifier of claim 4 wherein the bias circuit comprises at least one transistor having transistor dimensions and wherein each of the bias transistors of the amplifier stage have transistor dimensions the same as the transistor dimensions of the at least one transistor of the bias circuit.
7. The sense amplifier of claim 1 wherein the current amplifier comprises a differential current amplifier stage configured to sense and amplify a differential input current at differential input-output nodes.
8. The sense amplifier of claim 1 wherein the current amplifier and bias circuit are configured to have substantially the same loop gain.
9. A memory, comprising:
an array of memory cells;
readwrite circuitry coupled to the memory cells and configured to amplify read data read from the array, the readwrite circuitry including a sense amplifier, comprising:
a bias circuit configured to provide a bias voltage having a magnitude responsive to maintaining a substantially constant loop gain; and
a current amplifier stage coupled to the bias circuit to receive the bias voltage and configured to amplify input signals representing read data from the array that are coupled to an input-output node, the current amplifier stage having a loop gain controlled at least in part to the bias voltage.
10. A method for amplifying a current input, comprising
providing a bias voltage;
adjusting a magnitude of the bias voltage to maintain a substantially constant loop gain of a differential current mode amplifier; and
sensing a differential input and amplifying the same.
11. The method of claim 10, further latching a sensed state following the sensing of the differential input.
12. The method of claim 10 wherein providing a bias voltage comprises providing a bias voltage from a beta multiplier reference circuit.
13. A sense amplifier, comprising:
a sense amplifier stage configured to receive differential input signals and amplify the same, the current amplifier having a loop gain;
a latch mode circuit coupled to the sense amplifier stage configured to control the sense amplifier stage to latch a sensed state; and
a loop gain control circuit coupled to the sense amplifier stage and configured to control the loop gain of the sense amplifier stage.
14. The sense amplifier of claim 13 wherein the sense amplifier stage comprises a sense amplifier stage having a loop gain set according to a bias voltage and wherein the loop gain control circuit comprises a bias circuit configured to generate the bias voltage to control the loop gain of the sense amplifier stage.
15. The sense amplifier of claim 14 wherein the bias circuit comprises a beta multiplier reference circuit.
16. The sense amplifier of claim 14 wherein the bias circuit comprises a bias circuit configured to maintain a substantially constant loop gain and generate a bias voltage in response thereto.
17. The sense amplifier of claim 13 wherein the latch mode circuit is configured to increase the loop gain of the amplifier stage.

1. A semiconductor memory device comprising:
a semiconductor substrate including a plane portion expanding in a first direction and a second direction perpendicular to the first direction, a fin portion formed on an upper surface of the plane portion and expanding in the first direction and a stacking direction, and a pillar portion formed on an upper surface of the fin portion and extending in the stacking direction;
a first gate electrode formed on a first gate insulating layer on a side surface of the fin portion, and extending in the first direction;
a second gate electrode formed on a second gate insulating layer on a side surface of the pillar portion, and extending in the second direction;
a variable-resistance element formed on an upper surface of the pillar portion; and
an interconnection formed on an upper surface of the variable-resistance element.
2. The device of claim 1, wherein the variable-resistance element comprises:
a storage layer as a ferromagnetic layer having a variable magnetization direction;
a reference layer as a ferromagnetic layer having an invariable magnetization direction; and
a tunnel barrier layer as a nonmagnetic layer formed between the storage layer and the reference layer.
3. The device of claim 1, wherein the fin portion, the first gate insulating layer, and the first gate electrode form a first selection transistor, and the pillar portion, the second gate insulating layer, and the second gate electrode form a second selection transistor.
4. The device of claim 3, wherein when performing various operations on the variable-resistance element, a potential difference is produced between the plane portion and the interconnection while the first selection transistor and the second selection transistor are turned on.
5. The device of claim 1, further comprising an insulating layer formed between the first gate electrode and the plane portion.
6. The device of claim 1, further comprising an insulating layer formed between the second gate electrode and the first gate electrode.
7. The device of claim 1, further comprising an epitaxial layer formed between the pillar portion and the variable-resistance element, and having a planar area larger than those of the pillar portion and the variable-resistance element.
8. The device of claim 1, wherein the interconnection extends in the first direction.
9. The device of claim 1, wherein the interconnection expands in the first direction and the second direction.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1-15. (canceled)
16. A transmission line having thickness, comprising:
first and second multilayer conductors, each of the multilayer conductors including:
at least one separation dielectric layer and a plurality of conductor layers stacked in an alternating manner in the thickness direction, the plurality of conductor layers electrically coupled in parallel, each of the plurality of conductor layers including:
a first conductor sublayer, and
a second conductor sublayer separated from the first conductor sublayer by a sublayer dielectric layer in the thickness direction, the second conductor sublayer at least partially overlapping with the first conductor sublayer, as seen when viewed cross-sectionally in the thickness direction;
the first multilayer conductor mirroring the second multilayer conductor across a center axis of the transmission line, the center axis extending in a lengthwise direction that is orthogonal to the thickness direction.
17. The transmission line of claim 16, wherein in each of the multilayer conductors:
each of the plurality of conductor layers has a respective area of overlap of the first and second conductor sublayers of the conductor layer, as seen when viewed cross-sectionally in the thickness direction; and
at least two of the plurality of conductor layers have respective areas of overlap of different sizes.
18. The transmission line of claim 16, wherein, in each of the multilayer conductors:
the plurality of conductor layers comprises M conductor layers, where M is an integer greater than one;
a first conductor layer of the M conductor layers has a capacitive reactance of X1;
a second conductor layer of the M conductor layers has a capacitive reactance of X2;
the first conductor layer is a closest conductor layer of the M conductor layers to the center axis of the transmission line;
the second conductor layer is a second closest conductor layer of the M conductor layers to the center axis of the transmission line;
X2=X1\u2212(M\u22122+1)XLH; and
XLH is an incremental inductive reactance of each of the M conductor layers.
19. An assembly, comprising:
a multilayer conductor, including:
at least one separation dielectric layer and a plurality of conductor layers stacked in an alternating manner, each of the plurality of conductor layers including:
a first conductor sublayer, and
a second conductor sublayer separated from the first conductor sublayer by a sublayer dielectric layer, the second conductor sublayer at least partially overlapping with the first conductor sublayer; and
a magnetic core adjacent to at least part of the multilayer conductor.
20. The assembly of claim 19, wherein:
the at least one separation dielectric layer and the plurality of conductor layers are concentrically stacked in an alternating manner around a common axis;
the magnetic core includes a center post; and
the common axis forms a loop around the center post and around a center axis of the multilayer conductor.
21. The assembly of claim 20, the multilayer conductor having a toroidal shape.
22. The assembly of claim 21, wherein:
each first conductor sublayer forms a first discontinuity along the common axis, such that the first conductor sublayer does not completely encircle the center axis;
each second conductor sublayer forms a second discontinuity along the common axis, such that the second conductor sublayer does not completely encircle the center axis; and
each first discontinuity is angularly displaced from each second discontinuity around the center axis.
23. The assembly of claim 19, wherein:
the at least one separation dielectric layer and the plurality of conductor layers are concentrically stacked in an alternating manner around a center axis;
each first conductor sublayer forms a first discontinuity, such that the first conductor sublayer does not completely encircle the center axis;
each second conductor sublayer forms a second discontinuity, such that the second conductor sublayer does not completely encircle the center axis;
each first discontinuity is angularly displaced from each second discontinuity around the center axis;
the magnetic core comprises:
first and second end magnetic elements separated in a lengthwise direction parallel to the center axis, and
an outer ring disposed around the center axis, the outer ring joining the first and second end magnetic elements in the lengthwise direction; and

the multilayer conductor is disposed (a) within the outer ring, and (b) between the first and second end magnetic elements.
24. The assembly of claim 23, the multilayer conductor having a cylindrical shape.
25. The assembly of claim 24, further comprising a magnetic center post disposed along the center axis and joining the first and second end magnetic elements in the lengthwise direction.
26. The assembly of claim 25, the first and second end magnetic elements formed of a magnetic material having a first permeability, and the magnetic center post formed of a magnetic material having a second permeability, the first permeability being larger than the second permeability.
27. The assembly of claim 25, the magnetic center post comprising a plurality of discrete magnetic elements separated from each other in the lengthwise direction.
28. The assembly of claim 19, wherein:
the magnetic core includes:
an outer ring, and
a center post within the outer ring and extending along a center axis, the center axis extending in a thickness direction;

the at least one separation dielectric layer and the plurality of conductor layers are stacked in an alternating manner in the thickness direction;
the first and second conductor sublayers are concentrically disposed around the center post; and
the multilayer conductor is disposed within the outer ring.
29. The assembly of claim 28, wherein:
each first conductor sublayer is a foil conductor having a C-shape, as seen when viewed cross-sectionally in the thickness direction; and
each second conductor sublayer is a foil conductor having an inverted C-shape, as seen when viewed cross-sectionally in the thickness direction.
30. The assembly of claim 29, wherein:
each first conductor sublayer forms a first notch;
each second conductor sublayer forms a second notch; and
each first notch is angularly displaced from each second notch around the center axis.
31. The assembly of claim 30, wherein in each of the plurality of conductor layers, the first conductor sublayer, the second conductor sublayer, and the sublayer dielectric layer are stacked in the thickness direction.
32. The assembly of claim 30, at least two adjacent conductor layers of the plurality of conductor layers being angularly offset from each other around the center axis.
33. The assembly of claim 32, wherein:
the magnetic core further includes a base;
the center post and the outer ring are disposed on the base in the thickness direction, to form a recess in the magnetic core;
the recess is disposed around the common axis; and
the multilayer conductor is disposed in the recess.
34. The assembly of claim 33, further comprising one or more cooling channels disposed in the recess between the plurality of conductor layers and a bottom surface of the recess, the bottom surface of the recess being formed by the base of the magnetic core, the one or more cooling channels adapted to carry a cooling liquid.
35. The assembly of claim 34, further comprising a heat sink plate disposed between the plurality of conductor layers and the bottom surface of the recess, in the thickness direction.
36. The assembly of claim 28, the magnetic core further including a base ring and a top ring opposing each other in the thickness direction, each of the outer ring and the center post joining the base ring and the top ring.
37. The assembly of claim 19, further comprising an alternating current electric power source electrically coupled to at least one of the conductor sublayers.
38-44. (canceled)