Author: claimsbot

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising: forming a light reflective layer, an anti-reflective coating layer over the light-reflective layer, and a material over the anti-reflective coating layer; and using a non-polymerizing oxygen-rich fluorocarbon chemistry to selectively etch the anti-reflective coating layer.
2. A method for manufacturing, according to claim 1, wherein the anti-reflective coating layer is selectively etched with respect to the material over the anti-reflective coating layer.
3. A method for manufacturing, according to claim 1, wherein the anti-reflective coating layer is selectively etched with respect to the light reflective layer.
4. The method of claim 1, wherein the oxygen rich fluorocarbon chemistry includes CHF3.
5. The method of claim 1, wherein the oxygen rich fluorocarbon chemistry includes a relatively large amount of oxygen and a relatively small amount of CHF3.
6. The method of claim 1, wherein the oxygen rich fluorocarbon chemistry includes about 45 ccm of oxygen, and about 5 ccm of CHF3.
7. The method of claim 1, wherein selectively etching the semiconductor device includes etching at low power.
8. The method of claim 1, wherein selectively etching the semiconductor device includes the use of an upper electrode and a lower electrode, wherein the upper electrode is at a power setting of about 200 watts, and the lower electrode is at a power setting of about 100 watts.
9. The method of claim 1, wherein the semiconductor further comprises a photoresist layer, and wherein a significant amount of the resist is ashed while selectively etching the anti-reflective coating layer.
10. The method of claim 1, wherein the anti-reflective coating layer includes SiON, and wherein etching the anti-reflective coating layer includes etching the SiON.
11. The method of claim 1, wherein the light-reflective layer includes TiN, and wherein etching the anti-reflective coating layer leaves the TiN intact.
12. The method of claim 1, wherein the material over the anti-reflective coating layer includes oxide, and wherein etching the anti-reflective coating layer does not include etching the oxide.
13. The method of claim 1, wherein the material over the anti-reflective coating layer includes oxide, wherein the light-reflective layer includes a metal film, and wherein selectively etching the anti-reflective coating layer does not include etching the oxide or the metal film.
14. A method for manufacturing a semiconductor device, comprising: forming a light reflective layer, an anti-reflective coating layer over the light-reflective layer, and a material over the anti-reflective coating layer;
etching material over the anti-reflective coating layer and exposing the antireflective coating layer; and
using a non-polymerizing oxygen-rich fluorocarbon chemistry to selectively etch the anti-reflective coating layer.
15. A method for manufacturing a semiconductor device, according to claim 14, the semiconductor device further including a photoresist layer over the material over the anti-reflective coating layer, wherein etching material over the anti-reflective coating layer includes etching the resist, the method further comprising ashing the resist.
16. A method for manufacturing a semiconductor device, according to claim 14, wherein the light reflective layer remains intact.
17. A method for manufacturing a semiconductor device, according to claim 14, wherein the material over the anti-reflective layer remains intact during the etching of the anti-reflective coating layer.
18. A method for manufacturing a semiconductor device, wherein the semiconductor device includes a light reflective layer, an anti-reflective coating layer over the light-reflective layer, and a material over the anti-reflective coating layer, the method comprising:
using non-polymerizing means to selectively etch the anti-reflective coating layer with respect to the light-reflective layer and the material over the anti-reflective coating layer.
19. A semiconductor device manufactured according to claim 18.
20. A semiconductor device manufactured according to claim 1.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A method for marking a semiconductor device, comprising:
providing energy reactive marking material over a surface of the semiconductor device; and
exposing at least selected portions of at least one of said surface and said energy reactive marking material to energy to form of a mark on said surface without substantially creating an imprint in said surface.
2. The method of claim 1, wherein said providing comprises directing a stream of said energy reactive marking material at least proximate selected portions of said surface.
3. The method of claim 1, wherein said providing comprises disposing an energy reactive marking material comprising a pigment onto said surface.
4. The method of claim 1, wherein said providing comprises disposing a quickly curing energy reactive marking material onto said surface.
5. The method of claim 1, wherein said providing comprises dispensing said energy reactive marking material onto said surface.
6. The method of claim 1, wherein said providing comprises rolling said energy reactive marking material onto said surface.
7. The method of claim 1, wherein said exposing comprises placing the packaged semiconductor device in a path of an energy beam.
8. The method of claim 7, further comprising translating said energy with said stream of said energy reactive marking material.
9. The method of claim 1, wherein said exposing effects a color reaction of said energy reactive marking material.
10. The method of claim 1, wherein said exposing effects an absorption of energy by said energy reactive marking material.
11. The method of claim 1, wherein said exposing and said providing form said mark with a non-wet finish.
12. The method of claim 1, wherein said exposing comprises exposing said selected portions to a laser beam.
13. The method of claim 1, wherein said exposing comprises exposing said selected portions to focused light.
14. The method of claim 1, wherein said exposing comprises exposing said selected portions to heat.
15. The method of claim 1, further comprising inspecting a quality of said mark.
16. The method of claim 15, further comprising rejecting the packaged semiconductor device if said mark is not within selected quality control parameters.
17. The method of claim 1, further comprising exposing said selected portions to a coolant either during or immediately subsequent to said exposing at least selected portions to energy.
18. The method of claim 1, wherein said providing and said exposing occur without damaging or decomposing said surface.
19. The method of claim 1, wherein said exposing is effected either substantially simultaneously with said providing or immediately thereafter.
20. The method of claim 1, wherein said exposing and said providing effect at least one of fusing and bonding energy reactive marking material to said surface.
21. The method of claim 1, further comprising removing an unused quantity of said energy reactive marking material from said surface.
22. A semiconductor device including a surface with a marking thereon, said marking comprising energy-reacted material on said surface without being substantially recessed in said surface.
23. The semiconductor device of claim 22, wherein said energy-reacted material comprises a pigment.
24. The semiconductor device of claim 22, wherein said energy-reacted material of said marking is at least partially laterally surrounded by unreacted energy-reactive material.
25. The semiconductor device of claim 24, wherein a color of said energy-reacted material is visibly different from a color of said unreacted energy-reactive material.
26. The semiconductor device of claim 22, wherein said marking has a non-wet finish.
27. The semiconductor device of claim 22, wherein regions of said surface beneath and laterally adjacent said marking are substantially free of decomposition and damage.
28. The semiconductor device of claim 22, wherein said marking is at least one of bonded or fused to said surface.
29. The semiconductor device of claim 22, wherein said surface on which said marking is located comprises a surface of a packaging material.
30. The semiconductor device of claim 22, wherein said surface on which said marking is located comprises a surface of a semiconductor die.

1. An information processing apparatus comprising:
a main body;
an optical disc drive provided in the main body, the optical disc drive configured to output an eject signal to an outside in response to an operation of an eject button; and
a drive management module provided in the main body, the drive management module configured to supply power to the optical disc drive when the eject signal is received from the optical disc drive which is in a power-off state, to determine, after supplying the power to the optical disc drive, whether the optical disc drive is in a ready state or not, and to send to a signal instructing opening of a tray of the optical disc drive when it is determined that the optical disc drive is in the ready state.
2. The information processing apparatus of claim 1, wherein the drive management module is configured to power off the optical disc drive when a non-use state of the optical disc drive has continued for a predetermined period.
3. The information processing apparatus of claim 1, wherein the drive management module is configured to power off the optical disc drive when an event of requesting power-off of the optical disc drive is occurred.
4. The information processing apparatus of claim 1, wherein the drive management module is configured to determine whether the main body is shaking or not by using an acceleration sensor in the main body when the eject signal is received from the optical disc drive which is in the power-off state, and to supply the power to the optical disc drive if the main body is not shaking.
5. An information processing apparatus comprising:
a main body;
an optical disc drive provided in the main body, the optical disc drive configured to output an eject signal to an outside, the eject signal being generated by an operation of an eject button regardless of whether the optical disc drive is in a power-on state or not; and
a drive management module provided in the main body, the drive management module configured to power off the optical disc drive, to supply power to the optical disc drive when the eject signal is received from the optical disc drive which is in a power-off state, to determine, after supplying the power to the optical disc drive, whether the optical disc drive is in a ready state or not, and to send to a signal instructing opening of a tray of the optical disc drive when it is determined that the optical disc drive is in the ready state.
6. The information processing apparatus of claim 5, wherein the drive management module is configured to determine whether the main body is shaking or not by using an acceleration sensor in the main body when the eject signal is received from the optical disc drive which is in the power-off state, and to supply the power to the optical disc drive if the main body is not shaking.
7. A drive control method of controlling an optical disc drive in an information processing apparatus, the method comprising:
powering off the optical disc drive configured to output an eject signal to an outside in response to an operation of an eject button;
supplying power to the optical disc drive when the eject signal is received from the optical disc drive which is in a power-off state;
determining, after supplying the power to the optical disc drive, whether the optical disc drive is in a ready state or not, and
sending to a signal instructing opening of a tray of the optical disc drive when it is determined that the optical disc drive is in the ready state.
8. The drive control method of claim 7, further comprising determining whether the information processing apparatus is shaking or not by using an acceleration sensor in the information processing apparatus when the eject signal is received from the optical disc drive which is in the power-off state, wherein the supplying the power to the optical disc drive is performed if the information processing apparatus is not shaking.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An apparatus for extracting data from virtually concatenated (VCAT) plesiochronous digital hierarchy (PDH) streams carried in a synchronous digital hierarchy (SDH) signal, comprising:
an SDH overhead and pointer processor coupled to a SONET network;
a first telecom bus coupled to said SDH overhead and pointer processor;
a second telecom bus coupled to an SDH VCAT demapper;
a plurality of PDH units coupled between said first telecom bus and said second telecom bus, said plurality of PDH units providing PDH demapping and PDH frame synchronization according to a gapped clock produced by said PDH demapping to generate at least one serialized bit stream as well as providing serial to parallel conversion of said at least one serialized bit stream into bytes for supply to said second telecom bus;
a signal path connecting said first telecom bus and said second telecom bus, said signal path distinct from said plurality of PDH units; and
a configuration block for selectively controlling operation of said SDH VCAT demapper in one of a first mode and second mode, wherein
in said first mode, bytes produced by said SDH overhead and pointer processor are supplied to said SDH VCAT demapper over said first telecom bus, said signal path and said second telecom bus, and
in said second mode, bytes produced by said SDH overhead and pointer processor are supplied to said plurality of PDH units over said first telecom bus for processing and output to said SDH VCAT demapper over said second telecom bus;

wherein said SDH VCAT demapper deskews members of a virtual concatenated group (VCG) associated with frames containing virtual concatenation link capacity adjustment scheme information (VLI) by
selecting an acceptable delay which is less than the maximum compensable delay between members,
dividing each VLI frame into chunks,
assigning each chunk a number based on the multi-frame indicator (MFI) range and the number of chunks per VLI frame, and
temporarily storing chunks in a memory at an address dictated by a remainder function, the remainder function operating on the acceptable delay and a respective chunk number.
2. An apparatus according to claim 1, further comprising:
a GFP demapper coupled to said SDH VCAT demapper.
3. An apparatus according to claim 2, further comprising:
an Ethernet MAC coupled to said GFP demapper.
4. An apparatus according to claim 1, wherein:
said PDH units include PDH demappers and PDH frame synchronizers.
5. An apparatus according to claim 4, further comprising:
a control decoder coupled to said first telecom bus, to said SDH VCAT demapper, and to said PDH demappers.
6. An apparatus according to claim 5, further comprising:
a low order pointer processor coupled to said first telecom bus, to said control decoder, and to said SDH VCAT demapper.
7. A method according to claim 1, wherein:
the remainder function includes long division.
8. A method according to claim 7, wherein:
the long division is performed iteratively before a remainder is determined and the remainder is used to address the memory.
9. A method according to claim 7, wherein:
the divisor of the long division is configurable.
10. A method according to claim 1, wherein:
the memory address for temporary storage of chunks is calculated according to the equation
Address(i)=(Chunk_Value%Address_Range_for_VCG)+i*Address_Range_for_VCG
where \u201ci\u201d is the member number, \u201c%\u201d is a remainder function and Address_Range_for_VCG is the maximum delay to be compensated.
11. A method for extracting data from virtually concatenated (VCAT) plesiochronous digital hierarchy (PDH) streams carried in a synchronous digital hierarchy (SDH) signal, comprising:
processing the SDH signal with an SDH overhead and pointer processor to generate bytes corresponding thereto;
in a first mode, transferring bytes generated by the SDH overhead and pointer processor to a first telecom bus and then to a second telecom bus over a signal path connecting said first telecom bus to said second telecom bus for output to an SDH VCAT demapper coupled to said second telecom bus; and
in a second mode, transferring bytes generated by the SDH overhead and pointer processor to a first telecom bus and then to a plurality of PDH units coupled to the first telecom bus, said plurality of PDH units providing PDH demapping and PDH frame synchronization according to a gapped clock produced by said PDH demapping to generate at least one serialized bit stream as well as providing serial to parallel conversion of said at least one serialized bit stream into bytes for supply to said second telecom bus and output to said SDH VCAT demapper coupled to said second telecom bus;
wherein said SDH VCAT demapper deskews members of a virtual concatenated group (VCG) associated with frames containing virtual concatenation link capacity adjustment scheme information (VLI) by
selecting an acceptable delay which is less than the maximum compensable delay between members,
dividing each VLI frame into chunks,
assigning each chunk a number based on the multi-frame indicator (MFI) range and the number of chunks per VLI frame, and
temporarily storing chunks in a memory at an address dictated by a remainder function, the remainder function operating on the acceptable delay and a respective chunk number.
12. A method according to claim 11, further comprising:
demapping GFP frames output from said SDH VCAT demapper.
13. The method according to claim 12, further comprising:
extracting Ethernet frames from the GFP frames.
14. A method according to claim 11, wherein:
the remainder function includes long division.
15. A method according to claim 14, wherein:
the long division is performed iteratively before a remainder is determined and the remainder is used to address the memory.
16. A method according to claim 14, wherein:
the divisor of the long division is configurable.
17. A method according to claim 11, wherein:
the memory address for temporary storage of chunks is calculated according to the equation
Address(i)=(Chunk_Value%Address_Range_for_VCG)+i*Address_Range_for_VCG
where \u201ci\u201d is the member number, \u201c%\u201d is a remainder function and Address_Range_for_VCG is the maximum delay to be compensated.
18. A method for processing a synchronous digital hierarchy (SDH) signal carrying a virtual concatenated group (VCG), the VCG associated with frames containing virtual concatenation link capacity adjustment scheme information (VLI), the method comprising:
a) providing a demapper that processes members of the VCG; and
b) operating the demapper to deskew members of the VCG by
i) selecting an acceptable delay which is less than the maximum compensable delay between members;
ii) dividing each VLI frame into chunks;
iii) assigning each chunk a number based on the multi-frame indicator (MFI) range and the number of chunks per VLI frame; and
iv) temporarily storing chunks in a memory at an address dictated by a remainder function, the remainder function operating on the acceptable delay and a respective chunk number.
19. A method according to claim 18, wherein:
the remainder function includes long division.
20. A method according to claim 19, wherein:
the long division is performed iteratively before a remainder is determined and the remainder is used to address the memory.
21. A method according to claim 19, wherein:
the divisor of the long division is configurable.
22. A method according to claim 18, wherein
the memory address for temporary storage of chunks is calculated according to the equation
Address(i)=(Chunk_Value%Address_Range_for_VCG)+i*Address_Range_for_VCG
where \u201ci\u201d is the member number, \u201c%\u201d is a remainder function and Address_Range_for_VCG is the maximum delay to be compensated.