Author: claimsbot

1. A method for automatic detection of defects in TSV vias formed in a layer of semiconductor material, this detection taking place before stacking this layer with a plurality of other layers of semiconductor material for the design of a multilayer chip integrated circuit, including:
measurement on each of said TSV vias of at least one parameter derived from an electrical characteristic of the TSV vias,
detection of defects in said TSV vias according to a comparison of the parameters measured with at least one reference parameter,
calculating said at least one reference parameter using the measured parameters,

wherein said at least one parameter measured on each of the TSV vias includes an oscillation frequency value derived from a capacitive characteristic of the TSV vias.
2. The method for automatic detection of defects in TSV vias as claimed in claim 1, wherein the calculation of said at least one reference parameter comprises:
the determination, based on the parameters measured, of an expected value of the parameter to be measured on each of said TSV vias, this expected value being considered to be characteristic of a TSV via without defects, and
the calculation of said at least one reference parameter by applying a predefined and programmable permitted deviation parameter relative to this expected value.
3. The method for automatic detection of defects in TSV vias as claimed in claim 2, wherein the measurement on each of said TSV vias of an oscillation frequency derived from a capacitive characteristic of the TSV vias includes the following steps:
connection of a set of ring oscillators to all the TSV vias formed in the layer of semiconductor material, each ring oscillator being connected to at least one TSV via,
sequential selection of each of said ring oscillators,
sequential measurement of an oscillation frequency of each ring oscillator selected.
4. The method for automatic detection of defects in TSV vias as claimed in claim 2, wherein:
the expected value, annotated FMIN, is the lowest of the oscillation frequencies measured,
the permitted deviation parameter, annotated TTT, is expressed as a percentage of the expected value, and
said at least one reference parameter, annotated FREF, is a threshold frequency calculated as follows:
FREF=FMIN\xb7(1+TTT),
defects being detected in said TSV vias once a measured oscillation frequency exceeds this threshold frequency.
5. The method for automatic detection of defects in TSV vias as claimed in claim 2, wherein:
the expected value, annotated FMOY, is the mean of the oscillation frequencies measured,
the permitted deviation parameter, annotated TTT, is expressed as a percentage of the expected value, and
said at least one reference parameter, annotated FREF\u2212INF, FREF\u2212SUP, consists of the lower and upper limits of a frequency interval calculated as follows:
FREF\u2212INF=FMOY\xb7(1\u2212TTT) and FREF\u2212SUP=FMOY\xb7(1+TTT),
defects being detected in said TSV vias once a measured oscillation frequency is outside this interval.
6. A device for automatic detection of defects in TSV vias formed in a layer of semiconductor material, for a detection taking place before stacking this layer with a plurality of other layers of semiconductor material for the design of a multilayer chip integrated circuit, comprising:
means for measuring on each of said TSV vias at least one parameter derived from an electrical characteristic of the TSV vias,
means for detecting defects in said TSV vias according to a comparison of the parameters measured with at least one reference parameter,
means for calculating said at least one reference parameter based on the parameters measured,

wherein said at least one parameter measured on each of the TSV vias comprises an oscillation frequency value derived from a capacitive characteristic of the TSV vias.
7. The device for automatic detection of defects in TSV vias as claimed in claim 6, wherein the measuring means include a set of ring oscillators connected to all the TSV vias formed in the layer of semiconductor material, each ring oscillator being connected to at least one TSV via.
8. The device for automatic detection of defects in TSV vias as claimed in claim 7, wherein the calculating means include:
a counter of a number of rising edges of an oscillation signal of a ring oscillator selected sequentially for a predefined and programmable counting time, for the sequential supply of an oscillation frequency value,
a computer of at least one expected value of the oscillation frequency to be measured on each of said ring oscillators, this expected value being considered to be characteristic of a ring oscillator connected to at least one TSV via without defects, and of at least one reference frequency by applying a predefined and programmable permitted deviation parameter relative to this expected value.
9. A system for automatic detection of defects in TSV vias, comprising:
a detection device as claimed claim 6, and

a module for controlling access, from an external tester, to the detection device according to the IEEE 1149.1 standard or JTAG standard.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

I claim:

1. A placket closure comprising:
a first member having at least one pair of spaced apart, parallel rails, each rail having a bead lip; and
a second member having at least one rail having a bead head, the bead head being positionable between the bead lips of said first member in order to form an interlocking engagement; and
means for attaching said first member and said second member to respective sides of a garment placket;
whereby said first member and said second member provide the placket with a releasable closure for opening and closing the placket.
2. The placket closure according to claim 1, wherein said bead head has a diamond shaped cross-section.
3. The placket closure according to claim 2, wherein each of the bead lips has a semi-diamond shaped cross-section, said pair of rails defining a diamond-shaped channel.
4. The placket closure according to claim 1, wherein said bead head has a circular shaped cross-section.
5. The placket closure according to claim 4, wherein each said bead lip has a circular shaped cross-section.
6. The placket closure according to claim 1, wherein said bead head has a rectangular shaped cross-section.
7. The placket closure according to claim 6, wherein each said bead lip has a rectangular shaped cross-section.
8. A garment comprising:
at least one panel of material having a placket, the placket having a first side and a second side;
a first member having at least one pair of spaced apart, parallel rails, each rail having a bead lip; and
a second member having at least one rail having a bead head, the bead head being positionable between the bead lips of said first member in order to form an interlocking engagement; and
means for attaching said first member and said second member to the first side and the second side of the placket, respectively;
whereby said first member and said second member provide the placket with a releasable closure for opening and closing the placket.
9. The garment according to claim 8, wherein said bead head has a diamond shaped cross-section.
10. The garment according to claim 9, wherein each said bead lip has a semi-diamond shaped cross-section.
11. The garment according to claim 8, wherein said bead head has a circular shaped cross-section.
12. The garment according to claim 11, wherein each said bead lip has a circular shaped cross-section.
13. The garment according to claim 8, wherein said bead head has a rectangular shaped cross-section.
14. The garment according to claim 13, wherein each said bead lip has a rectangular shaped cross-section.
15. The garment according to claim 8, wherein said panel of material having said placket forming a portion of clothing is selected from the group consisting of pull over collars, pants flies, sleeve cuffs, skirt flies, dress flies, and pockets.

1. A bicycle suspension assembly, comprising:
(a) at least first and second telescoping portions having a common longitudinal axis;
(b) a damper cartridge body partially defining a variable volume first chamber and coupled to the first telescoping portion;
(c) a piston coupled to a piston rod; the piston and at least a portion of the piston rod movable along the common longitudinal axis within the first telescoping portion;
(d) a second chamber;
(e) a third chamber; the third chamber at least partially surrounding the first and second chambers and whereby fluid flows from the first chamber ultimately to the third chamber as the piston rod moves further into the first telescoping portion;
(f) a moveable inertia mass;
(g) a shaft, having an interior hollow portion and an outer surface; the interior hollow portion being in fluidic communication with at least one-flow passage intermediate the ends of the shaft that is selectively at least partially obstructed by the inertia mass to selectively control the degree of fluid flow restriction from the first chamber to the second chamber depending upon the position of the inertia mass;
(h) the inertia mass movable along the outer surface of the shaft between:
(1) a first position at least partially restricting fluid flow through the at least one flow passage, wherein a portion of the fluid bypasses flowing through the at least one flow passage to flow from the first chamber ultimately to the third chamber as the piston rod moves further into the first telescoping portion; and
(2) a second position providing less restriction to fluid flow through the at least one flow passage, wherein less fluid bypasses flowing through the at least one flow passage to flow from the first chamber ultimately to the third chamber as the piston rod moves further into the first telescoping portion; and

(i) further comprising:
(1) a first compression valve;
(2) a blowoff valve; and
(3) wherein:
(a) when the inertia mass is in its first position fluid must flow through the compression and blowoff valves to travel from the first chamber to the third chamber; and
(b) when the inertia mass is in its second position fluid flows through only one of the compression and blowoff valves to travel from the first chamber to the third chamber.
2. A bicycle suspension assembly, comprising:
(a) at least first and second telescoping portions having a common longitudinal axis;
(b) a variable volume first chamber partially defined by the first telescoping portion;
(c) a variable volume second chamber partially defined by the first telescoping portion;
(d) a piston dividing the first telescoping portion into the first and second chambers and coupled to a piston rod; the piston and at least a portion of the piston rod movable along the common longitudinal axis within the first telescoping portion;
(e) a variable volume third chamber at least partially defined by the second telescoping portion and containing a fluid; the second telescoping portion at least partially surrounding the first telescoping portion;
(f) a variable volume fourth chamber in fluid communication with the first chamber;
(g) a moveable inertia mass;
(h) a shaft, having an interior hollow portion and an outer surface, the interior hollow portion being in fluidic communication with at least one flow passage intermediate the ends of the shaft that is selectively at least partially obstructed by the inertia mass to control the degree of fluid flow restriction from the first chamber to the fourth chamber depending upon the position of the inertia mass;
(i) the inertia mass moveable along the outer surface of the shaft between:
(1) a first position at least partially restricting fluid flow through the at least one flow passage, wherein a portion of fluid bypasses flowing through the at least one flow passage to flow from the first chamber to the fourth chamber as the piston rod moves further into the first telescoping portion; and
(2) a second position providing less restriction to fluid flow through the at least one flow passage, wherein less fluid bypasses flowing through the at least one flow passage to flow from the first chamber to the fourth chamber as the piston rod moves further into the first telescoping portion: and

(j) wherein the inertia mass moves from the first position towards the second position when an upward acceleration imparted to at least a portion of the bicycle suspension assembly exceeds a predetermined acceleration threshold.
3. The bicycle suspension assembly of claim 2, wherein the fluid contained in the variable volume third chamber is a pressurized gas.
4. The bicycle suspension assembly of claim 2 further comprising a pressure-relief valve associated with a pressure-relief chamber.
5. The bicycle suspension assembly of claim 4, wherein the pressure relief valve is disposed between the first chamber and the fourth chamber.
6. The bicycle suspension assembly of claim 2, wherein the bicycle suspension assembly comprises a shock absorber.
7. The bicycle suspension assembly of claim 2, wherein the shaft has a longitudinal axis and the predetermined acceleration threshold may be adjusted by changing the orientation of the longitudinal axis of the shaft.
8. The bicycle suspension assembly of claim 2, wherein the first inertia mass position substantially inhibits fluid flow through the at least one flow passage.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for forcing a search processor to skip over rules within a group of rules, the method comprising:
in a compiler provided with a set of rules for matching a key, the set of rules divided into groups, each group being prioritized with respect to each other and each rule within each group being prioritized with respect to each other, and the set of rules including at least one skip group rule;
rewriting rules belonging to a same group as the skip group rule and having priorities lower than the skip group rule, the lower priority rules being rewritten based on the skip group rule such that in response to matching a key to the skip group rule, a search processor skips over the skip group rule and the lower priority rules;
providing the rewritten rules to the search processor;
wherein rewriting the lower priority rules includes subtracting the skip group rule from each of the lower priority rules, each lower priority rule being rewritten with a respective subtracted rule as one or more rewritten rules;
wherein subtracting includes, given the skip group rule including a field having a first bitmask and each of the lower priority rules including a corresponding field having a second bitmask, for each second bitmask, inverting the first bitmask and intersecting the inverted first bitmask with a subject second bitmask to form an third bitmask, and including the third bitmask in a rewritten rule;
wherein intersecting the inverted first bitmask with the subject second bitmask includes, bit-by-bit:
intersecting a don’t-care bit of the inverted first bitmask with a don’t-care bit of the subject second bitmask yields a don’t-care bit in the third bitmask;
intersecting a don’t-care bit with a value bit yields the value bit in the third bitmask:
intersecting a value bit with an equal value bit yields the value bit in the third bitmask; and
intersecting a value bit with an unequal value bit yields the third bitmask having a null value.
2. The method of claim 1 wherein each rule includes at least one field and wherein subtracting includes subtracting, on a field-by-field basis, the skip group rule from each of the lower priority rules.
3. The method of claim 1 wherein a group of rules includes a first skip group rule and a second skip group rule; and
wherein subtracting includes subtracting the first skip group rule from each of the lower priority rules and subtracting the second skip group rule from each of the lower priority rules having priorities lower than the second skip group rule.
4. The method of claim 1, wherein subtracting further includes, given the skip group rule including a field having a first range and each of the lower priority rules including a corresponding field having a second range, for each lower priority rule, subtracting the first range from a respective second range and including the subtracted range in a rewritten rule.
5. The method of claim 4, wherein the subtracted range includes a first sub-range and a second sub-range, the first sub-range and second sub-range being included in a first rewritten rule and a second rewritten rule.
6. The method of claim 4, wherein the first range and second range each includes one value.
7. The method of claim 1 wherein inverting the first bitmask includes for each value bit in the first bitmask, creating a mask value by:
inverting a subject value bit; and
setting remain bits to don’t-care bits; and
or’ing the mask values and yielding the inverted first bitmask value.
8. The method of claim 1 wherein the first bitmask and the second bitmask are prefixes in which don’t-care bits are the least significant bits.
9. The method of claim 1 wherein rewriting includes determining whether the skip group rule and a lower priority rule overlap; and rewriting the lower priority rule as it is.
10. The method of claim 9 wherein, in an event, the determination is the skip group rule and lower priority rule do not overlap, writing the lower priority rule without change.
11. The method of claim 1 further comprising coalescing two or more rewritten rules into a coalesced rule.
12. A system for forcing a search processor to skip over rules within a group of rules, the system comprising:
a memory having computer executable instructions thereupon;
at least one interface for receiving a set of rules for matching a key, the set of rules divided into groups, each group being prioritized with respect to each other and each rule within each group being prioritized with respect to each other, and the set of rules including at least one skip group rule, the set of rules including at least one skip group rule;
a compiler, comprising one or more processors, coupled to the memory and the at least one interface, the computer executable instructions when executed by the compiler cause the compiler to:
rewrite rules belonging to a same group as the skip group rule and having priorities lower than the skip group rule, the lower priority rules being rewritten based on the skip group rule such that in response to matching a key to the skip group rule, a search processor skips over the skip group rule and the lower priority rules;
provide the rewritten rules to the search processor;
wherein the compiler rewrites the lower priority rules by subtracting the skip group rule from each of the lower priority rules, each lower priority rule being rewritten with a respective subtracted rule as one or more rewritten rules;
wherein given the skip group rule including a field having a first bitmask and each of the lower priority rules including a corresponding field having a second bitmask, for each second bitmask, the compiler subtracts by inverting the first bitmask and intersecting the inverted first bitmask with a subject second bitmask to form an third bitmask, and including the third bitmask in a rewritten rule;
wherein the compiler intersects the inverted first bitmask with the subject second bitmask includes, bit-by-bit, by:
intersecting a don’t-care bit of the inverted first bitmask with a don’t-care bit of the subject second bitmask yields a don’t-care bit in the third bitmask;
intersecting a don’t-care bit with a value bit yields the value bit in the third bitmask;
intersecting a value bit with an equal value bit yields the value bit in the third bitmask; and
intersecting a value bit with an unequal value bit yields the third bitmask having a null value.
13. A tangible non-transitory computer-readable storage medium having computer readable instructions stored therein for forcing a search processor to skip over rules within a group of rules, which when executed by a compiler provided with a set of rules for matching a key, the set of rules divided into groups, each group being prioritized with respect to each other and each rule within each group being prioritized with respect to each other, the set of rules including at least one skip group rule, cause the compiler to:
rewrite rules belonging to a same group as the skip group rule and having priorities lower than the skip group rule, the lower priority rules being rewritten based on the skip group rule such that in response to matching a key to the skip group rule, a search processor skips over the skip group rule and the lower priority rules;
provide the rewritten rules to the search processor;
wherein the compiler rewrites the lower priority rules by subtracting the skip group rule from each of the lower priority rules, each lower priority rule being rewritten with a respective subtracted rule as one or more rewritten rules;
wherein given the skip group rule including a field having a first bitmask and each of the lower priority rules including a corresponding field having a second bitmask, for each second bitmask, the compiler subtracts by inverting the first bitmask and intersecting the inverted first bitmask with a subject second bitmask to form an third bitmask, and including the third bitmask in a rewritten rule;
wherein the compiler intersects the inverted first bitmask with the subject second bitmask includes, bit-by-bit, by:
intersecting a don’t-care bit of the inverted first bitmask with a don’t-care bit of the subject second bitmask yields a don’t-care bit in the third bitmask;
intersecting a don’t-care bit with a value bit yields the value bit in the third bitmask;
intersecting a value bit with an equal value bit yields the value bit in the third bitmask; and
intersecting a value bit with an unequal value bit yields the third bitmask having a null value.