1461121889-3b29ec7e-66d6-4fd4-a094-19f5e62a1bd3

1. A method for automatic detection of defects in TSV vias formed in a layer of semiconductor material, this detection taking place before stacking this layer with a plurality of other layers of semiconductor material for the design of a multilayer chip integrated circuit, including:
measurement on each of said TSV vias of at least one parameter derived from an electrical characteristic of the TSV vias,
detection of defects in said TSV vias according to a comparison of the parameters measured with at least one reference parameter,
calculating said at least one reference parameter using the measured parameters,

wherein said at least one parameter measured on each of the TSV vias includes an oscillation frequency value derived from a capacitive characteristic of the TSV vias.
2. The method for automatic detection of defects in TSV vias as claimed in claim 1, wherein the calculation of said at least one reference parameter comprises:
the determination, based on the parameters measured, of an expected value of the parameter to be measured on each of said TSV vias, this expected value being considered to be characteristic of a TSV via without defects, and
the calculation of said at least one reference parameter by applying a predefined and programmable permitted deviation parameter relative to this expected value.
3. The method for automatic detection of defects in TSV vias as claimed in claim 2, wherein the measurement on each of said TSV vias of an oscillation frequency derived from a capacitive characteristic of the TSV vias includes the following steps:
connection of a set of ring oscillators to all the TSV vias formed in the layer of semiconductor material, each ring oscillator being connected to at least one TSV via,
sequential selection of each of said ring oscillators,
sequential measurement of an oscillation frequency of each ring oscillator selected.
4. The method for automatic detection of defects in TSV vias as claimed in claim 2, wherein:
the expected value, annotated FMIN, is the lowest of the oscillation frequencies measured,
the permitted deviation parameter, annotated TTT, is expressed as a percentage of the expected value, and
said at least one reference parameter, annotated FREF, is a threshold frequency calculated as follows:
FREF=FMIN\xb7(1+TTT),
defects being detected in said TSV vias once a measured oscillation frequency exceeds this threshold frequency.
5. The method for automatic detection of defects in TSV vias as claimed in claim 2, wherein:
the expected value, annotated FMOY, is the mean of the oscillation frequencies measured,
the permitted deviation parameter, annotated TTT, is expressed as a percentage of the expected value, and
said at least one reference parameter, annotated FREF\u2212INF, FREF\u2212SUP, consists of the lower and upper limits of a frequency interval calculated as follows:
FREF\u2212INF=FMOY\xb7(1\u2212TTT) and FREF\u2212SUP=FMOY\xb7(1+TTT),
defects being detected in said TSV vias once a measured oscillation frequency is outside this interval.
6. A device for automatic detection of defects in TSV vias formed in a layer of semiconductor material, for a detection taking place before stacking this layer with a plurality of other layers of semiconductor material for the design of a multilayer chip integrated circuit, comprising:
means for measuring on each of said TSV vias at least one parameter derived from an electrical characteristic of the TSV vias,
means for detecting defects in said TSV vias according to a comparison of the parameters measured with at least one reference parameter,
means for calculating said at least one reference parameter based on the parameters measured,

wherein said at least one parameter measured on each of the TSV vias comprises an oscillation frequency value derived from a capacitive characteristic of the TSV vias.
7. The device for automatic detection of defects in TSV vias as claimed in claim 6, wherein the measuring means include a set of ring oscillators connected to all the TSV vias formed in the layer of semiconductor material, each ring oscillator being connected to at least one TSV via.
8. The device for automatic detection of defects in TSV vias as claimed in claim 7, wherein the calculating means include:
a counter of a number of rising edges of an oscillation signal of a ring oscillator selected sequentially for a predefined and programmable counting time, for the sequential supply of an oscillation frequency value,
a computer of at least one expected value of the oscillation frequency to be measured on each of said ring oscillators, this expected value being considered to be characteristic of a ring oscillator connected to at least one TSV via without defects, and of at least one reference frequency by applying a predefined and programmable permitted deviation parameter relative to this expected value.
9. A system for automatic detection of defects in TSV vias, comprising:
a detection device as claimed claim 6, and

a module for controlling access, from an external tester, to the detection device according to the IEEE 1149.1 standard or JTAG standard.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

I claim:

1. A placket closure comprising:
a first member having at least one pair of spaced apart, parallel rails, each rail having a bead lip; and
a second member having at least one rail having a bead head, the bead head being positionable between the bead lips of said first member in order to form an interlocking engagement; and
means for attaching said first member and said second member to respective sides of a garment placket;
whereby said first member and said second member provide the placket with a releasable closure for opening and closing the placket.
2. The placket closure according to claim 1, wherein said bead head has a diamond shaped cross-section.
3. The placket closure according to claim 2, wherein each of the bead lips has a semi-diamond shaped cross-section, said pair of rails defining a diamond-shaped channel.
4. The placket closure according to claim 1, wherein said bead head has a circular shaped cross-section.
5. The placket closure according to claim 4, wherein each said bead lip has a circular shaped cross-section.
6. The placket closure according to claim 1, wherein said bead head has a rectangular shaped cross-section.
7. The placket closure according to claim 6, wherein each said bead lip has a rectangular shaped cross-section.
8. A garment comprising:
at least one panel of material having a placket, the placket having a first side and a second side;
a first member having at least one pair of spaced apart, parallel rails, each rail having a bead lip; and
a second member having at least one rail having a bead head, the bead head being positionable between the bead lips of said first member in order to form an interlocking engagement; and
means for attaching said first member and said second member to the first side and the second side of the placket, respectively;
whereby said first member and said second member provide the placket with a releasable closure for opening and closing the placket.
9. The garment according to claim 8, wherein said bead head has a diamond shaped cross-section.
10. The garment according to claim 9, wherein each said bead lip has a semi-diamond shaped cross-section.
11. The garment according to claim 8, wherein said bead head has a circular shaped cross-section.
12. The garment according to claim 11, wherein each said bead lip has a circular shaped cross-section.
13. The garment according to claim 8, wherein said bead head has a rectangular shaped cross-section.
14. The garment according to claim 13, wherein each said bead lip has a rectangular shaped cross-section.
15. The garment according to claim 8, wherein said panel of material having said placket forming a portion of clothing is selected from the group consisting of pull over collars, pants flies, sleeve cuffs, skirt flies, dress flies, and pockets.