Author: claimsbot

1. A system for automated transfer of articles from a cart to a transfer surface, the system comprising:
a cart having a shelf for carrying articles and a fin over the shelf;
a cart drive mechanism located over the cart which contacts the fin to drive the cart along a driven cart path and past a stationary diverter arm;
the diverter arm extending laterally into the driven cart path and over the shelf of the cart to contact an object on the shelf and laterally divert the object off of the shelf on to a transfer surface.
2. The system of claim 1 wherein the cart further comprises a flange which extends over a portion of the shelf, and a distal end of the diverter arm fits between the flange and the shelf as the cart passes the diverter arm.
3. A system for transfer of articles from a cart, the system comprising:
a cart having a shelf for carrying articles and a fin located over the shelf;
a cart drive mechanism located over the cart which contacts the fin to drive the cart along a cart path and past a stationary diverter arm;
the diverter arm extending laterally into the cart path and over the shelf of the cart to contact an object on the shelf and laterally divert the object off of the shelf.
4. The system of claim 3 wherein the cart further comprises a flange which extends over a portion of the shelf, and a distal end of the diverter arm fits between the flange and the shelf as the cart passes the diverter arm.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method comprising:
pulsing a dopant perpendicular to an upper surface of a substrate, forming an implantation beam pulse;
applying an electric field and a magnetic field simultaneously, at a target fin of a fin-type field effect transistor (FINFET), to the implantation beam pulse to effectuate a curvilinear trajectory path of the implantation beam pulse;
varying the curvilinear trajectory path of the implantation beam pulse by varying a direction of the electric field and the magnetic field; and
implanting the dopant onto a sidewall surface of the target FINFET fin on the upper surface of the substrate via the curvilinear trajectory path of the implantation beam pulse.
2. The method of claim 1, further comprising:
masking top and sidewall surfaces of one or more other FINFET fins adjacent to the target FINFET fin to prevent implantation of the one or more other FINFET fins with the dopant.
3. (canceled)
4. The method of claim 1, further comprising:
varying the curvilinear trajectory path of the implantation beam pulse by varying a strength of the electric field and the magnetic field.
5. The method of claim 1, wherein the electric field and the magnetic field are pulsed in synchronization with the implantation beam pulse.
6. The method of claim 1, wherein concentration levels of the dopant at a top surface and at a plurality of sidewall surfaces of the target FINFET fin are substantially the same.
7. The method of claim 6, wherein depths of the concentration levels of the dopant at the top surface and at the plurality of sidewall surfaces of the target FINFET fin are substantially the same.
8. The method of claim 1, wherein the curvilinear trajectory path is at an angle greater than 0 degree and less than 90 degrees with a reference to the sidewall surface of the target FINFET fin.
9. The method of claim 8, further comprising:
applying a plurality of electric fields in different directions to the implantation beam pulse to effectuate the angle in the curvilinear trajectory path.
10. A device comprising:
a substrate having an upper surface;
a fin-type field effect transistor (FINFET) fin formed on the upper surface; and
a top surface and a plurality of side surfaces of the FINFET fin implanted with a dopant, wherein concentration levels of the dopant at the top surface and at the plurality of side surfaces of the FINFET fin are substantially same, and
wherein the dopant is implanted via an implantation beam pulse varied by at least one electric field and at least one magnetic field simultaneously applied at the FINFET fin.
11. (canceled)
12. The device of claim 10, wherein depths of the concentration levels of the dopant at the top surface and at the plurality of side surfaces of the FINFET fin are substantially same.
13. A method comprising:
forming a plurality of fin-type field effect transistor (FINFET) fins on an upper surface of a substrate, wherein each pair of adjacent FINFET fins is separated by a trench along the upper surface of the substrate;
masking top and sidewall surfaces of one or more of the plurality of FINFET fins adjacent to a target FINFET fin in the plurality of FINFET fins;
pulsing a dopant perpendicular to the upper surface of the substrate, forming an implantation beam pulse;
applying an electric field and a magnetic field simultaneously, at the target fin of the FINFET, to the implantation beam pulse to effectuate a curvilinear trajectory path of the implantation beam pulse;
varying the curvilinear trajectory path of the implantation beam pulse by varying a direction of the electric field and the magnetic field; and
implanting the dopant onto a sidewall surface of the target FINFET fin via the curvilinear trajectory path of the implantation beam pulse.
14. (canceled)
15. The method of claim 13, further comprising:
varying the curvilinear trajectory path of the implantation beam pulse by varying a strength of the electric field and the magnetic field.
16. The method of claim 13, wherein the electric field and the magnetic field are pulsed in synchronization with the implantation beam pulse.
17. The method of claim 13, wherein concentration levels of the dopant at a top surface and at a plurality of sidewall surfaces of the target FINFET fin are substantially the same.
18. The method of claim 17, wherein depths of the concentration levels of the dopant at the top surface and at the plurality of sidewall surfaces of the target FINFET fin are substantially the same.
19. The method of claim 13, wherein the curvilinear trajectory path is at an angle greater than 0 degree and less than 90 degrees with a reference to the sidewall surface of the target FINFET fin.
20. The method of claim 19, further comprising:
applying a plurality of electric fields in different directions to the implantation beam pulse to effectuate the angle in the curvilinear trajectory path.

1. An overwritable recording medium, the recording medium comprising:
content information recording regions which represent desired content information; and
sync code recording regions which represent sync codes synchronized with each other during the reading of the content information,
wherein the sync code recording regions are formed by the sync codes having at least detectors defined by at least two kinds of patterns for being detected as the sync codes.
2. The recording medium according to claim 1,
wherein the sync code recording regions are formed by the sync codes having at least the detectors defined by recording patterns having different lengths according to the patterns.
3. The recording medium according to claim 1,
wherein, when the detectors are composed of a plurality of components, the sync code recording regions are formed by the sync codes having at least the detectors defined by recording patterns having different combinations of the components according to the patterns.
4. The recording medium according to claim 1,
wherein the sync code recording regions are formed by the sync codes having at least the detectors defined by the recording patterns longer than the recording patterns having the maximum lengths in the content information recording regions in the circumferential direction of the recording medium.
5. A recording medium according to claim 1,
wherein the sync code recording regions are formed by the sync codes having the detectors and specifying information for specifying data array positions of the sync codes in the content information.
6. A recording medium according to claim 1,
wherein the sync code recording regions are separated from the respective content information recording regions by a predetermined distance.
7. A recording device for recording, in an overwritable recording medium, content information recording regions that represent desired content information and sync code recording regions for forming the sync codes having at least detectors defined by at least two kinds of patterns for being detected as the sync codes, the recording device comprising:
a sync code selecting device which selects any one of the identifiers of the sync codes in the sync code recording regions; and
a recording forming device which forms the content information recording patterns and sync code recording patterns including detectors forming the selected sync codes, in the recording medium.
8. The recording device according to claim 7,
wherein, when the sync code recording regions that are formed by the sync codes having at least the detectors defined by recording patterns having different lengths according to the patterns are recorded in the recording medium, the recording forming device generates the sync code recording patterns having the detectors defined by recording patterns having different lengths according to the patterns based on the identifiers of the sync codes selected by the sync code selecting device and forms the generated sync code recording patterns in the recording medium.
9. The recording device according to claim 7,
wherein, when the detectors are composed of a plurality of components, the recording forming device generates sync code recording patterns having at least the detectors defined by recording patterns having different combinations of the components according to the patterns and forms the generated sync code recording patterns in the recording medium.
10. The recording device according to claim 7,
wherein the recording forming device forms the sync code recording patterns in the recording medium so as to be separated from the respective content recording regions by a predetermined distance.
11. A reproducing device for reproducing a recording medium in which content information recording regions that represent desired content information and sync code recording regions that are formed by the sync codes having at least detectors defined by at least two kinds of patterns for being detected as the sync codes are recorded, the reproducing device comprising:
a reading device which reads the content information recording regions and the sync code recording regions from the recording medium;
a sync code detecting device which detects the sync codes based on the information on the detectors included in the information on the read sync code recording regions; and
a reproducing device which reproduces the content information based on the detected sync codes.
12. The reproducing device according to claim 11,
wherein, when the recording medium in which the sync code recording regions that are formed by the sync codes having at least detectors defined by recording patterns having different lengths according to the patterns are formed is reproduced, the sync code detecting device detects the detectors defined by recording patterns having different lengths according to the patterns to thus detect the sync codes.
13. The reproducing device according to claim 10,
wherein, when the recording medium in which the sync code recording regions that are formed by the sync codes having at least the detectors defined by recording patterns having different combinations of components according to the patterns are formed is reproduced, the sync code detecting device detects the detectors defined by recording patterns having different combinations of components according to the patterns to thus detect the sync code recording regions.
14. A method of recording, in an overwritable recording medium, content information recording regions that represent desired content information and sync code recording regions that are formed by sync codes having at least detectors defined by at least two kinds of patterns for being detected as the sync codes, the method comprising:
a sync code selecting process of selecting any one of the identifiers of the sync codes in the sync code recording regions; and
a recording forming process of forming the content information recording patterns and sync code recording patterns including detectors forming the selected sync codes, in the recording medium.
15. The recording method according to claim 14,
wherein, when the sync code recording regions that are formed by the sync codes having at least the detectors defined by recording patterns having different lengths according to the patterns are recorded in the recording medium, in the recording forming process, the sync code recording patterns having the detectors defined by recording patterns having different lengths according to the patterns based on the identifiers of the sync codes selected by the sync code selecting device and forms the generated sync code recording patterns in the recording medium.
16. The recording method according to claim 14,
wherein, when the detectors are composed of a plurality of components, in the recording forming process, the sync code recording patterns having at least the detectors defined by recording patterns having different combinations of the components according to the patterns are generated and the generated sync code recording patterns are formed in the recording medium.
17. A method of reproducing a recording medium in which content information recording regions that represent desired content information and sync code recording regions that are formed by the sync codes having at least detectors defined by at least two kinds of patterns for being detected as the sync codes are recorded, the method comprising:
a reading process of reading the content information recording regions and the sync code recording regions from the recording medium;
a sync code detecting process of detecting the sync codes based on the information on the detectors included in the information on the read sync code recording regions; and
a reproducing process of reproducing the content information based on the detected sync codes.
18. The reproducing method according to claim 17,
wherein, when the recording medium in which the sync code recording regions that are formed by the sync codes having at least detectors defined by recording patterns having different lengths are formed is reproduced, in the sync code detecting process, the detectors defined by recording patterns having different lengths are detected to thus detect the sync codes.
19. The reproducing method according to claim 17,
wherein, when the recording medium in which the sync code recording regions that are formed by the sync codes having at least the detectors defined by recording patterns having different combinations of components are formed is reproduced, in the sync code detecting process, the detectors defined by recording patterns having different combinations of components according to the patterns are detected to thus detect the sync code recording regions.
20. A recording program for a computer to record, in an overwritable recording medium, content information recording regions that represent desired content information and sync code recording regions that are formed by the sync codes having at least detectors defined by at least two kinds of patterns for being detected as the sync codes, the recording program making the computer functional as:
a sync code selecting device which selects any one of the identifiers of the sync codes in the sync code recording regions; and
a recording forming control device which forms the content information recording patterns and sync code recording patterns including detectors forming the selected sync codes in the recording medium.
21. The recording program according to claim 20,
wherein, when the sync code recording regions that are formed by the sync codes having at least the detectors defined by recording patterns having different lengths according to the patterns are recorded in the recording medium, the recording program makes the computer functional as:
the recording forming control device which generates sync code recording patterns having the detectors defined by recording patterns having different lengths according to the patterns based on the identifiers of the sync codes selected by the sync code selecting device and forms the generated sync code recording patterns in the recording medium.
22. A reproducing program for reproducing a recording medium in which content information recording regions that represent desired content information and sync code recording regions that are formed by sync codes having at least detectors defined by at least two kinds of patterns for being detected as the sync codes are recorded is reproduced by a computer, the reproducing program making the computer functional as:
a reading control device which reads the content information recording regions and the sync code recording regions from the recording medium;
a sync code detecting device which detects the sync codes based on the information on the detectors included in the information on the read sync code recording regions; and
a reproducing control device for reproducing the content information based on the detected sync codes.
23. The reproducing program according to claim 22,
wherein, when the recording medium in which the sync code recording regions that are formed by sync codes having at least detectors defined by recording patterns having different lengths according to the patterns are formed is reproduced, the reproducing program makes the computer functional as the sync code detecting device which detects the detectors defined by recording patterns having different lengths according to the patterns to thus detect the sync codes.
24. The reproducing program according to claim 22,
wherein, when the recording medium in which the sync code recording regions that are formed by the sync codes having at least the detectors defined by recording patterns having different combinations of components according to the patterns are formed is reproduced, the reproducing program makes the computer functional as the sync code detecting device for detecting the detectors defined by recording patterns having different combinations of components according to the patterns to thus detect the sync code recording regions.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor integrated circuit device comprising:
a first voltage generating circuit generating a first voltage;
a first reference voltage generating circuit to form a first reference voltage by use of an amplifying circuit by receiving the first voltage provided by said first voltage generating circuit and adjusting the voltage gain with a resistance circuit and a switch controlled by a first trimming switch setting signal;
a first output buffer which is activated by a first control signal to form an internal voltage corresponding to said first reference voltage;
a second reference voltage generating circuit to form a second reference voltage by adjusting the combination of threshold voltages of MOSFETs, using a plurality of MOSFETs and a switch controlled by a second trimming switch setting signal;
a second output buffer activated with a second control signal to form an internal voltage corresponding to said second reference voltage; and
an internal circuit to receive the internal voltage supplied from said first output buffer or said second output buffer activated by said first control signal and said second control signal, respectively;
wherein said internal circuit is set to the active condition by said first control signal when the internal voltage is supplied from said first output buffer and to the standby condition by said second control signal when the internal voltage is supplied from said second output buffer.
2. The semiconductor integrated circuit device according to claim 1,
wherein said second reference voltage generating circuit includes: a plurality of serial circuits, each of which is comprised of a plurality of diode type MOSFETs and switches; and a current source circuit provided in common for said plurality of serial circuits, and
wherein said second reference voltage is adjusted by controlling said switches with said second trimming setting signal.
3. The semiconductor integrated circuit device according to claim 1,
wherein said second reference voltage generating circuit includes: a second voltage circuit to generate a second voltage which is a forward voltage of a PN junction diode; a cascade-connected circuit including a plurality of cascade-connected voltage follower circuits which have an offset voltage with a differential MOSFET which causes currents of different current densities to flow at respective cascade-connecting points; and a selector to select a voltage at one of the cascade-connecting points, and
wherein said second voltage is used as an input voltage of an initial stage circuit of said cascade-connected circuit, and said selector is controlled by said second trimming switch setting signal to output a voltage at any one of said cascade-connecting points as said second reference voltage.
4. The semiconductor integrated circuit device according to claim 1, further comprising a third output buffer having a current supply capability that is lower than that of said first output buffer,
wherein said third output buffer is set to an operating condition in place of said first output buffer during a DC current testing condition of the semiconductor integrated circuit device.
5. The semiconductor integrated circuit device according to claim 4,
wherein said first output buffer is activated by said first control signal,
wherein said third output buffer is activated by a third control signal, and
wherein said first voltage generating circuit and said first reference voltage generating circuit are activated by a logical sum (OR) signal of said first control signal and said second control signal.
6. The semiconductor integrated circuit device according to claim 1, further comprising a voltage detecting circuit for detecting that an output voltage of said first control signal has reached a predetermined voltage to assure stable operation of said internal circuit,
wherein, when the operations of said first first voltage generating circuit, first reference voltage generating circuit and first output buffer are shifted to the active condition from the non-active condition by said first control signal, supply of a clock signal to said internal circuit is started by a detection signal of said voltage detection circuit, and the operation of said second output buffer is shifted to the non-active condition by said second control signal.
7. The semiconductor integrated circuit device according to claim 6, wherein said voltage detecting circuit includes a voltage comparing circuit to compare said first voltage with said first reference voltage and a delay circuit to receive a voltage comparison output signal of said voltage comparing circuit, and said detection signal is formed by delaying, with said delay circuit, the voltage comparison output signal indicating that said first reference voltage becomes higher than said first voltage.
8. The semiconductor integrated circuit device according to claim 1, further comprising a third output buffer which receives said second reference voltage and is activated by a fourth control signal,
wherein said fourth control signal activates said third output buffer under the condition that an internal voltage corresponding to said first reference voltage is outputted by said first control signal to change said internal circuit to the operating condition, and said internal circuit forms said second trimming switch setting signal to set the output voltage of said third output buffer to a predetermined voltage and then store this signal to a non-volatile storage circuit included in the internal circuit.
9. The semiconductor integrated circuit device according to claim 8, wherein said internal circuit forms said first trimming switch setting signal so as to set the output voltage of said first output buffer to the predetermined voltage and then stores this signal to said non-volatile storage circuit.
10. The semiconductor integrated circuit according to claim 9,
wherein said internal circuit includes a microprocessor, a ROM storing at least a part of the operations of said microprocessor, and the non-volatile storage circuit, and
wherein said ROM includes a program to execute an operation to form the first trimming switch setting signal and the second trimming switch setting signal for setting said first reference voltage and he second reference voltage to the predetermined voltage and the operation to store such first and second trimming switch setting signals to said non-volatile storage circuit.
11. The semiconductor integrated circuit device according to claim 9,
wherein said internal circuit includes a microprocessor, a ROM storing at least a part of the operations of said microprocessor, and the non-volatile storage circuit, and
wherein said ROM includes a function for reading a program for setting said first reference voltage and second reference voltage to the predetermined voltage.
12. A semiconductor integrated circuit device comprising:
a voltage generating circuit to form a first voltage;
a first reference voltage generating circuit including: an amplifying circuit having a first input terminal to receive said first voltage, a second input terminal, and an output terminal; a first resistance connected between said output terminal and said second input terminal; and a second resistance connected between said second input terminal and a second voltage, said first reference voltage generating circuit forming a first reference voltage;
a first output buffer to form an internal voltage corresponding to said first reference voltage;
a second reference voltage generating circuit including: a first MOSFET of diode connection and a current source circuit which are connected in serial between said second voltage and a third voltage; and a second MOSFET having a gate connected to a node between said first MOSFET and said current source circuit and outputting a second reference voltage from the sourcedrain path thereof;
a second output buffer to form an internal voltage corresponding to said second reference voltage; and
an internal circuit to receive the internal voltage supplied from said first output buffer and second output buffer,
wherein said internal voltage is supplied from said first output buffer when said internal circuit is in the active condition, and said internal voltage is supplied from said second output buffer when said internal circuit is in the standby condition.
13. A semiconductor integrated circuit device, comprising:
a voltage generating circuit to form a first voltage;
a first reference voltage generating circuit including: an amplifying circuit having a first input terminal to receive said first voltage, a second input terminal, and an output terminal; a first resistance connected between said output terminal and said second input terminal; and a second resistance connected between said second input terminal and a second voltage, said first reference voltage generating circuit forming a first reference voltage;
a second reference voltage generating circuit including: a first MOSFET of diode connection and a current source circuit which are connected in serial; and a second MOSFET having a gate connected to a node between said first MOSFET and said current source circuit and outputting said second reference voltage from the sourcedrain path thereof; and
an internal circuit to operate with an internal voltage,
wherein said internal voltage is formed based on said first reference voltage and said second reference voltage,
wherein said first reference voltage generating circuit is in the active condition when said internal circuit is in the active condition, and
wherein said first reference voltage generating circuit is in the non-active condition and said second reference voltage generating circuit is in the active condition when said internal circuit is in the standby condition.
14. A semiconductor integrated circuit device comprising:
a first reference voltage generating circuit receiving a first voltage and including an amplifying circuit having a resistance circuit and a switch controlled by a first trimming switch setting signal, to form a first reference voltage;
a second reference voltage generating circuit including a plurality of MOSFETs and a switch controlled by a second trimming switch setting signal, to form a second reference voltage; and
an internal circuit to operate by receiving an internal voltage;
wherein said internal voltage is formed based on said first reference voltage or said second reference voltage,
wherein said first reference voltage generating circuit is in the active condition when said internal circuit is in the active condition, and
wherein said first reference voltage generating circuit is in the non-active condition and said second reference voltage generating circuit is in the active condition when said internal circuit is in the standby condition.
15. A semiconductor integrated circuit device according to claim 1,
wherein said first voltage is a fixed voltage.
16. A semiconductor integrated circuit device according to claim 3,
wherein said second voltage is a constant voltage.