Author: claimsbot

1. A binary-to-Gray converting circuit, comprising:
a buffer unit configured to generate a data code of n bits, where n is a natural number equal to or greater than two, in response to a power supply voltage and a second binary bit signal through an nth binary bit signal except for a first binary bit signal, the first binary bit signal corresponding to a least significant bit of a binary code of n bits, the second through nth binary bit signals corresponding to other bits of the binary code; and
a conversion unit configured to generate a Gray code of n bits based on the binary code and the data code, and configured to generate a kth Gray bit signal, where k is a natural number equal to or greater than one and equal to or less than n, by latching a kth data bit signal in response to a kth binary bit signal, a logic level of the kth Gray bit signal being determined corresponding to a logic level of the kth data bit signal, the kth Gray bit signal corresponding to a kth bit of the Gray code, the kth data bit signal corresponding to a kth bit of the data code, and the kth binary bit signal corresponding to a kth bit of the binary code.
2. The binary-to-Gray converting circuit of claim 1, wherein the conversion unit includes a first flip-flop through an nth flip-flop, each of the first through nth flip-flops generates one of a first Gray bit signal through an nth Gray bit signal corresponding to a respective one of a first bit through an nth bit of the Gray code.
3. The binary-to-Gray converting circuit of claim 2, wherein each of the first through nth flip-flops includes:
a data input terminal configured to receive one of a first data bit signal through an nth data bit signal corresponding to a respective one of a first bit through an nth bit of the data code;
a clock input terminal configured to receive a respective one of the first through nth binary bit signals; and
a data output terminal configured to output a respective one of the first through nth Gray bit signals.
4. The binary-to-Gray converting circuit of claim 3, wherein the buffer unit includes a first inverter through an (n-1)th inverter, each of the first through (n-1)th inverters generates a respective one of the first through (n-1)th data bit signals.
5. The binary-to-Gray converting circuit of claim 4, wherein an mth inverter, where m is a natural number equal to or greater than one and equal to or less than (n-1), inverts an (m+1)th binary bit signal to generate an mth data bit signal.
6. The binary-to-Gray converting circuit of claim 5, wherein the buffer unit outputs the power supply voltage as the nth data bit signal.
7. The binary-to-Gray converting circuit of claim 6, wherein each of the first through nth flip-flops is a positive-edge triggered D flip-flop operating in response to a rising edge of the respective one of the first through nth binary bit signals.
8. The binary-to-Gray converting circuit of claim 2, wherein each of the first through nth flip-flops includes:
a data input terminal configured to receive one of a first data bit signal through an nth data bit signal corresponding to a respective one of a first bit through an nth bit of the data code;
a clock input terminal configured to receive an inversion signal of a respective one of the first through nth binary bit signals; and
an inverted-data output terminal configured to output a respective one of the first through nth Gray bit signals.
9. The binary-to-Gray converting circuit of claim 8, wherein the buffer unit includes a first inverter through an (n-1)th inverter, each of the first through (n-1)th inverters generates a respective one of the first through (n-1)th data bit signals,
wherein an mth inverter, where m is a natural number equal to or greater than one and equal to or less than (n-1), inverts an (m+1)th binary bit signal to generate an mth data bit, and the buffer unit outputs the power supply voltage as the nth data bit signal.
10. The binary-to-Gray converting circuit of claim 9, wherein each of the first through nth flip-flops is a negative-edge triggered D flip-flop operating in response to a falling edge of the respective one of the first through nth binary bit signals.
11. A Gray code counter, comprising:
a binary counter circuit configured to generate a binary code of n bits, where n is a natural number equal to or greater than two, based on a power supply voltage and a clock signal; and
a binary-to-Gray converting circuit configured to generate a Gray code of n bits based on the binary code and the power supply voltage,
wherein the binary-to-Gray converting circuit comprises:
a buffer unit configured to generate a data code of n bits in response to the power supply voltage and a second binary bit signal to an nth binary bit signal except for a first binary bit signal, the first binary bit signal corresponding to a least significant bit of the binary code, the second through nth binary bit signals corresponding to other bits of the binary code, the first through nth binary bit signals being sequentially toggled; and
a conversion unit configured to generate the Gray code based on the binary code and the data code, and configured to generate a kth Gray bit signal, where k is a natural number equal to or greater than one and equal to or less than n, by latching a kth data bit signal in response to a kth binary bit signal of the binary code, a logic level of the kth Gray bit signal being determined corresponding to a logic level of the kth data bit signal, the kth Gray bit signal corresponding to a kth bit of the Gray code, the kth data bit signal corresponding to a kth bit of the data code, and the kth binary bit signal corresponding to a kth bit of the binary code.
12. The Gray code counter of claim 11, wherein the binary counter circuit is a synchronous counter circuit or an asynchronous counter circuit.
13. The Gray code counter of claim 12, wherein the binary counter circuit includes a first flip-flop through an nth flip-flop that are cascade-connected, each of the first through nth flip-flops generate one of the first through nth binary bit signals in response to the clock signal.
14. The Gray code counter of claim 11, wherein the binary counter circuit performs an up-counting operation or a down-counting operation.
15. The Gray code counter of claim 14, wherein the conversion unit includes a first flip-flop through an nth flip-flop, each of the first through nth flip-flops generate one of a first Gray bit signal through an nth Gray bit signal corresponding to a respective one of a first bit through an nth bit of the Gray code, and
wherein each of the first through nth flip-flops is a positive-edge triggered D flip-flop operating in response to a rising edge of a respective one of the first through nth binary bit signals when the binary counter circuit performs the up-countering operation, and is a negative-edge triggered D flip-flop operating in response to a falling edge of a respective one of the first through nth binary bit signals when the binary counter circuit performs the down-countering operation.
16. A binary-to-Gray converting circuit, comprising:
a buffer unit configured output a clock signal and a data signal, both based on a bit included in a binary code to be translated to a Gray code by the binary-to-Gray converting circuit; and
a conversion unit, coupled to the buffer unit, configured to receive the clock signal at a clock input terminal of an upper stage of the conversion unit and configured to receive the data signal at a data input terminal of a lower stage of the conversion unit, relative to the upper stage.
17. The circuit of claim 16 wherein the buffer unit further comprises:
an input terminal configured to receive the bit included in the binary code to be translated to a Gray code;
an output terminal, coupled to the input terminal, configured to provide the bit to the clock input terminal of the upper stage of the conversion unit as the clock signal; and
an inverter circuit, coupled to the input terminal, configured to invert the bit to provide the data signal to the lower stage of the conversion unit.
18. The circuit of claim 16 wherein the buffer unit is configured to receive a plurality of parallel bits included in the binary code and is configured to provide a respective plurality of parallel bits included in a data code provided to the conversion unit; and
the conversion unit is configured to receive the respective plurality of parallel bits included in a data code at respective stages of the conversion unit .
19. The circuit of claim 18 wherein an uppermost stage of the conversion unit receives a static power supply voltage signal as an uppermost bit included in the data code.
20. The circuit of claim 18 wherein a lower order bit included in the binary code is provided as a lowest stage clock input to the conversion unit.
21.-23. (canceled)

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An object-oriented system for managing relational numerical data, comprising:
a relation interface that provides access to a relation and its attributes and tuples, wherein an attribute is a data item with a numeric value and a relation is a set of n-tuples of attribute values, wherein said relation interface maintains its tuples in a fixed order and is adapted to selecting subsets of attributes andor tuples wherein a new relation interface instance is created;
an iterator interface for iterating over the tuples of a relation, wherein said iterator is adapted to acquiring the tuple attribute data as said data is being accessed; and
a notification interface for notifying other classes whenever changes occur in a relation interface instance.
2. The system of claim 11, further comprising:
a tuple interface for providing access to tuple values for each attribute of a relation, wherein each tuple interface instance is associated with a particular relation interface instance, and
wherein said iterator interface extends said tuple interface and is further adapted for saving and restoring a current position in the tuples of said relation, for moving to a tuple position defined by an attribute value, determining whether an iterator’s current position corresponds to one of a relation’s tuples and whether a current tuple is the first tuple in a continuous segment of tuples within the relation.
3. The system of claim 1, further comprising:
an attribute interface that represents an attribute of a relation, said attribute interface adapted for providing access to said attribute’s identifier, numeric data type, meta-data, range of values assumed by said attribute in said relation, value status and actual value of said attribute, wherein each attribute interface instance is associated with a relation interface instance.
4. The method of claim 3, wherein said meta-data of an attribute includes a textual description of said attribute, the measurement used for the attribute’s values, and allowable range of values for the attribute.
5. The system of claim 1, wherein said relation interface is further adapted to selecting a subset of attributes to identify tuples in a relation.
6. The system of claim 1, further comprising an identifier interface that represents an identifier for attributes that can be used across multiple relations, wherein an attribute common to a plurality of relations is identified by a single name.
7. The system of claim 1, further comprising a condition interface for evaluating one or more attribute conditional expressions for selecting attributes for a tuple.
8. The system of claim 1, wherein said relation represents a plurality of time based sensor measurements, wherein each attribute is associated with measurements from one sensor, and each attribute value is associated with a time stamp.
9. The system of claim 8, further comprising a source layer that acquires attribute data from one or more data sources as a time series of measurements with associated timelines and sorts the measurements for each attribute; and
a processing layer that merges timelines for each of the measurement time series into a single merged timeline, makes the measurement data available to an application program, and that includes a cache for storing data acquired from the source layer.
10. The system of claim 9, wherein said cache, when an application requests measurement data in a specified time range with a start time and an end time, determines whether a data cluster stored in said cache covers said time range, and if so, returns said cluster to said application, wherein if a cluster does not cover the requested time range, determines the start time of a new time range from a cluster stored in said cache, wherein if said new start time is before the requested end time, said cache returns data in the range of said requested start time and said new start time, and wherein if said new start time is after the requested end time, said cache returns data in the range of said requested start time and said requested end time.
11. The system of claim 9, wherein said processing layer merges timelines by associating an index variable with each attribute that corresponds with its timestamp in the merged timeline, comparing timestamps of all attributes at a position indicated by said index variable to find a next timestamp, and adding the next timestamp to the merged timeline.
12. The system of claim 1, wherein said relation represents a bitmap color image using red, green, and blue color values, wherein each pixel of said bitmap image is associated with an attribute for each of its coordinates and each of its color values.
13. An object-oriented system for managing relational numerical data, comprising:
a relation interface that provides access to a relation and its attributes and tuples, wherein an attribute is a data item with a numeric value and a relation is a set of n-tuples of attribute values, wherein said relation interface maintains its tuples in a fixed order and is adapted to selecting subsets of attributes andor tuples wherein a new relation interface instance is created;
a tuple interface for providing access to tuple values for each attribute of a relation, wherein each tuple interface instance is associated with a particular relation interface instance, and
an attribute interface that represents an attribute of a relation, said attribute interface adapted for providing access to said attribute’s identifier, numeric data type, meta-data, range of values assumed by said attribute in said relation, value status and actual value of said attribute, wherein each attribute interface instance is associated with a relation interface instance.
14. The system of claim 13, further comprising an iterator interface for iterating over the tuples of a relation, wherein said iterator is adapted to acquiring the tuple attribute data as said data is being accessed, wherein said iterator interface extends said tuple interface and is further adapted for saving and restoring a current position in the tuples of said relation, for moving to a tuple position defined by an attribute value, determining whether an iterator’s current position corresponds to one of a relation’s tuples and whether a current tuple is the first tuple in a continuous segment of tuples within the relation; and
a notification interface for notifying other classes whenever changes occur in a relation interface instance.
15. A program storage device readable by a computer, tangibly embodying a program of instructions executable by the computer to implement an object-oriented system for managing relational numerical data, said system comprising:
a relation interface that provides access to a relation and its attributes and tuples, wherein an attribute is a data item with a numeric value and a relation is a set of n-tuples of attribute values, wherein said relation interface maintains its tuples in a fixed order and is adapted to selecting subsets of attributes andor tuples wherein a new relation interface instance is created;
an iterator interface for iterating over the tuples of a relation, wherein said iterator is adapted to acquiring the tuple attribute data as said data is being accessed; and
a notification interface for notifying other classes whenever changes occur in a relation interface instance.
16. The computer readable program storage device of claim 15, said system further comprising:
a tuple interface for providing access to tuple values for each attribute of a relation, wherein each tuple interface instance is associated with a particular relation interface instance, and
wherein said iterator interface extends said tuple interface and is further adapted for saving and restoring a current position in the tuples of said relation, for moving to a tuple position defined by an attribute value, determining whether an iterator’s current position corresponds to one of a relation’s tuples and whether a current tuple is the first tuple in a continuous segment of tuples within the relation.
17. The computer readable program storage device of claim 15, said system further comprising:
an attribute interface that represents an attribute of a relation, said attribute interface adapted for providing access to said attribute’s identifier, numeric data type, meta-data, range of values assumed by said attribute in said relation, value status and actual value of said attribute, wherein each attribute interface instance is associated with a relation interface instance.
18. The computer readable program storage device of claim 17, wherein said meta-data of an attribute includes a textual description of said attribute, the measurement used for the attribute’s values, and allowable range of values for the attribute.
19. The computer readable program storage device of claim 15, wherein said relation interface is further adapted to selecting a subset of attributes to identify tuples in a relation.
20. The computer readable program storage device of claim 1, said system further comprising an identifier interface that represents an identifier for attributes that can be used across multiple relations, wherein an attribute common to a plurality of relations is identified by a single name.
21. The computer readable program storage device of claim 15, said system further comprising a condition interface for evaluating one or more attribute conditional expressions for selecting attributes for a tuple.
22. The computer readable program storage device of claim 15, wherein said relation represents a plurality of time based sensor measurements, wherein each attribute is associated with measurements from one sensor, and each attribute value is associated with a time stamp.
23. The computer readable program storage device of claim 22, said system further comprising a source layer that acquires attribute data from one or more data sources as a time series of measurements with associated timelines and sorts the measurements for each attribute; and
a processing layer that merges timelines for each of the measurement time series into a single merged timeline, makes the measurement data available to an application program, and that includes a cache for storing data acquired from the source layer.
24. The computer readable program storage device of claim 23, wherein said cache, when an application requests measurement data in a specified time range with a start time and an end time, determines whether a data cluster stored in said cache covers said time range, and if so, returns said cluster to said application, wherein if a cluster does not cover the requested time range, determines the start time of a new time range from a cluster stored in said cache, wherein if said new start time is before the requested end time, said cache returns data in the range of said requested start time and said new start time, and wherein if said new start time is after the requested end time, said cache returns data in the range of said requested start time and said requested end time.
25. The computer readable program storage device of claim 23, wherein said processing layer merges timelines by associating an index variable with each attribute that corresponds with its timestamp in the merged timeline, comparing timestamps of all attributes at a position indicated by said index variable to find a next timestamp, and adding the next timestamp to the merged timeline.
26. The computer readable program storage device of claim 15, wherein said relation represents a bitmap color image using red, green, and blue color values, wherein each pixel of said bitmap image is associated with an attribute for each of its coordinates and each of its color values.

1. A method of treating a turbine blade, comprising:
providing the turbine blade having an endplate with a peripheral surface;
placing a covering strip on the peripheral surface using a plug connection to at least partially cover the peripheral surface;
providing the plug connection by a groove formed into the peripheral surfaces;
plugging a plug-in limb of the covering strip into the groove;
coating the turbine blade with a material comprising metal or metal alloy or ceramic;
removing coating material from regions of the peripheral surface which are not covered by the covering strip; and
removing the covering strip from the turbine blade.
2. The method as claimed in claim 1, wherein the covering strip covers a region of the peripheral surface which extends on a side of the plug connection remote from the airfoil.
3. The method as claimed in claim 1, wherein the peripheral surface and the covering strip are plugged together as a tongue-and-groove connection.
4. The method as claimed in claim 1, wherein the covering strip has an angle profiled section with a protective limb adjoining the plug-in limb.
5. The method as claimed in claim 4, wherein the plug-in limb and the protective limb are perpendicular to one another.
6. The method as claimed in claim 1, wherein the covering strip has a length that is greater than the depth of the airfoil.
7. The method as claimed in claim 1, wherein the peripheral surface has a step in a region of the plug connection.
8. The method as claimed in claim 7, wherein the step projects outward on the side of the plug connection remote from the airfoil.
9. The method as claimed in claim 7, wherein the step projects outward on the side of the plug connection facing the airfoil.
10. A turbine blade, comprising:
an airfoil having an endplate with a hot-gas side facing the airfoil and adjoining peripheral surfaces; and
a plug-connection recess arranged on at least one of the peripheral surfaces,
wherein the at least one peripheral surface has a step in a region of the plug-connection recess, and
wherein the step projects outward on a side of the plug-connection recess, the side being remote from the airfoil or facing the airfoil.
11. A turbine blade as claimed in claim 10, wherein a plug-connection projection is arranged on a further surface of the peripheral surfaces.
12. The turbine blade as claimed in claim 10, wherein the plug-connection recess is formed as a groove.
13. The turbine blade as claimed in claim 10, wherein a covering strip covers the region of a peripheral surface which extends on a side of a plug connection between the covering strip and the turbine blade remote from the blade.
14. The turbine blade as claimed in claim 13, the covering strip is formed as an angle profiled section having a protective limb which adjoins a plug-in limb at an right angle.
15. The turbine blade as claimed in claims 13, wherein a length of the covering strip is greater than the depth of the airfoil.
16. The turbine blade as claimed in claim 13, wherein the covering strip consists of metal.
17. The turbine blade as claimed in claim 13, wherein the airfoil is delimited at both ends by endplates, and a covering strip is fitted onto a peripheral surface of two endplates.
18. A turbine blade, comprising:
an airfoil having an endplate with a hot-gas side facing the airfoil and adjoining peripheral surfaces; and
a plug-connection projection arranged on at least one of the peripheral surface,
wherein the at least one peripheral surface has a step in a region of the plug-connection projection, and
wherein the step projects outward on a side of the plug-connection projection, the side being remote from the airfoil or facing the airfoil.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method, comprising cleaning a semiconductor substrate with a cleaning solution to form a cleaned substrate; immersing, for a period of time between several seconds and approximately five (5) minutes, the cleaned substrate in a solution containing hydrogen and fluorine ions of between approximately 1%-50% by weight; removing the substrate from the solution and blow-drying the substrate with nitrogen, thereby forming an interface layer containing hydrogen and fluorine on the semiconductor substrate, said interface layer being of sufficient thickness to passivate a surface of said semiconductor substrate in a vicinity of said interface layer; subsequently depositing a metal layer over the interface layer using a thermally evaporated source, thereby forming a junction having a metal layer disposed over the interface layer disposed over the semiconductor, said junction having a specific contact resistance of less than or equal to approximately 1000\u03a9-\u03bcm2.
2. The method of claim 1, wherein following removal of the substrate from the solution and prior to blow-drying the substrate with nitrogen, rinsing the substrate in deionized water for less than 30 sec.
3. A method, comprising heating a substrate containing a semiconductor surface in the presence of a nitrogenous material thereby to form a nitride interface layer of sufficient thickness to passivate said semiconductor surface; cooling the semiconductor surface; subsequently depositing a metal layer over the interface layer using a thermally evaporated source, thereby forming a junction having a metal layer disposed over the interface layer disposed over the semiconductor, said junction having a specific contact resistance of less than or equal to approximately 1000\u03a9-\u03bcm2.
4. The method of claim 3, wherein the nitrogenous material comprises a gas.
5. The method of claim 4, wherein the gas comprises ammonia.
6. The method of claim 3, wherein the substrate contains an exposed silicon surface and is annealed at a temperature between approximately 300\xb0 C. and approximately 750\xb0 C.
7. The method of claim 3, the heating is performed in a heating chamber and prior to the heating, pulling a vacuum of less than approximately one millionth of a Torr in the heating chamber, and then heating the substrate in the heating chamber.
8. The method of claim 3, wherein the substrate is heated to a temperature between approximately 900\xb0 C. and approximately 1000\xb0 C. in an inert ambient.
9. The method of claim 3, wherein the semiconductor surface is exposed to a pulse of ammonia for a time period between approximately 0.5 seconds and approximately 5 seconds.