1. A method of acquiring data surrounding an anomalous or identifiable event within a modulated input signal comprising the steps of:
demodulating the modulated input signal according to a specified modulation standard to obtain data representing information content;
analyzing the information content for an occurrence of the anomalous or identifiable event; and
generating a trigger signal upon the occurrence of the anomalous or identifiable event in order to acquire the data surrounding the anomalous or identifiable event from the modulated input signal.
2. The method as recited in claim 1 wherein the modulated input signal comprises a signal selected from the group consisting of a realtime modulated signal, a stored modulated signal, and a simulated modulated signal.
3. A method of acquiring data surrounding an anomalous or identifiable event within an input signal comprising the steps of:
inputting the input signal to each of a plurality of types of trigger generators, each trigger generator providing as an output a different type of trigger signal; and
combining the outputs from the trigger generators to produce an acquisition trigger signal for acquiring the data surrounding the anomalous or identifiable event from the input signal.
4. The method as recited in claim 3 wherein the types of trigger generators include one or more of a frequency domain trigger generator, a time domain trigger generator, a frequency modulation domain trigger generator and a modulation domain trigger generator.
5. The method as recited in claim 4 wherein the modulation domain trigger generator includes one or more of a QAM trigger generator, a CDMA trigger generator and an OFDM trigger generator.
6. The method as recited in claim 5 wherein each of the trigger generators include the steps of:
converting the input signal to a specified domain according to the type of the trigger generator; and
processing the converted input signal in the specified domain in response to specified trigger criteria to generate the trigger signal when the criteria are satisfied.
7. The method as recited in any of claims 3-6 wherein the input signal comprises a signal selected from the group consisting of a realtime signal, a stored signal and a simulated signal.
8. A multi-domain trigger generator for acquiring data surrounding an anomalous or identifiable event within an input signal comprising:
a plurality of trigger generators in parallel, each trigger generator being of a different type and receiving the input signal as an input and providing a trigger signal as an output; and
means for combining the trigger signals from the plurality of trigger generators to produce an acquisition trigger for acquiring the data surrounding the anomalous or identifiable event from the input signal.
9. The multi-domain trigger generator as recited in claim 8 wherein the trigger generators include one or more of a frequency domain trigger generator, a time domain trigger generator, a frequency modulation domain trigger generator and a modulation domain trigger generator.
10. The multi-domain trigger generator as recited in claim 9 wherein the modulation domain trigger generator includes one or more of a QAM trigger generator, a CDMA trigger generator and an OFDM trigger generator.
11. The multi-domain trigger generator as recited in claim 10 wherein each of the trigger generators comprise:
means for converting the input signal to a specified domain according to the type of the trigger generator; and
means for processing the converted input signal in the specified domain in response to specified trigger criteria to generate the trigger signal when the criteria are satisfied.
12. The apparatus as recited in any of claims 8-12 wherein the input signal comprises a signal selected from the group consisting of a realtime signal, a stored signal and a simulated signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of fabricating a FinFET, the method comprising:
forming a hard mask pattern on a semiconductor substrate;
etching the semiconductor substrate, using the hard mask pattern as an etching mask, to form a trench therein, the trench defining an active region;
forming an isolation layer that fills the trench and covers sidewalls of the hard mask pattern;
forming a photoresist pattern having a groove extending across the hard mask pattern;
etching the isolation layer, using the photoresist pattern and the hard mask pattern as an etching mask, to expose both sidewalls of the active region;
removing the photoresist pattern;
recessing sidewalls of the exposed active region to form a fin;
removing the hard mask pattern to expose an upper surface of the fin; and
forming a gate electrode that covers the exposed upper surface and sidewalls of the fin, wherein the gate electrode is insulated from the fin.
2. The method as recited in claim 1, further comprising forming a channel stopping region by implanting channel ions onto the semiconductor substrate before forming the hard mask pattern.
3. The method as recited in claim 2, wherein the hard mask pattern includes a lower hard mask pattern and an upper hard mask pattern, which are sequentially stacked.
4. The method as recited in claim 3, wherein forming the isolation layer includes:
forming an insulating layer on the semiconductor substrate having the hard mask pattern; and
planarizing the insulating layer until an upper surface of the lower hard mask pattern is exposed.
5. The method as recited in claim 4, further comprising selectively recessing the isolation layer after forming the isolation layer.
6. The method as recited in claim 3, wherein the hard mask pattern further includes a pad oxide layer.
7. The method as recited in claim 1, wherein forming the gate electrode includes:
forming a gate insulating layer that covers the upper surface and sidewalls of the fin;
forming a gate conductive layer and a gate hard mask layer overlying the gate insulating layer; and
sequentially patterning the gate hard mask layer and the gate conductive layer.
8. The method as recited in claim 7, further comprising forming source and drain regions, after forming the gate electrode.
9. The method as recited in claim 1, further comprising forming a channel stopping layer on the recessed active region between the fin and the isolation layer.
10. The method as recited in claim 1, wherein recessing sidewalls of the exposed active region comprises using an isotropic etching technique.
11. The method as recited in claim 1, wherein a width of the recessed active region is greater than a width of the fin.
12. The method as recited in claim 5, further comprising selectively recessing the isolation layer before forming the photoresist pattern.