Author: claimsbot

1. A driver circuit comprising:
a constant current supply generating a constant current;
a changeover circuit connecting a gate of an insulated gate device in turn-on to a power supply potential side via the constant current supply and connecting the gate of the insulated gate device in turn-off to a ground potential side;
a slope setting circuit setting a gate voltage waveform of the insulated gate device; and
an operational amplifier driving the gate of the insulated gate device based on a difference between a detected value of a gate voltage of the insulated gate device and a set value of the gate voltage set in the slope setting circuit.
2. The driver circuit according to claim 1, wherein the changeover circuit connects the gate of the insulated gate device to a power supply potential side based on a trigger input; and wherein the slope setting circuit generates the gate voltage waveform of the insulated gate device based on the trigger input.
3. The driver circuit according to claim 2, wherein the constant current supply comprises:
a first transistor having a resistor connected to a drain side thereof;
a second transistor constituting a current mirror together with the first transistor, the second transistor generating the constant current determined by a resistance value of the resistor and a reference voltage; and
a third transistor constituting a current mirror together with the second transistor, the third transistor comprising a drain connected to the gate of the insulated gate device.
4. The driver circuit according to claim 3, wherein the driver circuit further comprises:
a fourth transistor connected in series to the second transistor; and
a fifth transistor switching the fourth transistor for making a current flow through the resistor.
5. The driver circuit according to claim 1, wherein the constant current supply comprises:
a first transistor having a resistor connected to a drain side thereof;
a second transistor constituting a current mirror together with the first transistor, the second transistor generating the constant current determined by a resistance value of the resistor and a reference voltage; and
a third transistor constituting a current mirror together with the second transistor, the third transistor comprising a drain connected to the gate of the insulated gate device.
6. The driver circuit according to claim 5, wherein the driver circuit further comprises:
a fourth transistor connected in series to the second transistor; and
a fifth transistor switching the fourth transistor for making a current flow through the resistor.
7. The driver circuit according to claim 1, wherein the driver circuit sets an upper limit value of an output voltage from the slope setting circuit based on a value proportional to a power supply voltage of the driver circuit.
8. The driver circuit according to claim 1, wherein a voltage in the gate voltage waveform set by the slope setting circuit increases exponentially.
9. The driver circuit according to claim 8, wherein the slope setting circuit comprises:
a constant current supply generating a constant current;
a current mirror circuit generating a current proportional to the current generated by the constant current supply;
a series circuit comprising a resistor and a capacitor, the series circuit being connected to an output terminal of the slope setting circuit; and
a switching device triggered by a trigger input for making the current generated by the current mirror circuit flow to the series circuit.
10. The driver circuit according to claim 1, wherein a voltage in the gate voltage waveform set by the slope setting circuit increases linearly.
11. The driver circuit according to claim 10, wherein the slope setting circuit comprises:
a constant current supply generating a constant current;
a current mirror circuit generating a current proportional to the current generated by the constant current supply;
a capacitor connected to an output terminal of the slope setting circuit; and
a switching device triggered by the trigger input for making the current generated by the current mirror circuit flow to the capacitor.
12. The driver circuit according to claim 1, wherein the slope setting circuit comprises:
a first voltage waveform setting section making a set value of the gate voltage waveform of the insulate gate device increase exponentially;
a second voltage waveform setting section making the set value of the gate voltage waveform of the insulate gate device increase linearly; and
a voltage waveform selecting section selectively outputting any of the gate voltage waveform set by the first voltage waveform setting section and the gate voltage waveform set by the second voltage waveform setting section.
13. A driver circuit comprising:
a slope setting circuit that sets a gate voltage waveform of an insulated gate device; and
an operational amplifier that drives a gate of the insulated gate device based on a difference between a detected value of a gate voltage of the insulated gate device and a set value of the gate voltage set in the slope setting circuit;
wherein a voltage in the gate voltage waveform set by the slope setting circuit increases exponentially; and
wherein the slope setting circuit comprises:
a constant current supply generating a constant current;
a current mirror circuit generating a current proportional to the current generated by the constant current supply;
a series circuit comprising a resistor and a capacitor, the series circuit being connected to an output terminal of the slope setting circuit; and
a switching device triggered by a trigger input for making the current generated by the current mirror circuit flow to the series circuit.
14. A driver circuit comprising:
a slope setting circuit that sets a gate voltage waveform of an insulated gate device; and
an operational amplifier that drives a gate of the insulated gate device based on a difference between a detected value of a gate voltage of the insulated gate device and a set value of the gate voltage set in the slope setting circuit;
wherein a voltage in the gate voltage waveform set by the slope setting circuit increases linearly; and
wherein the slope setting circuit comprises:
a constant current supply generating a constant current;
a current mirror circuit generating a current proportional to the current generated by the constant current supply;
a capacitor connected to an output terminal of the slope setting circuit; and
a switching device triggered by the trigger input for making the current generated by the current mirror circuit flow to the capacitor.
15. A driver circuit comprising:
a slope setting circuit that sets a gate voltage waveform of an insulated gate device; and
an operational amplifier that drives a gate of the insulated gate device based on a difference between a detected value of a gate voltage of the insulated gate device and a set value of the gate voltage set in the slope setting circuit;
wherein the slope setting circuit comprises:
a first voltage waveform setting section making a set value of the gate voltage waveform of the insulate gate device increase exponentially;
a second voltage waveform setting section making the set value of the gate voltage waveform of the insulate gate device increase linearly; and
a voltage waveform selecting section selectively outputting any of the gate voltage waveform set by the first voltage waveform setting section and the gate voltage waveform set by the second voltage waveform setting section.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for storing a subtree in memory, the subtree including one or more leaf arrays and a plurality of tree arrays, a path of tree arrays includes a sequence of tree arrays along any route from the root of the subtree to any leaf of the subtree, the method comprising:
storing said one or more leaf arrays in a first set of memory channels of N+1 sets of memory channels, said N+1 sets of memory channels including N sets of memory channels plus the first set of memory channels; and
storing paths of the plurality of tree arrays in said N sets of memory channels, wherein for each particular path of tree arrays: a constraint that each tree array of the plurality of tree arrays associated with said particular path is stored in a different one of said N sets of memory channels; and wherein said tree arrays at a same level of tree arrays in the subtree are distributed among said N sets of memory channels that are available for a particular tree array given said constraint that each tree array of the plurality of tree arrays associated with a specific path is stored in a different one of said N sets of memory channels.
2. The method of claim 1, comprising identifying the first set of memory channels of said N+1 sets of memory channels based on an occupancy level of said N+1 sets of memory channels.
3. The method of claim 2, wherein the first set of memory channels includes the most available space of said N+1 sets of memory channels when said identifying the first set of memory channels is performed.
4. The method of claim 2, wherein the first set of memory channels includes the least available space of said N+1 sets of memory channels when said identifying the first set of memory channels is performed.
5. The method of claim 1, comprising identifying, based on an occupancy level of said N sets of memory channels, in which of said N sets of memory channels to store said paths.
6. The method of claim 5, comprising selecting a particular memory channel set of said N sets of memory channels to store a particular one of said paths, the particular memory channel set including the most available space of said N sets of memory channels at time of said selecting the particular memory channel set.
7. The method of claim 5, comprising selecting a particular memory channel set of said N sets of memory channels to store a particular one of said paths, the particular memory channel set including the least available space of said N sets of memory channels at time of said selecting the particular memory channel set.
8. The method of claim 1, wherein each of said N+1 sets of memory channels comprises a single memory channel.
9. The method of claim 1, wherein said storing one or more leaf arrays includes identifying a block of memory in an unused block data structure.
10. The method of claim 1, wherein said storing one or more leaf arrays includes:
identifying that there is no block of memory indicated as available in an unused block data structure; and
allocating a new memory page in the first memory channel.
11. The method of claim 1, wherein said storing said paths of the plurality of tree arrays includes identifying a block of memory in an unused block data structure.
12. The method of claim 1, wherein said storing said paths of the plurality of tree arrays includes:
identifying that there is no block of memory indicated as available in an unused block data structure; and
allocating a new memory page in one of said N sets of memory channels.
13. The method of claim 1, further comprising: initiating a memory compaction operation in response to an occupancy or a fragmentation level of at least one of said N sets of memory channels.
14. The method of claim 13, wherein said memory compaction operation includes storing a group of all said tree arrays stored in a single one of said N sets of memory channels which requires a largest storage space of that required by groups of all said leaf arrays stored in any one of the N sets of memory channels in a particular one of said N sets of memory channels having a greatest amount of storage space available for storing tree arrays.
15. The method of claim 13, wherein said memory compaction operation includes:
identifying an available space ordering based on an occupancy level of each of said N sets of memory channels;
identifying a storage requirement ordering based on the storage requirement of each of the plurality of tree arrays; and
storing the plurality of tree arrays in said N sets of memory channels based on the available space and storage requirement orderings.
16. The method of claim 1, further comprising: initiating a memory compaction operation in response to an occupancy or a fragmentation level of the first set of memory channels.
17. The method of claim 1, further comprising: initiating a memory compaction operation in response to an occupancy or a fragmentation level of at least one of said N+1 sets of memory channels.
18. The method of claim 17, wherein said memory compaction operation includes:
identifying whether (1) a tree array storage requirement for a group of all said tree arrays stored in a single one of said N sets of memory channels which requires a largest storage space of that required by groups of all said leaf arrays stored in any one of the N sets of memory channels or (2) a leaf array storage requirement for said one or more leaf arrays requires more storage space; and
storing the groups of said one or more leaf arrays identified as requiring more storage space in a particular one of said N+1 sets of memory channels having a greatest amount of storage space available.
19. The method of claim 17, wherein said memory compaction operation includes:
identifying an available space ordering based on an occupancy level of each of said N+1 sets of memory channels;
identifying a storage requirement ordering based on the storage requirement of each of the plurality of tree arrays and said one or more leaf arrays; and
storing the plurality of tree arrays and said one or more leaf arrays in said N+1 sets of memory channels based on the available space and storage requirement orderings.
20. An apparatus for storing a subtree in memory, the subtree including one or more leaf arrays and a plurality of tree arrays, a path of tree arrays includes a sequence of tree arrays along any route from the root of the subtree to any leaf of the subtree, the apparatus comprising:
means for storing said one or more leaf arrays in a first set of memory channels of N+1 sets of memory channels, said N+1 sets of memory channels including N sets of memory channels plus the first set of memory channels; and
means for storing paths of the plurality of tree arrays in said N sets of memory channels, wherein for each particular path of tree arrays: a constrain that each tree array of the plurality of tree arrays associated with said particular path is stored in a different one of said N sets of memory channels; and wherein said tree arrays at a same level of tree arrays in the subtree are distributed among said N sets of memory channels that are available for a particular tree array given said constraint that each tree array of the plurality of tree arrays associated with a specific path is stored in a different one of said N sets of memory channels.
21. The apparatus of claim 20, comprising means for identifying the first set of memory channels of said N+1 sets of memory channels based on an occupancy level of said N+1 sets of memory channels.
22. The apparatus of claim 20, comprising means for identifying, based on an occupancy level of said N sets of memory channels, in which of said N sets of memory channels to store said paths of the plurality of tree arrays.
23. The apparatus of claim 20, comprising means for performing a memory compaction operation on the subtree.
24. A method for storing a subtree in memory, the subtree including one or more leaf arrays and a plurality of tree arrays, a path of tree arrays includes a sequence of tree arrays along any route from the root of the subtree to any leaf of the subtree, the method comprising:
storing said one or more leaf arrays in a first set of memory channels of N+1 sets of memory channels, said N+1 sets of memory channels including N sets of memory channels plus the first set of memory channels; and
storing paths of the plurality of tree arrays in said N sets of memory channels, wherein each tree array of the plurality of tree arrays associated with one of said paths is stored in a different one of said N sets of memory channels;
wherein said storing one or more leaf arrays includes: identifying that there is no block of memory indicated as available in an unused block data structure; and allocating a new memory page in the first memory channel.
25. A method for storing a subtree in memory, the subtree including one or more leaf arrays and a plurality of tree arrays, a path of tree arrays includes a sequence of tree arrays along any route from the root of the subtree to any leaf of the subtree, the method comprising:
storing said one or more leaf arrays in a first set of memory channels of N+1 sets of memory channels, said N+1 sets of memory channels including N sets of memory channels plus the first set of memory channels; and
storing paths of the plurality of tree arrays in said N sets of memory channels, wherein each tree array of the plurality of tree arrays associated with one of said paths is stored in a different one of said N sets of memory channels;
wherein said storing said paths of the plurality of tree arrays includes: identifying that there is no block of memory indicated as available in an unused block data structure; and allocating a new memory page in one of said N sets of memory channels.
26. A method for storing a subtree in memory, the subtree including one or more leaf arrays and a plurality of tree arrays, a path of tree arrays includes a sequence of tree arrays along any route from the root of the subtree to any leaf of the subtree, the method comprising:
storing said one or more leaf arrays in a first set of memory channels of N+1 sets of memory channels, said N+1 sets of memory channels including N sets of memory channels plus the first set of memory channels;
storing paths of the plurality of tree arrays in said N sets of memory channels, wherein each tree array of the plurality of tree arrays associated with one of said paths is stored in a different one of said N sets of memory channels; and
initiating a memory compaction operation in response to an occupancy or a fragmentation level of at least one of said N sets of memory channels;
wherein said memory compaction operation includes storing a group of all said tree arrays stored in a single one of said N sets of memory channels which requires a largest storage space of that required by groups of all said leaf arrays stored in any one of the N sets of memory channels in a particular one of said N sets of memory channels having a greatest amount of storage space available for storing tree arrays.
27. A method for storing a subtree in memory, the subtree including one or more leaf arrays and a plurality of tree arrays, a path of tree arrays includes a sequence of tree arrays along any route from the root of the subtree to any leaf of the subtree, the method comprising:
storing said one or more leaf arrays in a first set of memory channels of N+1 sets of memory channels, said N+1 sets of memory channels including N sets of memory channels plus the first set of memory channels;
storing paths of the plurality of tree arrays in said N sets of memory channels, wherein each tree array of the plurality of tree arrays associated with one of said paths is stored in a different one of said N sets of memory channels; and
initiating a memory compaction operation in response to an occupancy or a fragmentation level of at least one of said N sets of memory channels;
wherein said memory compaction operation includes: identifying an available space ordering based on an occupancy level of each of said N sets of memory channels; identifying a storage requirement ordering based on the storage requirement of each of the plurality of tree arrays; and storing the plurality of tree arrays in said N sets of memory channels based on the available space and storage requirement orderings.
28. A method for storing a subtree in memory, the subtree including one or more leaf arrays and a plurality of tree arrays, a path of tree arrays includes a sequence of tree arrays along any route from the root of the subtree to any leaf of the subtree, the method comprising:
storing said one or more leaf arrays in a first set of memory channels of N+1 sets of memory channels, said N+1 sets of memory channels including N sets of memory channels plus the first set of memory channels;
storing paths of the plurality of tree arrays in said N sets of memory channels, wherein each tree array of the plurality of tree arrays associated with one of said paths is stored in a different one of said N sets of memory channels; and
initiating a memory compaction operation in response to an occupancy or a fragmentation level of at least one of said N+1 sets of memory channels;
wherein said memory compaction operation includes: identifying whether (1) a tree array storage requirement for a group of all said tree arrays stored in a single one of said N sets of memory channels which requires a largest storage space of that required by groups of all said leaf arrays stored in any one of the N sets of memory channels or (2) a leaf array storage requirement for said one or more leaf arrays requires more storage space; and storing the groups of said one or more leaf arrays identified as requiring more storage space in a particular one of said N+1 sets of memory channels having a greatest amount of storage space available.
29. A method for storing a subtree in memory, the subtree including one or more leaf arrays and a plurality of tree arrays, a path of tree arrays includes a sequence of tree arrays along any route from the root of the subtree to any leaf of the subtree, the method comprising:
storing said one or more leaf arrays in a first set of memory channels of N+1 sets of memory channels, said N+1 sets of memory channels including N sets of memory channels plus the first set of memory channels;
storing paths of the plurality of tree arrays in said N sets of memory channels, wherein each tree array of the plurality of tree arrays associated with one of said paths is stored in a different one of said N sets of memory channels; and
initiating a memory compaction operation in response to an occupancy or a fragmentation level of at least one of said N+1 sets of memory channels;
wherein said memory compaction operation includes: identifying an available space ordering based on an occupancy level of each of said N+1 sets of memory channels; identifying a storage requirement ordering based on the storage requirement of each of the plurality of tree arrays and said one or more leaf arrays; and storing the plurality of tree arrays and said one or more leaf arrays in said N+1 sets of memory channels based on the available space and storage requirement orderings.

1. A battery charger comprising:
a circuit, and
a plurality of charging pins,
the circuit comprising a microcontroller,
each pin of the plurality of charging pins electrically coupled to the circuit,
where the microcontroller sets a state of each charging pin of the plurality of charging pins.
2. The battery charger of claim 1 where the state of each charging pin is selected from the group consisting of a positive pin, a ground pin, a communications pin, a trigger pin, and an unused pin.
3. The battery charger of claim 1 where the microcontroller sets the state of each charging pin of the plurality of charging pins after determining which charging pin of the plurality of charging pins is in electrical contact with a trigger contact of a device.
4. The battery charger of claim 1 where the plurality of charging pins are arranged such that they exhibit approximate rotational symmetry around a point.
5. The battery charger of claim 1 further comprising an electrical connector.
6. The battery charger of claim 1, further comprising a magnet positioned against the body such that a magnetic field of the magnet attracts a device against the tips of the plurality of charging pins.
7. The battery charger of claim 6 where the magnet comprises one or more holes arranged such that one or more of the plurality of charging pins passes through at least one of the one or more holes.
8. A battery charger comprising:
a body,
an electrical connector,
a circuit, and
a plurality of charging pins,
the circuit comprising a microcontroller,
the electrical connector electrically coupled to the circuit,
the body comprising a cavity having a rear surface,
each pin of the plurality of charging pins electrically coupled to the microcontroller,
the plurality of charging pins disposed such that a tip of each charging pin of the plurality of charging pins extend above the rear surface of the cavity,
where the microcontroller sets a state of each charging pin of the plurality of charging pins.
9. The battery charger of claim 8 where the state of each charging pin is selected from the group consisting of a positive pin, a ground pin, a communications pin, a trigger pin, and an unused pin.
10. The battery charger of claim 8 where the microcontroller sets the state of each charging pin of the plurality of charging pins after determining which charging pin of the plurality of charging pins is in electrical contact with a trigger contact of a device.
11. The battery charger of claim 8 where the plurality of charging pins are arranged such that they exhibit approximate rotational symmetry around a point.
12. The battery charger of claim 8 further comprising a first plurality of load switches and a second plurality of load switches, the number of load switches of the first plurality of load switches equal to the number of charging pins of the plurality of charging pins, the number of load switches of the second plurality of load switches equal to the number of charging pins of the plurality of charging pins, where each charging pin of the plurality of charging pins is electrically connected to a load switch of the first plurality of load switches, and each load switch of the first plurality of load switches is electrically connected to a charging pin of the plurality of charging pins, and where each charging pin of the plurality of charging pins is electrically connected to a load switch of the second plurality of load switches, and each load switch of the second plurality of load switches is electrically connected to a charging pin of the plurality of charging pins, and each load switch of the first plurality of load switches is electrically connected to the microcontroller, and each load switch of the second plurality of load switches is electrically connected to the microcontroller; and
where when the circuit is energized, the microcontroller senses a voltage from each charging pin of the plurality of charging pins until a voltage within a voltage range is detected from one charging pin of the plurality of charging pins, whereupon the microcontroller sets the state of each charging pin of the plurality of charging pins according to a predetermined relative layout by enabling a subset of load switches of the first plurality of load switches and the second plurality of load switches.
13. The battery charger of claim 12 further comprising a power-on-reset controller and a third plurality of load switches, where the power-on-reset controller is electrically coupled to the microcontroller, and where each charging pin of the plurality of charging pins is electrically connected to a load switch of the third plurality of load switches, and each load switch of the third plurality of load switches is electrically connected to a charging pin of the plurality of charging pins, and each load switch of the third plurality of load switches is electrically connected to the power-on-reset controller; and where the power-on-reset controller resets the circuit when power is connected to the electrical connector.
14. A method for operating a battery charger, the method comprising:
detecting a device coupling to the battery charger,
scanning a plurality of voltages from a plurality of electrical lines,
evaluating which voltage of the plurality of voltages is within a predetermined voltage range,
determining an orientation of the device based upon the voltage that is within the predetermined voltage range, and
configuring a state of each electrical line of the plurality of electrical lines according to a predetermined pattern relative to the orientation.
15. The method for operating a battery charger of claim 14 further comprising:
detecting a voltage of an electrical line corresponding to a battery of the device, and
when the voltage is below a threshold then setting a charge controller to a charging state.
16. The method for operating a battery charger of claim 14 further comprising:
detecting a voltage of an electrical line corresponding to a battery of the device, and
when the voltage exceeds a threshold then setting the charge controller to a maintenance state.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A compound of formula (I),
the N-oxide forms, the pharmaceutically acceptable addition salts and the stereo-chemically isomeric forms thereof, wherein
each n is an integer with value 0, 1 or 2 and when n is 0 then a direct bond is intended;
each m is an integer with value 1 or 2;
each X is independently N or CH;
each Y is independently O, S, or NR4; wherein
each R4 is hydrogen, C1-6alkyl, C1-6alkyloxyC1-6alkyl, C3-6cycloalkyl, C3-6cycloalkylmethyl, phenylC1-6alkyl, \u2014C(\u2550O)\u2014CHR5R6 or \u2014S(\u2550O)2\u2014N(CH3)2; wherein
each R5 and R6 is independently hydrogen, amino, C1-6alkyl or aminoC1-6alkyl; and
when Y is NR4 and R2 is on the 7-position of the indolyl then R2 and R4 together can form the bivalent radical
\u2014(CH2)2\u2014\u2003\u2003(a-1), or
\u2014(CH2)3\u2014\u2003\u2003(a-2);
R1 is hydrogen, C1-6alkyl, hydroxyC1-6alkyl, C1-6alkylsulfonyl, C1-6alkylcarbonyl or mono- or di(C1-6alkyl)aminosulfonyl;
R2 is hydrogen, hydroxy, amino, halo, C1-6alkyl, cyano, C2-6alkenyl, polyhaloC1-6alkyl, nitro, phenyl, C1-6alkylcarbonyl, hydroxycarbonyl, C1-6alkylcarbonylamino, C1-6alkyloxy, or mono- or di(C1-6alkyl)amino;
R3 is hydrogen, C1-6alkyl, or C1-6alkyloxy; and
when R2 and R3 are on adjacent carbon atoms, they can form the bivalent radical \u2014O\u2014CH2\u2014O\u2014.
2. A compound according to claim 1 wherein
each n is an integer with value 0 or 1; each R4 is hydrogen, C1-6alkyl, C1-6alkyloxyC1-6alkyl, C3-6cycloalkyl or phenylC1-6alkyl; R1 is hydrogen, C1-6alkyl, hydroxyC1-6alkyl, C1-6alkylcarbonyl or C1-6alkylsulfonyl; and R2 is hydrogen, halo, C1-6alkyl, cyano, nitro, polyhaloC1-6alkyl or C1-6alkyloxy.
3. A compound according to claim 1 wherein
wherein each n is an integer with value 1; each m is an integer with value 1; each X is independently N; each Y is independently NR4; each R4 is C1-6alkyl; R1 is hydrogen; R2 is hydrogen or halo; and R3 is hydrogen.
4. A compound selected from the group consisting of compound No. 1a, compound No. 30, compound No. 39 and compound No. 50:
and the N-oxide forms, the pharmaceutically acceptable addition salts and the stereo-chemically isomeric forms thereof.
5. A pharmaceutical composition comprising pharmaceutically acceptable carriers and as an active ingredient a therapeutically effective amount of a compound as claimed in claim 1.
6. A process of preparing a pharmaceutical composition as claimed in claim 5 wherein the pharmaceutically acceptable carriers and the compound as claimed in claim 5 are intimately mixed.
7. A combination of an anti-cancer agent and a compound as claimed in claim 1.
8. A process for preparing a compound as claimed in claim 1, said process comprising the steps of:
a) reacting an intermediate of formula (II), wherein Q is tetrahydropyranyloxyaminocarbonyl, herein referred to as an intermediate of formula (II-a), with trifluoro acetic acid, yielding a hydroxamic acid of formula (I)
b) reacting an intermediate of formula (II), wherein Q is C1-2alkyloxycarbonyl, herein referred to as intermediates of formula (II-c), with hydroxylamine, in the presence of a base and in methanol with the production of a hydroxamic acid of formula (I)
9. A compound of formula (II),
the N-oxide forms, the pharmaceutically acceptable addition salts and the stereo-chemically isomeric forms thereof, wherein
each n is an integer with value 0, 1 or 2 and when n is 0 then a direct bond is intended;
each m is an integer with value 1 or 2;
each X is independently N or CH;
each Y is independently O, S, or NR4; wherein
each R4 is hydrogen, C1-6alkyl, C1-6alkyloxyC1-6alkyl, C3-6cycloalkyl, C3-6cycloalkylmethyl, phenylC1-6alkyl, \u2014C(\u2550O)\u2014CHR5R6 or \u2014S(\u2550O)2\u2014N(CH3)2; wherein
each R5 and R6 is independently hydrogen, amino, C1-6alkyl or aminoC1-6alkyl; and
when Y is NR4 and R2 is on the 7-position of the indolyl then R2 and R4 together can form the bivalent radical
\u2014(CH2)2\u2014\u2003\u2003(a-1), or
\u2014(CH2)3\u2014\u2003\u2003(a-2);
R1 is hydrogen, C1-6alkyl, hydroxyC1-6alkyl, C1-6alkylsulfonyl, C1-6alkylcarbonyl or mono- or di(C1-6alkyl)aminosulfonyl;
R2 is hydrogen, hydroxy, amino, halo, C1-6alkyl, cyano, C2-6alkenyl, polyhaloC1-6alkyl, nitro, phenyl, C1-6alkylcarbonyl, hydroxycarbonyl, C1-6alkylcarbonylamino, C1-6alkyloxy, or mono- or di(C1-6alkyl)amino;
R3 is hydrogen, C1-6alkyl, or C1-6alkyloxy;
when R2 and R3 are on adjacent carbon atoms, they can form the bivalent radical \u2014O\u2014CH2\u2014O\u2014; and
Q is C1-2alkyloxycarbonyl, hydroxycarbonyl or tetrahydropyranyloxyaminocarbonyl.
10. A process for preparing a compound as claimed in claim 9, said process comprising the steps of:
a) reacting a compound of formula (II), wherein Q is hydroxycarbonyl, herein referred to as compounds of formula (II-b), with an intermediate of formula (III) in the presence of reagents comprising N\u2032-(ethylcarbonimidoyl)-N,N-dimethyl-1,3-propanediamine, monohydrochloride (EDC) or 1-hydroxy-1H-benzotriazole (HOBT) with the formation of a compound of formula (II-a),
b) reacting an intermediate of formula (VI) with the carboxaldehyde of formula (V), wherein t is an integer with value 0 or 1, and when t is 0 then a direct bond is intended, in the presence of sodium borohydride, with the formation of a compound of formula (II-a),
c) reacting a compound of formula (II), wherein Q is methyl- or ethyloxycarbonyl (C1-2alkyl), herein referred to as compounds of formula (II-c), with an acidic solution or basic solution, with the formation of a compound of formula (II-b),
d) reacting the carboxylic acid ethyl ester of formula (IV) with the carboxaldehyde of formula (V), in the presence of sodium borohydride in methanol, with the formation of a compound of formula (II-c),
e) reacting an intermediate of formula (XIV) with the intermediate of formula (XV), in the presence of sodium borohydride in methanol,
with the formation of a compound of formula (II-c),
f) reacting an intermediate of formula (X) with an intermediate of formula (XI) wherein W is group comprising fluoro, chloro, bromo or iodo, or methylsulfonyloxy, with the formation of a compound of formula (II-c), or
g) reacting an intermediate of formula (XII) with an intermediate of formula (XIII), wherein W described above, with the formation of a compound of formula (II-c)
11. A pharmaceutical composition comprising pharmaceutically acceptable carriers and as an active ingredient a therapeutically effective amount of a compound as claimed in claim 2.
12. A pharmaceutical composition comprising pharmaceutically acceptable carriers and as an active ingredient a therapeutically effective amount of a compound as claimed in claim 3.
13. A pharmaceutical composition comprising pharmaceutically acceptable carriers and as an active ingredient a therapeutically effective amount of a compound as claimed in claim 4.
14. A combination of an anti-cancer agent and a compound as claimed in claim 2.
15. A combination of an anti-cancer agent and a compound as claimed in claim 3.
16. A combination of an anti-cancer agent and a compound as claimed in claim 4.
17. A compound of the following structure:
and the N-oxide forms, the pharmaceutically acceptable addition salts and the stereo-chemically isomeric forms thereof.
18. A compound selected from the group consisting of:
and the N-oxide forms, the pharmaceutically acceptable addition salts and the stereo-chemically isomeric forms thereof.
19. A pharmaceutical composition comprising pharmaceutically acceptable carriers and as an active ingredient a therapeutically effective amount of a compound as claimed in claim 17.
20. A pharmaceutical composition comprising pharmaceutically acceptable carriers and as an active ingredient a therapeutically effective amount of a compound as claimed in claim 18.
21. A combination of an anti-cancer agent and a compound as claimed in claim 17.
22. A combination of an anti-cancer agent and a compound as claimed in claim 18.
23. The combination of claim 7, wherein said anti-cancer agent is a DNA methyl transferase inhibitors.
24. The combination of claim 21, wherein said anti-cancer agent is a DNA methyl transferase inhibitors.
25. The combination of claim 22, wherein said anti-cancer agent is a DNA methyl transferase inhibitors.