1. A deep power down circuit to save power in a low power memory chip, comprising:
a) plurality of pass gate circuits each coupled to outputs of charge pump circuits and voltage regulators internal to a low power memory chip,
b) said pass gate circuits couple an external voltage of said low power memory chip to memory support circuits when the charge pumps, voltage regulators and voltage generators are turned off in a deep power down mode.
2. The deep power down circuit of claim 1, wherein said charge pumps and said voltage regulators are turned off at the beginning of a deep power down mode after a memory cell pre-charge is performed and pass gate circuits are turned on to provide power to said support circuits.
3. The deep power down circuit of claim 1, wherein said pass gate circuits are turned off and said charge pumps, voltage regulators and voltage generators are turned on at an end of the deep power down mode.
4. The deep power down circuit of claim 1, wherein said pass gate circuits are replaced by grounding gates that are activated in said deep power down mode to ground the outputs of the charge pumps and voltage regulators internal to said low power memory chip.
5. The deep power down circuit of claim 4, wherein a selected combination of said grounding gates and said pass gate circuits are used to replace the outputs of the charge pump circuits and voltage regulators when the low power memory chip is placed into said deep power down mode.
6. The deep power down circuit of claim 4, wherein said pass gate circuits and said grounding gates are not used and the outputs of said charge pump circuits and voltage regulator are allowed to float after being turned off in said deep power down mode.
7. The deep power down circuit of claim 6, wherein a select combination of said grounding gates, said pass gate circuits and the floating of the outputs of charge pump circuits and voltage regulators are used to replace the outputs of said charge pump circuits and voltage regulators when the low power memory chip is placed into said deep power down mode.
8. A method for reducing memory chip power during a deep power down mode, comprising:
a) preconditioning memory cells prior to applying a deep power down mode,
b) entering said deep power down mode and reducing power of a memory chip, comprising:
i) floating voltages used in preconditioning said memory cells,
ii) replacing internal memory chip voltages not related to preconditioning said memory cells with voltages derived from an external voltage of said memory chip.
9. The method of claim 8, wherein preconditioning the memory cells places said memory cells into a precharge state.
10. The method of claim 9, wherein floating voltages used in preconditioning said memory cell voltages, further comprises:
a) floating bit line voltages,
b) floating memory storage capacitor plate voltages,
c) floating memory cell substrate voltages.
11. The method of claim 8, wherein floating voltages not used in preconditioning said memory cell voltages includes turning off voltage regulators and charge pumps.
12. The method of claim 8, wherein replacing internal memory chip voltages not related to the preconditioning of said memory cell, further comprises:
a) turning off voltage regulators and charge pumps,
b) using pass gate circuits connecting voltages derived from an external chip voltage to replace said internal voltages from outputs of turned off voltage regulators and charge pumps.
13. The method of claim 12, wherein replacing internal memory chip voltages not related to the preconditioning of said memory cells with external derived voltages to prevent chip latch up upon exit from said deep power down mode.
14. The method of claim 12, wherein replacing internal memory chip voltages is by using grounding gates to ground the outputs of turned off voltage regulators and charge pumps.
15. The method of claim 14, wherein the outputs of said turned off voltage regulators and charge pumps are floated and not replaced with either said pass gate circuits and said grounding gates.
16. The method of claim 15, wherein the outputs of said turned off voltage regulators and said charge pumps are replaced with a select combination of pass gate circuits, grounding gates and the floating of said voltage regulators and said charge pumps.
17. A system for conserving memory chip power during a deep power down mode, comprising:
a) a means for turning off on-chip voltage regulators and charge pumps on a memory chip,
b) a means for replacing output voltages of said voltage regulators and charge pumps during a deep power down mode.
18. The system of claim 17, wherein the means for turning off on-chip regulators and charge pumps allows memory cell voltages to be floated.
19. The system of claim 17, wherein the means for turning off on-chip regulators and charge pumps eliminates standby power needed to maintain voltages created by said voltage regulators and said charge pumps.
20. The system of claim 17, wherein the means for replacing output voltages of said voltage regulators and said charge pumps during deep power down mode with voltages derived from an external memory chip voltage uses pass gate circuits.
21. The system of claim 20, wherein the means for replacing output voltages of said voltage regulators and said charge pumps prevents circuit latch up when the deep power down mode is removed and the memory chip returns to normal operation.
22. The system of claim 20, wherein the means for replacing the output voltage of said voltage regulators and charge pumps during deep power down mode uses a means to ground outputs of said voltage regulators and said charge pumps.
23. The system of claim 22, wherein the means for replacing the output voltage of said voltage regulators and charge pumps during deep power down mode floats the outputs of the voltage regulators and the charge pumps.
24. The system of claim 23, wherein the means for replacing the output voltage of said voltage regulators and charge pumps during deep power down mode uses a select combination of pass gate circuits, grounding gates and floating of the outputs of the charge pumps and voltage regulators.
25. A deep power down mode for low power memory chips, comprising:
a) a low power memory chip,
b) internal voltage circuits providing said memory chip with internal circuit power,
c) a pass gate circuit connecting an externally derived voltage to said internal voltage circuits,
d) a deep power down signal for controlling a reduced power of said memory chip,
e) said deep power down signal controlling said internal voltage circuits off and controlling pass gate circuits on during a deep power down mode to reduce power of said memory chip.
26. The deep power down mode of claim 25, wherein the internal voltage circuits are a plurality of voltage regulators and charge pump circuits.
27. The deep power down mode of claim 25, wherein said pass gate circuits couple said externally derived voltage to outputs of said internal voltage circuits during deep power down mode.
28. The deep power down mode of claim 25, wherein said pass gate circuits are replaced with grounding gates that ground outputs of said internal voltage circuits during deep power down mode.
29. The deep power down mode of claim 28, wherein said internal voltage circuits are turned off and the outputs of the internal voltage circuits are allowed to float during said deep power down mode.
30. The deep power down mode of claim 29, wherein a selected combination of said pass gate circuits, said grounding gates and floating outputs of the internal voltage circuits are used to reduce memory chip power during said deep power down mode.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A fault diagnosis apparatus for diagnosing a fault that occurs in an apparatus having a drive mechanism including a plurality of elements that include a driving component activated by current supply and a power transmission component that transmits a driving force of the driving component to another component, comprising:
a first signal detection unit that detects a first signal indicating an operation state of the drive mechanism within a predetermined period; and
a fault diagnosis unit that executes a fault diagnosis on each element of the drive mechanism based on a deviation of the first signal detected by the first signal detection unit from a normal range.
2. The fault diagnosis apparatus according to claim 1, wherein
the drive mechanism includes a plurality of driving components and a signal generation unit that generates a control signal capable of switching the plurality of driving components on and off individually,
the first signal detection unit includes a detection component used in common for the plurality of driving components by which the first signal is detected in a case where the signal generation unit controls one of the driving component to be on, and
the fault diagnosis unit executes the fault diagnosis on the plurality of elements including the plurality of driving components respectively based on the first signal of the plurality of driving components detected by the first signal detection unit in a state where the signal generation unit switches one of the plurality of driving components on.
3. The fault diagnosis apparatus according to claim 1, wherein
the fault diagnosis unit extracts a feature value adapted to execute the fault diagnosis based on the first signal detected by the first signal detection unit, and executes the fault diagnosis based on the feature value and a standard feature value indicating the normal range of the first signal.
4. The fault diagnosis apparatus according to claim 1, wherein
the fault diagnosis unit compares the first signal with pre-first signals that are previously obtained on each element of the plurality of elements in a state where the plurality of elements has no faults to determine which signal is corresponding to the first signal among the pre-first signals to specify which element has the fault or details of the fault.
5. The fault diagnosis apparatus according to claim 1, wherein
the first signal detection unit includes a current detection unit that detects a signal indicating an operation current applied to the driving component as the first signal.
6. The fault diagnosis apparatus according to claim 1, wherein
the first signal detection unit includes a vibration detection unit that detects a signal indicating a vibration occurring in the drive mechanism as the first signal.
7. The fault diagnosis apparatus according to claim 1, wherein
the drive mechanism is used for a transport system for transporting a transported object, and
the first signal detection unit includes a timing detection unit including a plurality of detection units that detects a passage of the transported object and a measurement unit that measures a transporting timing and a transporting time of the transported object as the first signal based on a detection signal obtained by the plurality of detection units.
8. The fault diagnosis apparatus according to claim 1, wherein
the fault diagnosis unit diagnoses the power transmission component that transmits the driving force of the driving component activated by current supply to another component which does not receive current supply in a case where the first signal is out of the normal range.
9. The fault diagnosis apparatus according to claim 1, wherein
the first signal detection unit includes a current detection unit that detects a signal indicating an operation current applied to the driving component as the first signal and a vibration detection unit that detects a signal indicating a vibration occurring in the drive mechanism as the first signal, and
the fault detection unit executes the fault diagnosis on the power transmission component that transmits the driving force of the driving component activated by current supply to another component by multi-dimensionally analyzing the operation current detected by the current detection unit and the vibration detected by the vibration detection unit whether these are in the corresponding normal range or not respectively.
10. The fault diagnosis apparatus according to claim 1, wherein
the drive mechanism includes a plurality of drive mechanisms,
the first signal detection unit includes a second signal detection unit that detects a second signal indicating an operation state of each drive mechanism on a normal operation state, and
the fault diagnosis unit includes a second determination unit that determines whether the drive mechanism has a fault or not based on the second signal detected by the second signal detection unit and a first determination unit that executes the fault diagnosis on each elements in the drive mechanism determined that the drive mechanism has a fault by the second determination unit.
11. The fault diagnosis apparatus according to claim 1, wherein
the fault diagnosis unit includes a forecast unit that forecasts a fault by comparing the first signal detected by the first signal detection unit with the normal range of the first signal.
12. The fault diagnosis apparatus according to claim 11, wherein
the first signal detection unit detects the first signal more than once, and
the forecast unit forecasts a fault by comparing a distribution of the first signal based on the first signal detected by the first signal detection unit more than once with a distribution indicating the normal range of the first signal.
13. The fault diagnosis apparatus according to claim 1, further comprises a notifying unit that notifies information of the fault diagnosis to a customer.
14. The fault diagnosis apparatus according to claim 13, wherein the notifying unit notifies at least one of a fault part, a status of a fault and a detail of a diagnosis with the first signal detected by the first signal detection unit to a customer.
15. The fault diagnosis apparatus according to claim 1, wherein the fault diagnosis unit executes the fault diagnosis based on an average value and a standard deviation indicating the normal range.
16. The fault diagnosis apparatus according to claim 1, wherein the fault diagnosis unit executes the fault diagnosis by comparing a value that each sampling data obtained by digitizing the first signal is raised to the second power and integrated with the normal range.
17. The fault diagnosis apparatus according to claim 16, wherein
the first signal detection unit obtains the first signal more than once,
the fault diagnosis unit obtains a plurality of values that each sampling data obtained by digitizing the first signal is raised to the second power and integrated, and calculates an average value and a standard deviation based on the plurality of values, and executes the fault diagnosis by comparing the average value and the standard deviation with an average value and a standard deviation indicating the normal range.
18. The fault diagnosis apparatus according to claim 1, wherein the fault diagnosis unit determines to be normal in case where a value of the first signal is in a range of an average value\xb1(a standard deviation\xd73) that indicates the normal range.