Author: claimsbot

1. An interconnect network for operation within a communication node, said network comprising,
a selectable number of local interconnect modules located proximate to each other and each having local transfer elements for transferring information between a plurality of local IO channels and for transferring information between said plurality of local IO channels and a plurality of non-local IO channels, and
an expanded interconnect module located proximate to said local interconnect modules and having coupling means for electrically coupling to said non-local IO channels, and expanded transfer elements for transferring information between said local interconnect modules.
2-26. (canceled)

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for initializing memory, comprising:
configuring a plurality of memory devices in parallel, wherein the plurality of memory devices receive a shared enable signal; and
assigning a unique volume address to each of the plurality of memory devices.
2. The method of claim 1, wherein assigning the unique volume address includes assigning two unique volume addresses to a particular one of the plurality of memory devices during the initialization, wherein the particular one of the plurality of memory devices includes two target volumes.
3. The method of claim 1, wherein the method includes reconfiguring the plurality of memory devices, and reassigning a unique volume address to each of the plurality of memory devices during a subsequent initialization.
4. The method of claim 1, wherein assigning the unique volume address includes assigning a unique non-fixed volume address.
5. The method of claim 1, wherein assigning the unique volume address includes assigning a unique volume address to each of the plurality of memory devices in sequence.
6. The method of claim 1, wherein assigning the unique volume address includes assigning one unique volume addresses to a particular one of the plurality of memory devices during the initialization, wherein the particular one of the plurality of memory devices includes one target volume.
7. The method of claim 1, wherein the method includes retiring a particular one of the plurality of memory devices such that the particular memory device does not have a unique volume address assigned thereto during a subsequent initialization.
8. The method of claim 1, wherein configuring the plurality of memory devices in parallel includes configuring the plurality of memory devices during an initialization, wherein the plurality of memory devices are in a linear daisy chain configuration.
9. The method of claim 8, wherein the method includes:
configuring the plurality of memory devices, and an additional memory device added to the linear daisy chain configuration, during a subsequent initialization; and
assigning a unique non-fixed volume address to each of the plurality of memory devices and to the additional memory device during the subsequent initialization.
10. A method for initializing memory, comprising:
setting a shared enable signal to a particular state, wherein the shared enable signal is coupled to a plurality of memory devices, and wherein the plurality of memory devices are arranged in a linear daisy chain configuration;
providing a reset command to each of the plurality of memory devices;
configuring the plurality of memory devices in parallel; and
assigning a unique volume address to each of the plurality of memory devices.
11. The method of claim 10, wherein assigning the unique volume address comprises assigning a unique volume address to each of the plurality of memory devices in sequence.
12. The method of claim 10, wherein assigning the unique volume address to each of the plurality of memory devices includes:
assigning a first volume address to a first of the plurality of memory devices in response to the first of the plurality of memory devices indicating support in response to a first query; and
assigning a second volume address to a second of the plurality of memory devices in response to the second of the plurality of memory devices indicating support in response to a second query.
13. The method of claim 10, wherein assigning comprises assigning the unique volume address to a particular one of the plurality of memory devices in response to the particular one of the plurality of memory devices indicating support in response to a respective query; and
wherein the method includes setting the shared enable signal to a different state in response to the respective query being unanswered.
14. The method of claim 13, wherein setting the shared enable signal to the different state includes deselecting each of the plurality of memory devices.
15. A method of configuring memory devices associated with a shared enable signal, wherein each of the memory devices has a respective chain input and wherein a reset command is provided to each of the memory devices, the method comprising:
if the memory devices are to be configured in parallel, configuring each of the memory devices responsive to the reset command regardless of a state of the respective chain input;
if the memory devices are to be configured sequentially, only configuring a respective one of memory devices if it has an active state on the respective chain input responsive to the reset command.
16. The method of claim 15, wherein configuring a memory device comprises loading trims on the memory device.
17. A memory controller, comprising:
a first interface for coupling the memory controller to a host; and
a second interface for coupling the memory controller to a plurality of memory devices arranged in a linear daisy chain configuration, wherein the memory controller is configured to:
set a shared enable signal to a particular state, wherein the shared enable signal is coupled to a plurality of memory devices, and wherein the plurality of memory devices are arranged in a linear daisy chain configuration;
provide a reset command to each of the plurality of memory devices;
configure the plurality of memory devices in parallel; and
assign a unique volume address to each of the plurality of memory devices.
18. The memory controller of claim 17, wherein the memory controller is configured to assign a unique non-fixed volume address to each of the plurality of memory devices in sequence.
19. The memory controller of claim 17, wherein the memory controller is configured to:
assign a first volume address to a first of the plurality of memory devices in response to the first of the plurality of memory devices indicating support in response to a first query; and
assigning a second volume address to a second of the plurality of memory devices in response to the second of the plurality of memory devices indicating support in response to a second query.
20. The memory controller of claim 17, wherein the memory controller is configured to assign the unique volume address to a particular one of the plurality of memory devices in response to the particular one of the plurality of memory devices indicating support in response to a respective query; and
wherein the memory controller is configured to set the shared enable signal to a different state in response to the respective query being unanswered.
21. The memory controller of claim 20, wherein the memory controller is configured to deselect each of the plurality of memory devices to set the shared enable signal to the different state.
22. The memory controller of claim 17, wherein the memory controller is configured to assign the unique volume address to one target volume within each of the plurality of memory devices.
23. The memory controller of claim 17, wherein the memory controller is configured to assign a unique volume address to each target volume within each of the plurality of memory devices.
24. A memory controller, comprising:
a first interface for coupling the memory controller to a host; and
a second interface for coupling the memory controller to a plurality of memory devices arranged in a linear daisy chain configuration, wherein the memory controller is configured to:
selectively configure the plurality of memory devices in sequence or in parallel; and
assign a unique volume address to each of the plurality of memory devices.
25. The memory controller of claim 24, wherein the memory controller is configured to configure the plurality of memory devices and to assign unique volume addresses at each initialization of the plurality of memory devices.
26. The memory controller of claim 24, wherein the memory controller is configured to configure a particular one of the plurality of memory devices prior to assigning the unique volume address to the particular one of the plurality of memory devices.
27. The memory controller of claim 24, wherein the memory controller includes a programmable option to configure the plurality of memory devices during the initialization in sequence or in parallel.
28. The memory controller of claim 27, wherein the memory controller is configured to provide a read status command to the plurality of memory devices prior to providing a reset command to a particular one of the plurality of memory devices responsive to the programmable option indicating serial configuration.
29. The memory controller of claim 27, wherein the memory controller is configured to provide a reset command to the plurality of memory devices prior to assigning a unique volume address to each of the plurality of memory devices.
30. A memory system, comprising:
a plurality of memory devices coupled in a linear daisy chain configuration; and
a memory controller coupled to the plurality of memory devices, wherein the memory controller is configured to:
provide a shared enable signal to the plurality of memory devices;
configure the plurality of memory devices in parallel during an initialization of the plurality of memory devices; and
assign a unique volume address to each of the plurality of memory devices during the initialization.
31. The memory system of claim 30 wherein each of the plurality of memory devices includes:
an input to receive the shared enable signal;
a chain input; and
a chain output;
wherein the chain output of a particular one of the plurality of memory devices is coupled to the chain input of a next one of the plurality of memory devices in the linear daisy chain configuration.
32. The memory system of claim 31, wherein:
the chain output of a particular one of the plurality of memory devices is driven to a first state responsive to the unique volume address being assigned to the particular one of the plurality of memory devices; and
the chain output being in the first state causes the particular one of the plurality of memory devices to be deselected.
33. The memory system of claim 31, wherein:
the memory controller is also configured to selectively configure the plurality of memory devices in sequence;
wherein if the controller is selectively configured to configure the devices in sequence, a particular one of the plurality of memory devices having a chain input in a first state is configured to:
receive a reset command from the memory controller;
be configured independently of a remainder of the plurality of memory devices;
have a unique volume address assigned thereto; and
have a chain output driven to the first state in response to the unique volume address being assigned thereto.
34. The memory system of claim 30, wherein the memory controller includes:
a first shared enable signal output coupled to a first volume in each of the plurality of memory devices; and
a second shared enable signal output coupled to a second volume in each of the plurality of memory devices;
wherein the memory controller is configured to assign the unique volume address to the first volume of each of the plurality of memory devices independently of the second volume of each of the plurality of memory devices.

1. A method for converting a plurality of powerlines in at least a building structure into a communication network for a plurality of users, the method comprising:
coupling an apparatus for communicating between a data source and at least one of a plurality of users through a powerline network, the apparatus comprising:
a datasource connection, the datasource connection coupled to a data source;
a powerline device coupled to the datasource connection, the powerline device being adapted to receive and transmit information in a first format from the datasource connection and adapted to receive and transmit information in a second format;
a virtual local area network device including a first inputoutput port and a plurality of second inputoutput ports, each of the second inputoutput ports numbered from 1 through N, where N is an integer greater than 1;
a plurality of modem devices coupled to the virtual local area network device, the plurality of modem devices numbered from 1 through N, each of the plurality of modem devices being coupled respectively to one of the plurality of second inputoutput ports, each of the plurality of modem devices also being coupled to one of a plurality of powerlines numbered from 1 through N, each of the plurality of powerlines being capable of communicating information to and from the data source;

allowing at least one of the users to communicate to the data source through one of the plurality of powerlines; and
denying access to at least one of the users from communicating to the data source through one of the plurality of powerlines.
2. The method of claim 1 wherein the building structure is an office building.
3. The method of claim 1 wherein the building structure is a residential home.
4. The method of claim 1 wherein the building structure is a multi-tenant building.
5. The method of claim 1, and further comprising coupling one or more of the apparatuses in a cascaded deployment, each apparatus serving a plurality of users.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of manufacturing a phase change memory device, comprising:
providing a semiconductor substrate having a cell area and a coreperi area defined therein;
forming a gate of a driving transistor in the coreperi area of the semiconductor substrate;
forming a strain stress supplying layer in the cell area of the semiconductor substrate and in the coreperi area of the semiconductor substrate along opposing sides of the gate;
simultaneously forming a junction word line in the cell area and forming sourcedrain of the driving transistor in the coreperi area by implanting impurities of a first conductivity into the strain stress supplying layer;
forming an interlayer insulating layer over the semiconductor substrate in which the junction word line and the sourcedrain are formed therein; and
forming switching diodes within the interlayer insulating layer that are connected the junction word line.
2. The method of claim 1, wherein the semiconductor substrate comprises a silicon substrate, and the strain stress supplying layer comprises a SiGe layer.
3. The method of claim 1, further comprising forming a buffer layer having a lattice property between that of the semiconductor substrate and that of the strain stress supplying layer on an exposed portion of the semiconductor substrate wherein forming the buffer layer is performed after forming the gate and before forming a strain stress supplying layer.
4. The method of claim 1, wherein the forming switching diodes includes:
forming diode contact holes exposing portions of the junction word line by etching the interlayer insulating layer;
forming a semiconductor layer to fill in the diode contact holes;
implanting impurities of a first conductivity into the semiconductor layer; and
implanting impurities of a second conductivity into the semiconductor layer.
5. The method of claim 4, wherein the forming semiconductor layer includes an epitaxial grown semiconductor layer which uses the junction word line as a base.
6. The method of claim 4, wherein forming the semiconductor layer includes depositing a polysilicon layer.
7. The method of claim 1, further comprising: after the forming switching diodes,
forming heating electrodes contacting the switching diodes;
forming phase change structures contacting the heating electrodes; and
forming a bit line electrically connected to the phase change structures.
8. The method of claim 1, further comprising:
forming phase change material structures contact to the switching diodes; and
forming a bit line electrically connected to the phase change structures, wherein forming the phase change material and the bit line are performed after forming the switching diodes,