Author: claimsbot

What is claimed is:

1. A method for encoding data read from a multistate memory array comprising cells, where each of the cells has N states, where N is an integer greater than two, and each of the states is indicative of a different stored data bit, said method including the steps of:
(a) generating data signals by reading selected ones of the cells, where each of the data signals has a value indicative of a data bit stored in a different one of the cells, each said value is in a range which is a member of a sequence of ranges LiHi, where i is an integer from 1 through N, each said range LiHi consisting of values xi, where Li<xi<Hi, and where L1<H1<L2<H2< . . . <LN<HN; and
(b) encoding the data signals by replacing each of the data signals with an encoded data signal, where for each of the data signals whose value is in the range LiHi, the encoded data signal is an ordered set of bits Ei, where Em is not identical to En where m and n are different integers in the range from 1 through N, and where for each pair of ordered sets Ej1 and Ej indicative respectively of a first ordered set of bits and a second ordered set of bits, the second ordered set is generated by changing X bits of the first ordered set, where j is an integer in the range from 2 through N, and X is a selected integer.
2. The method of claim 1, wherein X1, so that for each said pair of ordered sets Ej1 and Ej, the second ordered set is generated by changing one bit of the first ordered set.
3. The method of claim 1, wherein each ordered set of bits Ei is an ordered set of binary bits.
4. The method of claim 3, wherein X1, so that for each said pair of ordered sets Ej1 and Ej, the second ordered set is generated by changing one binary bit of the first ordered set.
5. The method of claim 3, wherein N4, and wherein ordered sets Ej, Ej1, Ej2, and Ej3 are indicative, respectively, of ordered binary bit sets 00, 01, 11, and 10.
6. The method of claim 5, where L1 is substantially equal to 0 volts, H1 is substantially equal to 1.2 volts, L2 is substantially equal to 1.25 volts, H2 is substantially equal to 2.45 volts, L3 is substantially equal to 2.5 volts, H3 is substantially equal to 3.7 volts, L4 is substantially equal to 3.75 volts, and H4 is substantially equal to 5.0 volts, and ordered sets E1, E2, E3, and E4 are indicative, respectively, of ordered binary bit sets 00, 01, 11, and 10.
7. The method of claim 3, wherein N8, and wherein ordered sets Ej, Ej1, Ej2, and Ej3, Ej4, Ej5, Ej6, and Ej7 are indicative, respectively, of ordered binary bit sets 000, 001, 011, 010, 110, 111, 101, and 100.
8. The method of claim 3, wherein N8, and wherein ordered sets Ej, Ej1, Ej2, and Ej3, Ej4, Ej5, Ej6, and Ej7 are indicative, respectively, of ordered binary bit sets 000, 100, 101, 001, 011, 111, 110, and 010, respectively.
9. The method of claim 1, also including the steps of:
(c) performing error detection on the encoded data signals generated in step (b), thereby detecting an error in at least one of said encoded data signals; and
(d) correcting the error by changing one bit of the ordered set of bits indicated by said at least one of said encoded data signals.
10. A multistate memory system, including:
a memory array comprising cells, where each of the cells has N states, where N is an integer greater than two, and each of the states is indicative of a different stored data bit;
a first circuit connected to the memory array and configured to read selected ones of the cells thereby generating data signals, where each of the data signals has a value indicative of a data bit stored in a different one of said selected ones of the cells, each said value is in a range which is a member of a sequence of ranges LiHi, where i is an integer from 1 through N, each said range LiHi consisting of values xi, where Li<xi<Hi, and where L1<H1<L2<H2< . . . <LN<HN; and
an encoding unit connected to the first circuit and configured to encode the data signals by replacing each of said data signals with an encoded data signal, where for each of the data signals whose value is in the range LiHi, the encoded data signal is an ordered set of bits Ei, where Em is not identical to En where m and n are different integers in the range from 1 through N, and where for each pair of ordered sets Ej1 and Ej indicative respectively of a first ordered set of bits and a second ordered set of bits, the second ordered set is generated by changing X bits of the first ordered set, where j is an integer in the range from 2 through N, and where X is an integer.
11. The system of claim 10, wherein X1, so that for each said pair of ordered sets Ej1 and Ej, the second ordered set is generated by changing one bit of the first ordered set.
12. The system of claim 10, wherein each ordered set of bits Ei is an ordered set of binary bits.
13. The system of claim 12, wherein X1, so that for each said pair of ordered sets Ej1 and Ej, the second ordered set is generated by changing one bit of the first ordered set.
14. The system of claim 13, wherein N4, and wherein ordered sets Ej, Ej1, Ej2, and Ej3 are indicative, respectively, of ordered binary bit sets 00, 01, 11, and 10.
15. The system of claim 13, where L1 is substantially equal to 0 volts, H1 is substantially equal to 1.2 volts, L2 is substantially equal to 1.25 volts, H2 is substantially equal to 2.45 volts, L3 is substantially equal to 2.5 volts, H3 is substantially equal to 3.7 volts, L4 is substantially equal to 3.75 volts, and H4 is substantially equal to 5.0 volts, and ordered sets E1, E2, E3, and E4 are indicative, respectively, of ordered binary bit sets 00, 01, 11, and 10.
16. The system of claim 13, wherein N8, and wherein ordered sets Ej, Ej1, Ej2, and Ej3, Ej4, Ej5, Ej6, and Ej7 are indicative, respectively, of ordered binary bit sets 000, 001, 011, 010, 110, 111, 101, and 100.
17. The system of claim 13, wherein N8, and wherein ordered sets Ej, Ej1, Ej2, and Ej3, Ej4, Ej5, Ej6, and Ej7 are indicative, respectively, of ordered binary bit sets 000, 100, 101, 001, 011, 111, 110, and 010, respectively.
18. The system of claim 10, also including:
error detection and correction circuitry connected to the encoding unit and configured to perform error detection on the encoded data signals, thereby detecting an error in at least one of said encoded data signals and correcting the error by changing one bit of the ordered set of bits indicated by said at least one of said encoded data signals.
19. The memory system of claim 10, wherein said memory system is an integrated memory circuit, and each of said cells is a flash memory cell.
20. A multistate memory system, including:
a memory array comprising cells, where each of the cells has four states, each of the states is indicative of a different stored data bit, a first of the states is determined by a first voltage range L1H1 between voltages L1 and H1, a second of the states is determined by a second voltage range L2H2 between voltages L2 and H2, a third of the states is determined by a third voltage range L3H3 between voltages L3 and H3, and a fourth of the states is determined by a fourth voltage range L4H4 between voltages L4 and H4, where L1<H1<L2<H2<L3<H3<L4<H4;
a first circuit connected to the memory array and configured to read selected ones of the cells thereby generating data signals, each of the data signals having a voltage in one of said voltage ranges L1H1, L2H2, L3H3, and L4H4; and
an encoding unit connected to the first circuit and configured to encode the data signals by replacing each of said data signals with an encoded data signal, where for each of the data signals whose value is in the range LiHi, the encoded data signal is an ordered set of bits Ei, where i is an integer from 1 through 4, and where for each pair of ordered sets Ej1 and Ej indicative respectively of a first ordered set of bits and a second ordered set of bits, the second ordered set is generated by changing X bits of the first ordered set, where j is an integer in the range from 2 through 4, and X is an integer.
21. The system of claim 20, wherein X1, so that for each said pair of ordered sets Ej1 and Ej, the second ordered set is generated by changing one bit of the first ordered set.
22. The system of claim 20, wherein each ordered set of bits Ei is an ordered set of binary bits.
23. The system of claim 22, wherein X1, so that for each said pair of ordered sets Ej1 and Ej, the second ordered set is generated by changing one bit of the first ordered set.
24. The system of claim 23, wherein ordered sets Ej, Ej1, Ej2, and Ej3 are indicative, respectively, of ordered binary bit sets 00, 01, 11, and 10.
25. The system of claim 20, where L1 is substantially equal to 0 volts, H1 is substantially equal to 1.2 volts, L2 is substantially equal to 1.25 volts, H2 is substantially equal to 2.45 volts, L3 is substantially equal to 2.5 volts, H3 is substantially equal to 3.7 volts, L4 is substantially equal to 3.75 volts, and H4 is substantially equal to 5.0 volts.
26. The system of claim 20, also including:
error detection and correction circuitry connected to the encoding unit and configured to perform error detection on the encoded data signals, thereby detecting an error in at least one of said encoded data signals, and to correct the error by changing one bit of the ordered set of bits indicated by said at least one of said encoded data signals.
27. The memory system of claim 20, wherein each of said cells is a flash memory cell.
28. The memory system of claim 27, wherein said memory system is an integrated memory circuit.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A liquid crystal display comprising:
a couple of substrates disposed facing each other; and
a liquid crystal layer disposed between the pair of substrates, the liquid crystal layer containing liquid crystal molecules having a negative dielectric anisotropy, each pixel in the liquid crystal layer having more than two regions, the liquid crystal molecules in one of the regions having a pre-tilt angle different from that of the liquid crystal in another region.
2. The liquid crystal display according to claim 1, wherein the pre-tilt angle of the liquid crystal molecules is 0\xb0 in one of the regions of the liquid crystal layers.
3. A method of manufacturing a liquid crystal display comprising steps of:
sealing, between a couple of substrates disposed facing each other, a liquid crystal layer composed of a vertical alignment liquid crystal containing monomers;
polymerizing the monomers in a first region within a pixel, with a first voltage applied between the couple of substrates holding the liquid crystal layer in between; and
polymerizing the monomers in a second region within a pixel, with a second voltage different from the first voltage applied between the couple of substrates holding the liquid crystal layer in between.
4. The method of manufacturing a liquid crystal display according to claim 3, wherein one of the first voltage and the second voltage is 0V.

1. An optical scanner for scanning an image carrier comprising:
an illuminant part emitting an optical beam;
a deflecting part deflecting the optical beam;
an image forming part focusing the deflected optical beam on the image carrier; and
an optical axis adjustment part adjusting an optical axis of the optical beam with respect to a sub-scanning direction during an image writing operation of image data,
the optical axis adjustment part comprising a prism for adjustment of a scanning position or a beam spot position of the optical beam on the image carrier with respect to a sub-scanning direction during the writing of image data by rotating the prism on an optical axis of the optical beam to deflect the incoming optical beam within a maximum deflection angle \u03a6, the maximum deflection angle \u03a6 being defined in a formula \u03a6=(n\u22121)\xd7\u03b1 in which n is a refractive index of the prism and \u03b1 is an apex angle of the prism, and the apex angle \u03b1 of the prism satisfies:
0.1<\u03b2\xd7tan(n\u22121)\xd7\u03b1<1.0
in which \u03b2 is a lateral magnification of all optical systems with respect to the sub-scanning direction, to compensate for misalignment of the scanning position or beam spot position due to fluctuation in rotation of the image carrier.
2. The optical scanner as claimed in claim 1, wherein the optical axis adjustment part further adjusts a writing start position on the image carrier.
3. The optical scanner as claimed in claim 2, further comprising:
a beam position detection part detecting a beam position of the optical beam.
4. The optical scanner as claimed in claim 3, further comprising:
a housing integrally accommodating the illuminant part, the deflecting part, the image forming part, the optical axis adjustment part, and the beam position detection part.
5. The optical scanner as claimed in claim 4, wherein the beam position detected by the beam position detection part is allowed to conduct free expansion relative to a location of the beam position detection part within the housing.
6. The optical scanner as claimed in claim 1, further comprising a rotation adjusting mechanism configured to adjust a rotational angle of the prism based on a detected amount of the misalignment of the scanning position beam spot position.
7. An image forming apparatus, comprising:
a plurality of image carriers; and
an optical scanner scanning the plurality of image carriers, the optical scanner comprising: an illuminant part emitting one or more optical beams; a deflecting part deflecting the optical beams; an image forming part focusing the deflected optical beams on the plurality of image carriers; and an optical axis adjustment part comprising a prism for adjustment of scanning positions or beam spot positions of the optical beams on the plurality of image carriers with respect to a sub-scanning direction during an image writing operation by rotating the prism on optical axes of the optical beams to deflect the incoming optical beam within a maximum deflection angle \u03a6, the maximum deflection angle \u03a6 being defined in a formula \u03a6=(n\u22121)\xd7\u03b1 in which n is a refractive index of the prism and \u03b1 is an apex angle of the prism, and the apex angle \u03b1 of the prism satisfies:
0.1<\u03b2\xd7tan(n\u22121)\xd7\u03b1<1.0
in which \u03b2 is a lateral magnification of all optical systems with respect to the sub-scanning direction, to compensate for misalignment of the scanning positions or beam spot positions due to fluctuation in rotation of the image carriers.
8. The image forming apparatus as claimed in claim 7, wherein the optical axis adjustment part further adjusts writing start positions on the plurality of image carriers.
9. The image forming apparatus as claimed in claim 8, further comprising:
a resist difference detection part detecting a resist difference between writing start positions on the plurality of image carriers.
10. The image forming apparatus as claimed in claim 9, wherein the optical axis adjustment part adjusts the writing start positions on the plurality of image carriers based on the resist difference detected by the resist difference detection part.
11. The image forming apparatus as claimed in claim 9, wherein a distance between an image transferred position onto a transferred member of the image forming apparatus and a resist position detected by the resist difference detection part is set to be an approximately integer multiple of a circumferential length of a driving roller for driving the transferred member.
12. The image forming apparatus as claimed in claim 8, further comprising:
a beam spot position detection part detecting beam spot positions on the plurality of image carriers.
13. The image forming apparatus as claimed in claim 12, wherein the optical axis adjustment part adjusts scanning positions on the plurality of image carriers based on misplacement of the beam spot positions detected by the beam spot position detection part.
14. The image forming apparatus as claimed in claim 7, further comprising a rotation adjusting mechanism configured to adjust a rotational angle of the prism based on a detected amount of the misalignment of the scanning position beam spot position.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A system, comprising:
a server including an information application, said information application being in communication with an information database, said information database comprising a plurality of marketplaces, each marketplace being associated with a classification, and a plurality of listings respectively classified within said plurality of marketplaces;
wherein said plurality of marketplaces comprise pre-defined marketplaces and user-defined marketplaces distinct from said pre-defined marketplaces, at least one of said user-defined marketplaces being classified in a classification within at least one of said pre-defined marketplaces; and
wherein at least one of said user-defined marketplaces is associated with a categorical classification defining at least one listing topic, and at least a subset of said at least one listing topic defined by said categorical classification is inherited and created within said marketplace.
2. The system of claim 1, wherein said information application is selectively accessible by users and said user-defined marketplaces are selectively created by a subset of the users.
3. The system of claim 1, wherein said information database forms at least a portion of a computing device and said information application is a software application executed by said computing device.
4. The system of claim 1, wherein each of said plurality of listings comprises listing attribute data, said listing attribute data comprising at least one of a classification attribute, a geographic attribute, a contact information attribute, a fee-type attribute, and a position adjustment attribute.
5. The system of claim 1, wherein a fee-type attribute is assigned to each of said user-defined marketplaces.
6. The system of claim 1, wherein said plurality of listings and said user-defined marketplaces are created based at least in part on data supplied by an access device in communication with said information application.
7. The system of claim 6, wherein approval from administrators of said system is required prior to creation of at least a subset of said user-defined marketplaces.
8. The system of claim 6, wherein said information application is configured to generate and transmit a response to said access device based upon a request transmitted from said access device, said request comprising at least one search term and said response comprising at least one of said plurality of listings responsive to said request.
9. The system of claim 1, wherein at least one of said user-defined marketplaces is classified within at least one other user-defined marketplaces.
10. The system of claim 1, wherein at least one of said user-defined marketplaces is associated with a geographic classification stored in said information database.
11. The system of claim 10, wherein said geographic classification is user-defined.
12. The system of claim 1, wherein at least one of said user-defined marketplaces is linked with at least one other user-defined marketplace.
13. The system of claim 12, wherein one of said user-defined marketplaces linked to another marketplace inherits listing topics defined within the marketplace to which it is linked.
14. The system of claim 1, wherein access to said user-defined marketplace is restricted based on a set of user-defined access rights.
15. The system of claim 14, wherein said user-defined access rights limit access to said user-defined marketplace to registered users of said user-defined marketplace and registered users of marketplaces that are linked to said user-defined marketplace.
16. The system of claim 1, wherein a user-defined marketplace includes user-defined listing topics.