Author: claimsbot

1. A circuit for performing a write operation in a phase change memory device having a phase change memory cell, comprising:
a programmable fuse unit for adjusting the magnitude of write current through the phase change memory cell.
2. The circuit according to claim 1, wherein the programmable fuse unit comprises laser-programmable fuses.
3. The circuit according to claim 1, wherein the programmable fuse unit comprises electrically-programmable fuses.
4. The circuit according to claim 1, wherein the magnitude of a first write current applied to establish a relatively higher resistance state of the phase change memory cell, is higher than the magnitude of a second write current applied to establish a relatively lower resistance state of the phase change memory cell.
5. A write driver circuit for a phase change memory device having a plurality of phase change memory cells each having first and second resistance states, the circuit comprising:
a write current control unit for outputting a first level of voltage by establishing a first programmable current path while a first selection pulse signal is applied, and outputting a second level of voltage by establishing a second programmable current path while a second selection pulse signal is applied.
6. The circuit of claim 5, wherein at least one of the first programmable current path and the second programmable current path comprises a programmable fuse.
7. The circuit of claim 5, wherein at least one of the first programmable current path and the second programmable current path includes a transistor having a source-to-drain resistance that is controlled by the conducting state of at least one programmable fuse.
8. The circuit of claim 7, wherein the at least one programmable fuse is a laser-programmable fuse.
9. The circuit of claim 5, further comprising:
a pulse selection unit for selecting one of first and second state pulses that are applied to change a resistance state of the phase change memory cell, in response to a logic state of the applied write data, and outputting the selected pulse as a first or second selected pulse signal; and
a current driving unit for generating a write current in response to the output voltage from the write current control unit.
10. The circuit of claim 9, wherein the -pulse selection unit comprises first and second transmission gates for respectively passing one of the first and second state pulses selected based upon received write data.
11. The circuit of claim 5, wherein the write current control unit comprises:
a reset current control unit for establishing the first programmable current path that includes at least one programmable fuse in response to the first selection pulse signal and;
a set current control unit for establishing the second programmable current path that includes at least one programmable fuse in response to the second selection pulse signal and allowing current flowing through the second current path to be decreased by the programmable fuse; and
an output voltage control unit that includes at least one programmable fuse, for outputting the first or second level of the voltage through a voltage output node.
12. The circuit of claim 11, further comprising a current driving unit for generating a write current in response to the output voltage from the write current control unit that includes a P-type switch having a gate terminal connected to the voltage output node of the output voltage control unit, a source terminal to receive a power supply voltage, and a drain terminal to output the write current.
13. A write driver circuit for performing a write operation in a phase change memory device having a plurality of phase change memory cells having first and second resistance states, the circuit comprising:
a write current control unit for outputting a first level of voltage by establishing a first programmable current path if a first selection pulse signal is applied, and outputting a second level of voltage by establishing a second programmable current path if a second selection-pulse signal is applied.
14. The circuit of claim 13, wherein at least one of the first programmable current path and the second programmable current path includes a programmable fuse adapted to change the resistance of one of the first programmable current path and the second programmable current path.
15. The circuit of claim 14, wherein at least one programmable fuse is adapted to change the resistance of one of the first programmable current path and the second programmable current path to compensate for a current output shift or for a phase change property shift of the phase change memory cell.
16. The circuit of claim 13, further comprising: a pulse selection unit for selecting one of first and second state pulses that are applied to change a resistance state of the phase change memory cell, in response to a logic state of the applied write data, and outputting the selected pulse as a first or second selected pulse signal; and
a current driving unit for generating a write current in response to the output voltage of the write current control unit.
17. The circuit of claim 16, wherein the pulse selection unit comprises first and second transmission gates that selectively pass the first and second state pulses based upon write data received at their respective control terminals.
18. The circuit of claim 16, wherein the write current control unit comprises:
a reset current control unit for establishing the first programmable current path in response to the first selection pulse signal;
a set current control unit for establishing the second programmable current path in response to the second selection pulse signal; and
an output voltage control unit having a voltage output node connected to the first and second current paths that outputs the first and second levels of voltage depending on the quantity of current flowing through the selected one first and second current paths.
19. The circuit of claim 18, wherein the first programmable current path includes at least one programmable fuse adapted to enable a change of the resistance of the first programmable current path; and
the second programmable current path includes at least one programmable fuse adapted to enable a change of the resistance of the second programmable current path.
20. The circuit of claim 19, wherein the current driving unit is composed of a P-type switch having a gate terminal connected to the voltage output node of the output voltage control unit, a source terminal connected to a power supply voltage, and a drain terminal to output the write current.
21. A write driver circuit for a phase change memory device having an array of phase change memory cells having first and second resistance states, the circuit comprising:
a pulse selection unit for selecting one of first and second state pulses that are applied to change the resistance state of a phase change memory cell based upon the logic state of applied write data, and for outputting the selected pulse as a first or second selected pulse signal;
a write current control unit for outputting a first level of voltage by establishing a first current path having a first programmable resistance, and outputting a second level of voltage by establishing a second current path having a second programmable resistance if the second selection pulse signal is applied; and
a current driving unit for generating a write current in response to the output voltage of the write current control unit.
22. The circuit of claim 21, wherein the pulse selection unit comprises first and second transmission gates that selectively pass the first and second state pulses based upon the applied write data received at their control terminals.
23. The circuit of claim 22, wherein the write current control unit comprises:
a reset current control unit for establishing the first current path in response to the first selection pulse signal, the resistance of the first current path being changeable using at least one programmable fuse;
a set current control unit for establishing the second current path in response to the second selection pulse signal and the resistance of the second current path being changeable using at least one programmable fuse; and
an output voltage control unit having a voltage output node connected to the first and second current paths, and outputting a selected one of the first and second level of voltages through the voltage output node, the actual voltage of selected one of the first and second level of voltages depending on the quantity of current flowing through the first or second current paths.
24. The circuit of claim 23, wherein the current driving unit is composed of a P-type transistor having a gate terminal connected to the voltage output node of the output voltage control unit.
25. The circuit of claim 24, wherein the resistance of the first current path changes in response to an output voltage of a first DC output circuit that includes at least one programmable fuse for controlling the voltage of the output voltage.
26. The circuit of claim 25, wherein the resistance of the second current path changes in response to an output voltage of a second DC output circuit that includes at least one programmable fuse for controlling the voltage of the output voltage.
27. A method for applying write currents to a phase change memory cell in a phase change memory device, the method comprising the step of:
adjusting the magnitude of a first write current determined by a first logic state of write data by programming a first fuse.
28. The method of claim 27, wherein the first fuse is a laser-programmable fuse.
29. The method of claim 27, wherein the first write current is a set current for crystallizing a phase change material in the phase change memory cell.
30. The method of claim 29, further comprising the step of adjusting the magnitude of a second write current determined by a second logic state of write data by programming a second fuse.
31. The method of claim 30, wherein the second fuse is a laser-programmable fuse.
32. The method of claim 31, wherein the second write current is a reset current for amorphizing the phase change material in the phase change memory cell.
33. The method of claim 30, wherein the first logic state is a logic \u201c0\u201d and the second logic state is a logic \u201c1\u201d.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A fiber optic current sensor having a coiled sensor fiber (1) which encloses a current conductor (S), and at least one phase delay element (4, 5) adjoining the sensor fiber (1), characterized in that the at least one phase delay element (4, 5) has a phase delay with a temperature dependence which at least approximately compensates for a temperature dependence of a Verdet’s constant (V) of the sensor fiber (1).
2. The current sensor as claimed in claim 1, characterized in that the at least one phase delay element (4, 5) has a phase delay angle whose value deviates from a phase delay angle of an ideal phase delay element.
3. The current sensor as claimed in one of claims 1 or 2, characterized in that the at least one phase delay element (4, 5) is a 4 fiber segment with an elliptical core, and in that the 4 fiber segment has a length (L) which deviates from a quarter or an odd multiple of a quarter of a beat length of orthogonal polarization modes.
4. The current sensor as claimed in claim 2, characterized in that the magnitude of the phase delay angle is selected as a function of a mutual alignment of fast axes of the phase delay element (4, 5).
5. The current sensor as claimed in claim 2, characterized in that the magnitude of the phase delay angle is selected as a function of a sign of the temperature dependence of the at least one phase delay element (4, 5).
6. The current sensor as claimed in claims 2, 4 and 5, characterized in that there are at least two phase delay elements (4, 5), each having a fast axis, the fast axes being orientated at least approximately parallel to one another, and in that in the case of a temperature dependence of the phase delay elements (4, 5) of positive sign the phase delay angle is greater, and in the case of a temperature dependence of negative sign it is smaller than a phase delay angle of an ideal phase delay element.
7. The current sensor as claimed in claims 2, 4 and 5, characterized in that there are at least two phase delay elements (4, 5) each having a fast axis, the fast axes being orientated at least approximately orthogonally to one another, and in that in the case of a temperature dependence of the phase delay elements (4, 5) of positive sign the phase delay angle is smaller, and in the case of a temperature dependence of negative sign it is larger than a phase delay angle of an ideal phase delay element.
8. The current sensor as claimed in claim 1, characterized in that it has a Sagnac interferometer.
9. The current sensor as claimed in claim 1, characterized in that it has a reflection interferometer.

1. A printed circuit board, comprising:
an electrically conductive bonding pad disposed on an outer surface of the printed circuit board, the bonding pad having a bonding pad perimeter at immediately bounding edges of the bonding pad, and
an electrically conductive via directly electrically contacting the bonding pad and disposed within the printed circuit board relative to the bonding pad, the via having a via perimeter at immediately bounding edges of the via,
where the via perimeter overlaps the pad perimeter such that a portion of the via perimeter is within the pad perimeter and a portion of the via perimeter is outside the pad perimeter.
2. The printed circuit board of claim 1, wherein the bonding pad is a ball bonding pad.
3. The printed circuit board of claim 1, wherein the bonding pad is a passive component bonding pad, where the passive components include at least one of a resistor, a capacitor, and an inductor.
4. The printed circuit board of claim 1, wherein the bonding pad is a wire bonding pad.
5. A package substrate, comprising:
an electrically conductive bonding pad disposed on an outer surface of the package substrate, the bonding pad having a pad perimeter at immediately bounding edges of the bonding pad, and
an electrically conductive via directly electrically contacting the bonding pad and disposed within the package substrate relative to the bonding pad, the via having a via perimeter at immediately bounding edges of the via,
where the via perimeter overlaps the pad perimeter such that a portion of the via perimeter is within the pad perimeter and a portion of the via perimeter is outside the pad perimeter.
6. The package substrate of claim 5, wherein the bonding pad is a ball bonding pad.
7. The package substrate of claim 5, wherein the bonding pad is a bump bonding pad.
8. The package substrate of claim 5, wherein the bonding pad is a wire bonding pad.
9. The package substrate of claim 5, wherein the bonding pad is a passive component bonding pad, where the passive components include at least one of a resistor, a capacitor, and an inductor.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A pulverulent coated flame retardant comprising a phosphorus-containing andor nitrogen-containing flame retardant wherein the silazanes andor silazane-organosiloxane mixtures are used as coating material.
2. The pulverulent coated flame retardant as claimed in claim 1, wherein the phosphorus-containing andor nitrogen-containing flame retardant is ammonium orthophosphate, ammonium diphosphate, ammonium polyphosphate, melamine phosphate, melamine orthophosphate, melamine diphosphate, melamine polyphosphate, melamine pyrophosphate, melamine borate, melamine cyanurate, melamine borophosphate, melamine 1,X-phthalate, andor melamine oxalate; melem, melam, melon, melam polyphosphate, melem polyphosphate andor melon polyphosphate.
3. The pulverulent coated flame retardant as claimed in claim 1, wherein the phosphorus-containing andor nitrogen-containing flame retardant is ammonium diphosphate andor ammonium polyphosphate.
4. The pulverulent coated flame retardant as claimed in one claim 1, wherein the silazanes used comprise dimeric andor polymeric silazanes of the formula (1)
\u2014(SiR\u2032R\u2033\u2014NR\u2032\u2033)n\u2014\u2003\u2003(1)
where R\u2032, R\u2033, and R\u2032\u2033 are identical or different and are mutually independently hydrogen or an optionally substituted alkyl, aryl, vinyl, or (trialkoxysilyl)alkyl moiety, where n is an integer and n is such that the number-average molar mass of the silazane is from 70 to 150 000 gmol.
5. The pulverulent coated flame retardant as claimed in one or more of claim 1, wherein the silazanes used comprise those of the formula (2),
\u2014(SiR\u2032R\u2033\u2014NR\u2032\u2033)n\u2014(SiR*R**\u2014NR***)p\u2014\u2003\u2003(2)

wherein R\u2032, R\u2033, R\u2032\u2033, R*, R**, and R*** are mutually independently and are hydrogen or an optionally substituted alkyl, aryl, vinyl, or (trialkoxysilyl)alkyl moiety, and n and p are such that the number-average molar mass of the silazane is from 150 to 150 000 gmol.
6. The pulverulent coated flame retardant as claimed in claim 6, wherein R\u2032, R\u2033, R\u2032\u2033, R*, R**, and R*** in the silazane of the formula (1) andor formula (2) are mutually independently a moiety from the group of hydrogen, methyl, ethyl, propyl, isopropyl, butyl, isobutyl, tert-butyl, phenyl, vinyl, or 3-(triethoxysilyl)propyl, 3-(trimethoxysilyl)propyl.
7. The pulverulent coated flame retardant as claimed in claim 5, wherein, in the silazane of the formula (2),
R\u2032, R\u2032\u2033, and R*** are hydrogen and R\u2033, R*, and R** are methyl andor vinyl, or
R\u2032 and R\u2032\u2033 are hydrogen, R\u2033, R*, and R** are methyl and R*** is (trialkoxysilyl)propyl, or
R\u2032, R\u2032\u2033, R*, and R*** are hydrogen, and R\u2033 and R** are methyl.
8. The pulverulent coated flame retardant as claimed in claim 1, wherein the organosiloxane of the silazane-organosiloxane mixtures is alkoxysiloxane andor oligomeric alkoxysiloxane comprising linear, branched, functionalized, andor cyclic alkyl, alkoxy, aminoalkyl, aryl andor vinyl groups.
9. The pulverulent coated flame retardant as claimed in claim 1, wherein the organosiloxane is 3-aminopropyltrialkoxysilane, 3-aminopropylmethyldialkoxysilane, 3-glycidyloxypropyltrialkoxysilane, 3-acryloxypropyltrialkoxysilane, 3-methacryloxypropyltrialkoxysilane, vinyltrialkoxysilane, vinyl-tris(2-methoxyethoxy)silane, propyltrialkoxysilane, butyltrialkoxysilane, pentyltrialkoxysilane, hexyltrialkoxysilane, heptyltrialkoxysilane, octyltrialkoxysilane, propylmethyldialkoxysilane, butylmethyldialkoxysilane, andor phenyltrialkoxysilane, phenylmethyldialkoxysilane, andor is an oligomeric vinyl-functional, aryl-functional, andor alkyl-functional alkoxysiloxane.
10. The pulverulent coated flame retardant as claimed claim 1, wherein from 1 to 50 parts by weight of the silazane or of a mixture of silazane and organosiloxane are applied to 100 parts by weight of flame retardant.
11. A process for the production of a pulverulent coated flame retardant as claimed in claim 1, comprising the step of applying the silazanes andor silazane-organosiloxane mixtures directly or in the form of a solution to the pulverulent flame retardant.
12. The process as claimed in claim 11, wherein the silazanes andor silazane-organosiloxane mixtures are applied by spraying or injection, or in droplet form, or by pouring onto the pulverulent flame retardants kept in motion via mixers, kneaders, stirrers, or gas.
13. The process as claimed in claim 11, wherein the temperature of the pulverulent flame retardant has been controlled in advance to from 10 to 200\xb0 C.
14. The process as claimed in claim 13, wherein hardening is then carried out for from 5 min to 24 h at temperatures of from 10 to 200\xb0 C.
15. A process for the production of a pulverulent coated flame retardant as claimed in claim 1, comprising the steps of suspending the flame retardant in a solvent and heating with the silazanes andor silazane-organosiloxane mixtures to from 10 to 200\xb0 C. for from 5 min to 24 h, with stirring.
16. The process as claimed in claim 15, wherein hardening is then carried out for from 5 min to 24 h at temperatures of from 10 to 200\xb0 C.
17. The process as claimed in claim 11, wherein the ratio by weight of silazane to organosiloxane is from 100:0 to 1:99.
18. The process as claimed in claim 11, wherein the ratio by weight of silazane to organosiloxane is from 75:25 to 1:99.
19. An intumescent coating, polyolefin and other polymers comprising the pulverulent coated flame retardant as claimed in claim 1.