Author: claimsbot

1. A storage device, comprising:
a controller and a second non-volatile memory, said controller including a first non-volatile memory, wherein
said controller further includes a first interface for connecting said controller to a host terminal device, a second interface for connecting said controller to said second non-volatile memory, a central processing device, and a volatile memory utilized by said central processing device,
said first non-volatile memory includes a first storage area for storing Km data used for encrypting or decrypting a program to be executed by said central processing device and a second storage area for storing data from said host terminal device,
said second non-volatile memory includes an access-permitted area for storing data from said host terminal device and an access-prohibited area for storing said program encrypted using said Km data, an access by a user being permitted to said access-permitted area but being limited to said access-prohibited area, and
said controller:
stores the data from said host terminal device in said access-permitted area of said second non-volatile memory without encryption, if a security level of the data from said host terminal device is lower than a predetermined level;
checks a free available capacity of said first non-volatile memory, if the security level of the data from said host terminal device is higher than the predetermined level;
stores the data from said host terminal device in said second storage area of said first non-volatile memory, if the free available capacity of said first non-volatile memory is sufficient; and
stores the data from said host terminal device in said access-permitted area of said second non-volatile memory after encrypting the data from said host terminal device by using said Km data, if the free available capacity of said first non-volatile memory is insufficient.
2. The storage device as claimed in claim 1, wherein said Km data includes key information and a program used for said encryption or said decryption processing.
3. The storage device as claimed in claim 1, wherein, in correspondence with a command or an attribute of data from said host terminal device, said controller determines whether to access said first non-volatile memory or to access said second non-volatile memory.
4. The storage device as claimed in claim 1, wherein, in correspondence with a command or an attribute of data from said host terminal device, said controller determines whether or not to encrypt general data, said general data having been received from said host terminal device so as to be written into said second non-volatile memory.
5. The storage device as claimed in claim 1, wherein said first non-volatile memory further includes at least one of a storage area for storing Ko data and a storage area for storing Ki data, said Ko data being used for cipher communication between a server and said host terminal device , said Ki data being used for cipher communication between said server and said storage device , said server being connected to said host terminal device via a network.
6. The storage device as claimed in claim 5, wherein said controller, using said Km data, encrypts at least one program of a program included in said Ko data and a program included in said Ki data, and then writes said encrypted one program into said access-prohibited area.
7. The storage device as claimed in claim 1, wherein said controller is an IC chip, said second non-volatile memory being a flash memory chip.
8. The storage devices a claimed in claim 1, wherein
said first non-volatile memory includes a storage area for storing Kl data which said central processing device uses for encryption or decryption according to said program stored in said second non-volatile memory.
9. The storage device as claimed in claim 1, wherein
tamper-resistibility of said controller is higher than that of said second non-volatile memory.
10. The storage device as claimed in claim 1, wherein said controller:
checks an attribute of the data from said host terminal device;
checks a free available capacity of said first non-volatile memory, if the data from said host terminal device is smaller than a predetermined capacity based on the attribute checked;
stores the data from said host terminal device in said second storage area of said first non-volatile memory, if the free available capacity of said first non-volatile memory is sufficient;
stores the data from said host terminal device in said access-permitted area of said second non-volatile memory after encrypting the data from said host terminal device by using said Km data, if the free available capacity of said first non-volatile memory is insufficient; and
stores the data from said host terminal device in said access-permitted area of said second non-volatile memory after encrypting the data from said host terminal device by using said Km data, if the data from said host terminal device is larger than said predetermined capacity based on the attribute checked.
11. The storage device as claimed in claim 10, wherein if the data from said host terminal device has no attribute, said controller checks the security level of the data from said terminal device.
12. The storage device as claimed in claim 10, wherein, if the security level of the data from said host terminal device is an intermediate level, said controller stores the data from said host terminal device in said access-permitted area of said second non-volatile memory after encrypting the data from said host terminal device by using said Km data without checking the free available capacity of said first non-volatile memory.
13. A host terminal device, comprising:
a connectabledisconnectable storage device including a controller and a second non-volatile memory, said controller including a first non-volatile memory,
a first interface for connecting said host terminal device to said storage device, and
a first central processing device, wherein
said controller further includes a second interface for connecting said controller to said first interface, a third interface for connecting said controller to said second non-volatile memory, and a second central processing device,
said first non-volatile memory includes a first storage area for storing Km data used for encrypting or decrypting a program to be executed by said second central processing device and a second storage area for storing data from said host terminal device,
said second non-volatile memory includes an access-permitted area for storing data from said host terminal device and an access-prohibited area for storing said program encrypted using said Km data, an access by a user being permitted to said access-permitted area but being limited to said access-prohibited area, and
said controller:
stores the data from said host terminal device in said access-permitted area of said second non-volatile memory without encryption, if a security level of the data from said host terminal device is lower than a predetermined level;
checks a free available capacity of said first non-volatile memory, if the security level of the data from said host terminal device is higher than the predetermined level;
stores the data from said host terminal device in said second storage area of said first non-volatile memory, if the free available capacity of said first non-volatile memory is sufficient; and
stores the data from said host terminal device in said access-permitted area of said second non-volatile memory after encrypting the data from said host terminal device by using said Km data, if the free available capacity of said first non-volatile memory is insufficient.
14. The host terminal device as claimed in claim 13, wherein
said first non-volatile memory further stores Ko key information used for cipher communication a server and said host terminal device, said server being connected to said host terminal device via a network,
said first central processing device reads out said Ko key information from said first non-volatile memory, encrypting said Ko key information by using an encryption key that is capable of being decrypted by said server, and transmitting said encrypted Ko key information to said server,
said host terminal device then receives, from said server, data encrypted by using said Ko key information.
15. The host terminal device as claimed in claim 13, wherein
said first non-volatile memory further stores Ki key information used for cipher communication between a server and said storage device , said server being connected to said host terminal device via a network,
said second central processing device reads out said Ki key information from said first non-volatile memory, encrypting said Ki key information by using an encryption key that is capable of being decrypted by said server, and transmitting said encrypted Ki key information to said server via said host terminal device, and
said host terminal device then receives, from said server, data encrypted by using said Ki key information and transmitting the data thus received to said storage device.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A polishing pad, comprising:
a plurality of abrasive units each containing:
an adhesive compound; and
a plurality of abrasive particles distributed evenly within the adhesive compound,
wherein the surface of the abrasive units in contact with the surface of a wafer is roughened and the abrasive units are shaped into a triangular cone, hexagonal cone or circular cylinder and set up as an array.
2. The polishing pad of claim 1, wherein material constituting the abrasive particles comprises cerium oxide (CeO2).
3. The polishing pad of claim 1, wherein material constituting the adhesive compound comprises a resin.
4. A method of polishing a wafer, comprising the steps of:
providing a first polishing pad, wherein the first polishing pad comprises a plurality of first abrasive units each fabricated using an adhesive compound with evenly distributed abrasive particles therein;
performing a first polishing operation on the first polishing pad to planarize a wafer;
providing a second polishing pad, wherein the second polishing pad comprises a plurality of second abrasive units each fabricated using an adhesive compound with evenly distributed abrasive particles therein, and the surface of the second abrasive units in contact with the wafer is roughened and the abrasive units are shaped into a triangular cone, hexagonal cone or circular cylinder and set up as an array; and
performing a second polishing operation on the second polishing pad.
5. The wafer polishing method of claim 4, wherein material constituting the abrasive particles comprises cerium oxide (CeO2).
6. The wafer polishing method of claim 4, wherein material constituting the adhesive compound comprises a resin.
7-10. (cancelled)
11. The wafer polishing method of claim 4, wherein the second polishing operation is conducted at a rate faster than that of the first polishing operation.
12. The wafer polishing method of claim 4, wherein the second polishing operation is conducted at least at a same rate as the first polishing operation.

1. An optical disc apparatus, comprising:
a recording section for recording new data on an optical disc so as to be continuous to data which is previously recorded on the optical disc;
a detection section for detecting an amount of deviation between a position at which the previously recorded data is recorded and a position at which the previously recorded data should have been recorded; and
an adjustment section for adjusting a position at which the new data is to be recorded so that an amount of deviation between a position at which an end of the new data is to be recorded and a position at which the end of the new data should be recorded is smaller than the amount of deviation detected by the detection section.
2. An optical disc apparatus according to claim 1, wherein the adjustment section adjusts the position at which the new data is to be recorded so that the amount of deviation between the position at which the end of the new data is to be recorded and the position at which the end of the new data should be recorded is substantially zero.
3. An optical disc apparatus according to claim 1, wherein:
the recording section records the new data on the optical disc in synchronization with a recording clock; and
the adjustment section adjusts a frequency of the recording clock so as to adjust the position at which the new data is to be recorded.
4. An optical disc apparatus according to claim 1, further comprising reference frequency detection section for detecting a reference frequency of the recording clock, wherein the adjustment section control the frequency of the recording clock so that the frequency of the recording clock approaches the reference frequency.
5. An optical disc apparatus, comprising:
a pre-pit sync detection circuit for detecting a prescribed pre-pit pre-formed on an optical disc and outputting a pre-pit sync detection signal in response to detection of the prescribed pre-pit;
a data sync detection circuit for detecting a prescribed synchronization signal included in the previously recorded data and outputting a data sync detection signal in response to detection of the synchronization signal;
a recording clock generation circuit for generating a recording clock; and
a recording circuit system for recording the new data on the optical disc in synchronization with the recording clock based on the data sync detection signal,
wherein the recording clock generation circuit detects a time-wise amount of deviation between the pre-pit sync detection signal and the data sync detection signal and controls a frequency of the recording clock so as to correct the detected time-wise amount of deviation.
6. An optical disc apparatus according to claim 5, wherein the recording clock generation circuit includes:
a first timing signal generator for generating a first rectangular wave in synchronization with the recording clock based on the pre-pit sync detection signal;
a second timing signal generator for generating a second rectangular wave in synchronization with the recording clock based on the data sync detection signal; and
a control circuit for controlling the frequency of the recording clock so that a phase difference between the first timing signal and the second timing signal approaches zero.
7. An optical disc apparatus according to claim 6, wherein:
the first timing signal generator generates the first rectangular wave by dividing the frequency of the recording clock, and
the second timing signal generator generates the second rectangular wave by dividing the frequency of the recording clock.
8. An optical disc apparatus according to claim 5, wherein the recording clock generation circuit includes:
a first timer which is preset at a first prescribed value in response to the pre-pit sync detection signal;
a second timer which is preset at a second prescribed value in response to the data sync detection signal; and
a control circuit for controlling the truancy of the recording clock so that a difference between a value of the first timer and a value of the second timer approaches zero.
9. An optical disc apparatus according to claim 8, wherein the first timer and the second timer operate in synchronization with the recording clock.
10. An optical disc apparatus according to claim 5, wherein the optical disc has a track formed thereon having wobbles of a prescribed cycle, the optical disc apparatus further comprising a wobble detection circuit for detecting the wobbles and outputting a wobble signal representing a frequency of the wobbles, wherein the recording clock generation circuit controls the frequency of the recording clock in accordance with the wobble signal.
11. An optical disc apparatus according to claim 10, wherein the recording clock generation circuit controls the frequency of the recording clock in accordance with the wobble signal before recording of the new data is started; and controls the frequency of the recording clock in accordance with the wobble signal and the detected time-wise amount of deviation after the recording of the new data is started.
12. An optical disc apparatus according to claim 10, further comprising a reproduction clock generation circuit for generating a reproduction clock from the previously recorded data, wherein the recording clock generation circuit controls the frequency of the recording clock in accordance with the reproduction clock before recording of the new data is started; and controls the frequency of the recording clock in accordance with the wobble signal and the detected time-wise amount of deviation after the recording of the new data is started.
13. An optical disc apparatus according to claim 1, wherein:
the detection section comprises a first timing signal generator and a second timing signal generator;
the position at which the previously recorded data is recorded is detected based on a data sync detection signal; and
the position at which the previously recorded data should have been recorded is detected based on a pre-pit sync detection signal.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for canceling a read or write operation in a memory system having a plurality of dynamic random access memory (DRAM) devices comprising:
providing address and control information to the plurality of DRAM devices operation through a memory controller to enable a data stream to or from a processor;
masking data by the memory controller, thereby protecting the data stream during read operations if a command cancel signal is received;
generating a command cancel signal to disable the memory system if an incorrect data stream is presented to the DRAM, said command cancel signal being generated within a clocking cycle of the memory system; and
restoring the system in response to the command cancel signal.
2. The method of claim 1 which includes:
monitoring the integrity of read or write operations to a DRAM, and generating a command cancel signal in response to the detection of an incorrect operation.
3. A method for canceling a write or read operation in a memory system having a plurality of DRAM devices comprising:
timing the operations in clock cycles;
providing a write latency of one or more clock cycles between receipt of a write command and receipt of data; and
generating a command cancel signal to disable the write operation at the DRAM subsequent to the initial write command and prior to the write latency of the memory device, without damage to existing stored data.
4. The method of claim 3 wherein the command cancel signal terminates the write operation within the DRAM devices.
5. The method of claim 4 wherein the command cancel signal resets FIFO clocks.
6. The method of claim 3 wherein the command cancel signal is transmitted on a unique pin.
7. The method of claim 3 wherein the command cancel signal is triggered by ECC logic.
8. The method of claim 7 wherein the ECC logic operates in parallel or series mode.
9. The method of claim 8 wherein if an ECC error is detected in parallel mode a re-try operation is performed to determine if a soft error occurred allowing continuous ECC parallel operation.
10. The method of claim 9 wherein if an ECC error is detected which required correction, the ECC mode is changed to serial operation until a repair action is completed.
11. The method of claim 3 wherein the command cancel signal is triggered by a parity bit.