1. A shift register, comprising:
a first thin film transistor, whose gate is connected to a first node as a pull-up node, a source thereof is connected to a clock signal terminal, a drain thereof is connected to a output terminal of the present stage;
a second thin film transistor, whose gate is connected to a feedback signal terminal of the next stage, a source thereof is connected to said first node, a drain thereof is connected to a low level signal terminal;
a third thin film transistor, whose gate is connected to a feedback signal terminal of the next stage, a source thereof is connected to a second node as a pull-down node, a drain thereof is connected to the low level signal terminal, wherein the second node is connected with the output terminal of the present stage;
a capacitor, connected between said first node and the output terminal of the present stage;
a feedback module, connected between the trigger signal terminal of the previous stage, the clock signal terminal and said first node, and connected to the feedback signal terminal of the present stage and the trigger signal terminal of the present stage; and
a switch module, connected with the clock signal terminal, said feedback module and the output terminal of the present stage, and connected to the low level signal terminal;
wherein said feedback module is used to receive a trigger signal of the feedback module of the previous stage and the clock signal, in order to pull up the level of the first node, and to output feedback signal to the shift register of the previous stage and output the trigger signal to the feedback module of the next stage, said switch module is used to maintain the output terminal of the shift register of the present stage at a low level when the shift register of the present stage does not operate.
2. The shift register as claimed in claim 1, wherein said feedback module comprises:
a fourth thin film transistor, whose gate is connected to a first trigger signal terminal of the feedback module of the previous stage, a source thereof is connected to a gate of the fifth thin film transistor, a drain thereof is connected to a clock signal terminal;
a fifth thin film transistor, whose gate is connected to the source of the fourth thin film transistor, a source thereof is connected to the first node, a drain thereof is connected to the second trigger signal terminal of the feedback module of the previous stage; and
a sixth thin film transistor, whose gate is connected to the first node, a source thereof is connected to the clock signal terminal, a drain thereof is connected to a third node as a feedback node of the present stage.
3. The shift register as claimed in claim 2, wherein said switch module further comprises:
class-1 switch module, which is used to control a first switch module, a second switch module and a third switch module, said class-1 switch module comprising: a seventh thin film transistor, whose gate and drain are connected together to the clock signal terminal, a source thereof is connected to the second switch module and the third switch module; a eighth thin film transistor, whose gate is connected to the clock signal terminal, a source thereof is connected to a fourth node as a interlocking node, a drain thereof is connected to the low level signal terminal; a ninth thin film transistor, whose gate and source are connected together to the clock signal terminal, a drain thereof is connected to the fourth node;
the first switch module, used to maintain the output terminal of the present stage at a low level when the shift register of the present stage does not operate, which comprising: a tenth thin film transistor, whose gate is connected to the clock signal terminal, a source thereof is connected to the second node, a drain thereof is connected to the low level signal terminal; a eleventh thin film transistor, whose gate is connected to the fourth node, a source thereof is connected to the second node, a drain thereof is connected to the low level signal terminal;
the second switch module, used to maintain said first node at a low level when the shift register of the present stage does not operate, which comprising: a twelfth thin film transistor, whose gate is connected to the source of the seventh thin film transistor, a source thereof is connected to the first node, a drain thereof is connected to the feedback module of the previous stage; a thirteenth thin film transistor, whose gate is connected to the fourth node, a source thereof is connected to the second node, a drain thereof is connected to the first node; and
the third switch module, used to maintain said third node at a low level when the shift register of the present stage does not operate, which comprising: a fourteenth thin film transistor, whose gate is connected to the source of the seventh thin film transistor, a source thereof is connected to the third node, a drain thereof is connected to the low level signal terminal; a fifteenth thin film transistor, whose gate is connected to the fourth node, a source thereof is connected to the third node, a drain thereof is connected to the low level signal terminal.
4. The shift register as claimed in claim 2, further comprising: a seventeenth thin film transistor, whose gate is connected to the switch signal terminal, a source thereof is connected to the reset signal terminal, a drain thereof is connected to the second node.
5. The shift register as claimed in claim 2, further comprising: a sixteenth thin film transistor, whose gate is connected to the switch signal terminal, a source thereof is connected to the first node, a drain thereof is connected to the low level signal terminal.
6. The shift register as claimed in claim 3, further comprising: a sixteenth thin film transistor, whose gate is connected to the switch signal terminal, a source thereof is connected to the first node, a drain thereof is connected to the low level signal terminal.
7. The shift register as claimed in claim 3, further comprising: a seventeenth thin film transistor, whose gate is connected to the switch signal terminal, a source thereof is connected to the reset signal terminal, a drain thereof is connected to the second node.
8. The shift register as claimed in claim 1, further comprising: a sixteenth thin film transistor, whose gate is connected to the switch signal terminal, a source thereof is connected to the first node, a drain thereof is connected to the low level signal terminal.
9. The shift register as claimed in claim 1, further comprising: a seventeenth thin film transistor, whose gate is connected to the switch signal terminal, a source thereof is connected to the reset signal terminal, a drain thereof is connected to the second node.
10. A gate line driving device, comprising a plurality of shift registers connected in series, wherein said shift register comprises:
a first thin film transistor, whose gate is connected to a first node as a pull-up node, a source thereof is connected to a clock signal terminal, a drain thereof is connected to a output terminal of the present stage;
a second thin film transistor, whose gate is connected to a feedback signal terminal of the next stage, a source thereof is connected to said first node, a drain thereof is connected to a low level signal terminal;
a third thin film transistor, whose gate is connected to a feedback signal terminal of the next stage, a source thereof is connected to a second node as a pull-down node, a drain thereof is connected to the low level signal terminal, wherein the second node is connected with the output terminal of the present stage;
a capacitor, connected between said first node and the output terminal of the present stage;
a feedback module, connected between the trigger signal terminal of the previous stage, the clock signal terminal and said first node, and connected to the feedback signal terminal of the present stage and the trigger signal terminal of the present stage; and
a switch module, connected with the clock signal terminal, said feedback module and the output terminal of the present stage, and connected to the low level signal terminal;
wherein said feedback module is used to receive a trigger signal of the feedback module of the previous stage and the clock signal, in order to pull up the level of the first node, and to output feedback signal to the shift register of the previous stage and output the trigger signal to the feedback module of the next stage, said switch module is used to maintain the output terminal of the shift register of the present stage at a low level when the shift register of the present stage does not operate.
11. The gate line driving device as claimed in claim 10, wherein said feedback module comprises:
a fourth thin film transistor, whose gate is connected to a first trigger signal terminal of the feedback module of the previous stage, a source thereof is connected to a gate of the fifth thin film transistor, a drain thereof is connected to a clock signal terminal;
a fifth thin film transistor, whose gate is connected to the source of the fourth thin film transistor, a source thereof is connected to the first node, a drain thereof is connected to the second trigger signal terminal of the feedback module of the previous stage; and
a sixth thin film transistor, whose gate is connected to the first node, a source thereof is connected to the clock signal terminal, a drain thereof is connected to a third node as a feedback node of the present stage.
12. The gate line driving device as claimed in claim 11, wherein said switch module comprises:
class-1 switch module, which is used to control a first switch module, a second switch module and a third switch module, said class-1 switch module comprising: a seventh thin film transistor, whose gate and drain are connected together to the clock signal terminal, a source thereof is connected to the second switch module and the third switch module; a eighth thin film transistor, whose gate is connected to the clock signal terminal, a source thereof is connected to a fourth node as a interlocking node, a drain thereof is connected to the low level signal terminal; a ninth thin film transistor, whose gate and source are connected together to the clock signal terminal, a drain thereof is connected to the fourth node;
the first switch module, used to maintain the output terminal of the present stage at a low level when the shift register of the present stage does not operate, which comprising: a tenth thin film transistor, whose gate is connected to the clock signal terminal, a source thereof is connected to the second node, a drain thereof is connected to the low level signal terminal; a eleventh thin film transistor, whose gate is connected to the fourth node, a source thereof is connected to the second node, a drain thereof is connected to the low level signal terminal;
the second switch module, used to maintain said first node at a low level when the shift register of the present stage does not operate, which comprising: a twelfth thin film transistor, whose gate is connected to the source of the seventh thin film transistor, a source thereof is connected to the first node, a drain thereof is connected to the feedback module of the previous stage; a thirteenth thin film transistor, whose gate is connected to the fourth node, a source thereof is connected to the second node, a drain thereof is connected to the first node;
the third switch module, used to maintain said third node at a low level when the shift register of the present stage does not operate, which comprising: a fourteenth thin film transistor, whose gate is connected to the source of the seventh thin film transistor, a source thereof is connected to the third node, a drain thereof is connected to the low level signal terminal; a fifteenth thin film transistor, whose gate is connected to the fourth node, a source thereof is connected to the third node, a drain thereof is connected to the low level signal terminal.
13. The gate line driving device as claimed in claim 11, wherein said shift register further comprises: a seventeenth thin film transistor, whose gate is connected to the switch signal terminal, a source thereof is connected to the reset signal terminal, a drain thereof is connected to the second node.
14. The gate line driving device as claimed in claim 11, wherein said shift register further comprises: a sixteenth thin film transistor, whose gate is connected to the switch signal terminal, a source thereof is connected to the first node, a drain thereof is connected to the low level signal terminal.
15. The gate line driving device as claimed in claim 12, wherein said shift register further comprises: a sixteenth thin film transistor, whose gate is connected to the switch signal terminal, a source thereof is connected to the first node, a drain thereof is connected to the low level signal terminal.
16. The gate line driving device as claimed in claim 12, wherein said shift register further comprises: a seventeenth thin film transistor, whose gate is connected to the switch signal terminal, a source thereof is connected to the reset signal terminal, a drain thereof is connected to the second node.
17. The gate line driving device as claimed in claim 10, wherein said shift register further comprises: a sixteenth thin film transistor, whose gate is connected to the switch signal terminal, a source thereof is connected to the first node, a drain thereof is connected to the low level signal terminal.
18. The gate line driving device as claimed in claim 10, wherein said shift register further comprises: a seventeenth thin film transistor, whose gate is connected to the switch signal terminal, a source thereof is connected to the reset signal terminal, a drain thereof is connected to the second node.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of identifying a potential attack in network traffic that includes payload data transmitted to a host entity in a network, the method including:
monitoring and checking said traffic on route to said host entity for intrusion attacks;
performing a first data-check on one or more data bytes of the payload data at the host entity;
performing a second data-check, equivalent to the first data-check, on data of the network equivalent to the one or more bytes of payload data; and
comparing the results of the first and second data-checks to determine if there is a mismatch, any mismatch being an indication that said step of monitoring and checking said traffic on route to said host entity for intrusion attacks is unreliable,
wherein the first data-check is performed by a Host Intrusion Protection System (HIPS) and the second data-check is performed by an Intrusion Detection SystemIntrusion Protection System (IDSIPS).
2. The method of claim 1 wherein the HIPS is provided with a communication channel to the IDSIPS, the results of the first andor the second data-check being transmitted over the communication channel for the comparing.
3. The method of claim 2 further comprising providing the HIPS with configuration information specifying network connection types for which the method of identifying a potential attack is to be applied.
4. The method of claim 3 further comprising sending the configuration information to the IDSIPS.
5. The method of claim 1 wherein the payload data is an application level payload, and wherein the HIPS uses network hooks for accessing the payload to perform the first data-check.
6. The method of claim 1 wherein the data-checks are compared as the bytes are transmitted over the network.
7. The method of claim 1 wherein the first data-check is performed on a server monitoring traffic on a connection relating to a service, the method further comprising performing a predetermined action in response to the indication that said monitoring and checking step is unreliable.
8. The method of claim 7 wherein the predetermined action comprises terminating the connection, or logging the potential attack, or both.
9. The method of claim 1 wherein the first data-check is performed on a client computer monitoring traffic on a connection between the client computer and a remote network entity, the method further comprising notifying a user of the client computer of the indication that said monitoring and checking step is unreliable.
10. The method of claim 9 further comprising providing an option for the user to terminate the connection or to accept the payload.
11. The method of claim 9 further comprising automatically terminating the connection.
12. The method of claim 1 wherein performing the first and second data-checks comprise calculating a checksum.
13. The method of claim 12 wherein the checksum calculation is a sliding checksum with offset information.
14. The method of claim 1 wherein the indication that said monitoring and checking step is unreliable is identified as an indication of an attack that might include a plurality of Advanced Evasion Techniques (AETs).
15. A method comprising:
monitoring and checking said traffic on route to the host to identify an attack in network traffic that includes application level payload transmitted tofrom a host over a network connection and that includes a plurality of Advanced Evasion Techniques (AETs);
providing a Host Intrusion Protection System (HIPS) with a communication channel to an Intrusion Detection SystemIntrusion Protection System (IDSIPS);
the HIPS accessing at least a portion of the application level payload and calculating a checksum thereof;
the IDSIPS performing an equivalent checksum calculation for an equivalent portion of the application level payload assembled therein;
comparing the checksums calculated by the HIPS and the IDSIPS; and
signalling that said step of monitoring and checking said traffic on route to said host entity for intrusion attacks is unreliable if there is a mismatch.
16. A system comprising:
a network monitoring device configured to monitor and check said traffic on route to the host entity to identify a potential attack in network traffic that includes payload data transmitted to a host entity in a network;
a first data-checker configured to perform a first data-check on one or more data bytes of the payload data;
a second data-checker configured to perform a second data-check, equivalent to the first data-check, on data of the network equivalent to the one or more data bytes of the payload data; and
a comparator for comparing results of the first and second data-checks to determine if there is a mismatch, the mismatch being an indication that results from said network monitoring device are unreliable.
17. The system of claim 16 wherein the first data-checker is comprised within a Host Intrusion Protection System (HIPS) on the host entity, and the network monitoring device and the second data-checker are comprised within an Intrusion Detection SystemIntrusion Protection System (IDSIPS), the system further comprising a communication channel connecting the HIPS and the IDSIPS.
18. The system of claim 17 wherein the HIPS is installed on a server and is configured to monitor traffic relating to a service.
19. The system of claim 17 wherein the HIPS is installed on a client computer and is configured to monitor traffic between the client computer and a remote network entity.
20. A system comprising:
a host computer that includes a network connection over which the network traffic is sentreceived and a Host Intrusion Protection System (HIPS);
an Intrusion Detection SystemIntrusion Protection System (IDSIPS) for identifying an attack in network traffic that includes application level payload and that includes a plurality of Advanced Evasion Techniques (AETs);
a communication channel connecting the HIPS and the IDSIPS;
wherein the HIPS is configured to access at least a portion of the application level payload and to calculate a checksum thereof, the IDSIPS is configured to monitor and check said traffic on route to the host entity for attacks, and to perform an equivalent checksum calculation for an equivalent portion of the application level payload assembled therein; and
a comparator for comparing the checksums calculated by the HIPS and the IDSIPS and for signalling that the monitoring and checking performed by said IDSIPS is unreliable if there is a mismatch.
21. A computer network entity comprising:
a data-check comparator configured to perform a comparison between a first data-check of one or more data bytes of a payload of network traffic destined for a host entity and a second data-check, equivalent to the first data-check, on data of the network traffic equivalent to the one or more data bytes of the payload of network traffic and to signal that results of monitoring and checking said network traffic on route to said host entity for intrusion attacks are unreliable if the data-check comparison indicates a mismatch between the first and second data-checks,
wherein the first data-check is performed by a Host Intrusion Protection System (HIPS) and the second data-check is performed by an Intrusion Detection SystemIntrusion Protection System (IDSIPS).