1. A super-paramagnetic cladding layer comprised of a plurality of MLSL stacks formed adjacent to at least one side of a conductive line in a magnetic device in which said at least one side does not contact a sensor element and each MLSL stack is comprised of:
(a) a lower seed layer (SL); and
(b) an upper ML layer which is a composite comprised of a soft magnetic layer made of discontinuous particles formed on the SL layer and a capping layer formed on the soft magnetic layer and on the SL layer between the discontinuous particles.
2. The super-paramagnetic cladding layer of claim 1 wherein the magnetic device is an MRAM, the sensor element is an MTJ, and the conductive line is a word line, bit line, digit line, data line, column line, or row line.
3. The super-paramagnetic cladding layer of claim 1 wherein said seed layer is comprised of amorphous AlOx or another amorphous oxide with a thickness from about 0.8 to 10 nm.
4. The super-paramagnetic cladding layer of claim 1 wherein the soft magnetic layer is comprised of a soft magnetic alloy with near zero magnetostriction.
5. The super-paramagnetic cladding layer of claim 4 wherein the soft magnetic layer has a thickness less than about 2 nm and is comprised of NiFe having a Ni content of about 80 atomic % (Ni\u02dc80Fe\u02dc20), NiFe having a Ni content of about 30 atomic % (Ni\u02dc30Fe\u02dc70), CoFe having a Co content of about 90 atomic % (Co\u02dc90Fe\u02dc10), or combinations thereof.
6. The super-paramagnetic cladding layer of claim 1 wherein the soft magnetic layer is super para-magnetic at a temperature range above \u221230\xb0 C.
7. The super-paramagnetic cladding layer of claim 1 wherein the capping layer is about 0.5 to 5 nm thick and is comprised of Ru, Ta, or Cu.
8. The super-paramagnetic cladding layer of claim 1 wherein said super-para-magnetic cladding layer is comprised of about 5 to 50 MLSL stacks.
9. The super-paramagnetic cladding layer of claim 1 wherein a SL andor ML layer in a first MLSL stack has a different composition andor thickness than a SL or ML layer, respectively, in a second MLSL stack.
10. The super-paramagnetic cladding layer of claim 1 wherein the substrate is a dielectric layer andor said conductive line.
11. An MRAM structure, comprising:
(a) a first conductive line for passing a current therethrough to generate a magnetic field for switching a magnetic orientation of a free layer in an adjacent MTJ having a top surface and a bottom surface, said first conductive line has four sides including a side that contacts the bottom surface of said MTJ;
(b) a second conductive line for passing a current therethrough to generate a magnetic field for switching the magnetic orientation of the free layer in said MTJ, said second conductive line is aligned orthogonal to the first conductive line and has four sides including a side that contacts the top surface of said MTJ; and
(c) a super-paramagnetic cladding layer formed on at least one side of the first conductive line andor second conductive line wherein said at least one side does not contact said MTJ and wherein said super-paramagnetic cladding layer is comprised of a plurality of MLSL stacks in which SL is a seed layer formed on a substrate, and ML is a composite comprised of a soft magnetic layer made of discontinuous particles on the seed layer and a capping layer formed on the soft magnetic layer and on the seed layer between the discontinuous particles.
12. The MRAM structure of claim 11 wherein the first conductive line is a word line, bit line, digit line, data line, column line, or row line and is formed in a trench within a dielectric layer.
13. The MRAM of claim 11 wherein said seed layer is comprised of amorphous AlOx or another amorphous oxide with a thickness between about 0.8 and 10 nm.
14. The MRAM of claim 11 wherein the soft magnetic layer is comprised of a soft magnetic alloy with near zero magnetostriction.
15. The MRAM structure of claim 14 wherein the soft magnetic layer has a thickness less than about 2 nm and is comprised of NiFe having a Ni content of about 80 atomic % (Ni\u02dc80Fe\u02dc20), NiFe having a Ni content of about 30 atomic % (Ni\u02dc30Fe\u02dc70), CoFe having a Co content of about 90 atomic % (Co\u02dc90Fe\u02dc10), or combinations thereof.
16. The MRAM structure of claim 11 wherein the soft magnetic layer is super-para-magnetic at a temperature range above \u221230\xb0 C.
17. The MRAM structure of claim 11 wherein the capping layer is about 0.5 to 5 nm thick and is comprised of Ru, Ta, or Cu.
18. The MRAM structure of claim 11 wherein a plurality of MLSL stacks is defined as between about 5 and 50 MLSL stacks.
19. The MRAM structure of claim 11 wherein said super-paramagnetic cladding layer is comprised of an SL andor ML layer in a first MLSL stack that differs in composition andor thickness from an SL andor ML layer, respectively, in a second MLSL stack.
20. The MRAM structure of claim 11 wherein a first super-paramagnetic cladding layer is formed on the first conductive line and a second super-paramagnetic cladding layer is formed on the second conductive line and the first super-paramagnetic cladding layer has a thickness and composition essentially the same as that of the second super-paramagnetic cladding layer.
21. A method of forming a super-paramagnetic layer adjacent to a conductive line in a magnetic device having a sensor element; comprising:
(a) providing a substrate;
(b) depositing a seed layer (SL) on said substrate;
(c) forming a soft magnetic layer comprised of discontinuous particles on said seed layer;
(d) forming a capping layer on said soft magnetic layer and on said seed layer between the discontinuous particles to complete a first MLSL stack; and
(e) repeating steps (b)-(d) a plurality of times to form a total of \u201cx\u201d MLSL stacks.
22. The method of claim 21 wherein said magnetic device is an MRAM and said conductive line is a bit line, word line, digit line, data line, column line, or row line having four sides wherein one side is formed adjacent to a top surface or bottom surface of an MTJ in said MRAM, and said super-paramagnetic layer is formed on from one to three sides of the conductive line but not on the side adjacent to the MTJ.
23. The method of claim 22 wherein the substrate is the conductive line formed on the top surface of the MTJ.
24. The method of claim 22 wherein the substrate is a dielectric layer having a trench in which the conductive line will be formed following step (e) and said conductive line contacts the bottom surface of the MTJ.
25. The method of claim 21 wherein said seed layer is comprised of AlOx that is formed by a reactive sputtering of AlOx on said substrate or by first depositing an Al layer on the substrate and then oxidizing by a plasma, radical, or natural oxidation step.
26. The method of claim 21 wherein the soft magnetic layer is less than about 2 nm thick and is comprised of NiFe having a Ni content of about 80 atomic % (Ni\u02dc80Fe\u02dc20), NiFe having a Ni content of about 30 atomic % (Ni\u02dc30Fe\u02dc70), CoFe having a Co content of about 90 atomic % (Co\u02dc90Fe\u02dc10), or combinations thereof.
27. The method of claim 26 wherein the soft magnetic layer is deposited by a sputter deposition, CVD, PECVD, or IBD process.
28. The method of claim 21 wherein the capping layer is comprised of Ru, Ta, or Cu and is formed by a sputter deposition, CVD, PVD, PECVD, or IBD process.
29. The method of claim 21 wherein \u201cx\u201d is between about 5 and 50 and the total thickness of the super para-magnetic cladding layer is about 10 to 150 nm.
30. The method of claim 21 wherein the capping layer has a thickness between about 0.5 and 5 nm above the seed layer.
31. The method of claim 21 wherein the capping layer has a substantially flat surface.
32. The method of claim 21 wherein the thickness and composition of a soft magnetic layer in a first MLSL stack is different than that of a soft magnetic layer in a second MLSL stack.
33. The method of claim 21 wherein the thickness and composition of a capping layer in a first MLSL stack is different than that of a capping layer in a second MLSL stack.
34. The method of claim 21 wherein said substrate is heated at a temperature between about 80\xb0 C. and 200\xb0 C. during the formation of a soft magnetic layer comprised of discontinuous particles.
35. The method of claim 24 wherein the magnetic device is further comprised of a second conductive line on the top surface of the MTJ and a second super-paramagnetic cladding layer is formed on the second conductive line but not on a side of the second conductive line that contacts the top surface of the MTJ.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A fabricating method of an amorphous-silicon photoelectric device, comprising steps of:
performing a first patterning process so that patterns of a gate-electrode layer, a photosensor with the photodiode structure and a contact layer located below the photosensor are formed on a substrate, the contact layer being partially covered by the photosensor, the contact layer and the gate-electrode layer being provided in a same layer and made of a same material;
performing a second patterning process, so that patterns of an insulating layer, a semiconductor layer and a sourcedrain-electrode layer are sequentially formed on the resultant substrate of the first patterning process; and
forming a first passivation layer on the resultant substrate of the second patterning process, and performing a third patterning process so that a first via-hole is formed in the first passivation layer to expose partial regions of the contact layer, the photosensor, and the sourcedrain-electrode layer.
2. The method according to claim 1, further comprising steps of:
performing a fourth patterning process so that an electrically-conductive layer is formed on the resultant substrate of the third patterning process, and the electrically-conductive layer covering the first via-hole and the region of the semiconductor layer located between the source electrode and the drain electrode, and connecting the contact layer and a source electrode or a drain electrode in the sourcedrain-electrode layer.
3. The method according to claim 2, further comprising steps of:
forming a second passivation layer on the resultant substrate of the fourth patterning process, and performing a fifth patterning process so that a second via-hole is formed in the second passivation layer to at least expose a partial region of a gate line; and
performing a sixth patterning process so that a first transparent electrically-conductive layer is formed on the resultant substrate of the fifth patterning process to cover the second via-hole.
4. The method according to claim 1, wherein the step of performing a first patterning process so that patterns of a gate-electrode layer, a photosensor with the photodiode structure and a contact layer located below the photosensor are formed on a substrate comprises steps of:
forming the gate-electrode layer, a semiconductor layer, a transparent electrically-conductive layer and a photoresist on the substrate; and
performing an exposure-and-development-process, an etching process and an ashing process on the resultant substrate of the previous step so that the gate-electrode layer, the gate-line contact layer and the photosensor are formed.
5. The method according to claim 4, wherein the step of performing the exposure-and-development-process comprises the steps of:
performing a partial exposing process on a photoresist located above the gate-electrode layer, the gate line and a region of the contact layer which is not covered by the photosensor, so as to form a partially-exposed region;
performing no exposing process on a photoresist located above the photosensor, so as to form a non-exposed region; and
performing full exposing process on a photoresist located in other regions so as to form a fully-exposed region.
6. The method according to claim 5, wherein the steps of performing the etching process and an ashing process comprises the steps of:
performing an etching process on a second transparent electrically-conductive layer in the photosensor with the photodiode structure so as to etch off the second transparent electrically-conductive layer in the fully-exposed region;
performing an etching process on the semiconductor layer in the photosensor with the photodiode structure so as to etch off the semiconductor layer in the photosensor with the photodiode structure in the fully-exposed region;
performing an etching process on the gate-electrode layer so as to etch off the gate-electrode layer in the fully-exposed region;
removing the photoresist in the partially-exposed region in an ashing process;
performing an etching process on the second transparent electrically-conductive layer in the photosensor with the photodiode structure so as to etch off the second transparent electrically-conductive layer in the partially-exposed region;
performing an etching process on the semiconductor layer in the photosensor with the photodiode structure so as to etch off the semiconductor layer in the photosensor with the photodiode structure in the partially-exposed region; and
stripping off the residual photoresist on the substrate completely.
7. An amorphous-silicon photoelectric device comprising: a substrate; a thin-film transistor and a photosensor with the photodiode structure provided at different positions on the substrate; and a contact layer located below the photosensor and partially covered by the photosensor, wherein the contact layer and the gate-electrode layer in the thin-film transistor are provided in a same layer and made of a same material.
8. The amorphous-silicon photoelectric device according to claim 7, further comprises:
a first passivation layer covering over the photosensor and the thin-film transistor,
a first via-hole provided in the first passivation layer to expose partial regions of the contact layer, the photosensor, and a sourcedrain-electrode layer in the thin-film transistor, and
an electrically-conductive layer provided above the first passivation layer so as to cover the first via-hole and the region of the semiconductor layer located between a source electrode and a drain electrode in the thin-film transistor, and connect the contact layer and the source electrode or drain electrode in the thin-film transistor.
9. The method according to claim 2, wherein the step of performing a first patterning process so that patterns of a gate-electrode layer, a photosensor with the photodiode structure and a contact layer located below the photosensor are formed on a substrate comprises following steps of:
forming the gate-electrode layer, a semiconductor layer, a transparent electrically-conductive layer and a photoresist on the substrate; and
performing an exposure-and-development-process, an etching process and an ashing process on the resultant substrate of the previous step so that the gate-electrode layer, the gate-line contact layer and the photosensor are formed.
10. The method according to claim 9, wherein the step of performing the exposure-and-development-process comprises the steps of:
performing a partial exposing process on a photoresist located above the gate-electrode layer, the gate line and a region of the contact layer which is not covered by the photosensor, so as to form a partially-exposed region;
performing no exposing process on a photoresist located above the photosensor, so that the photoresist located above the photosensor remains as a non-exposed region; and
performing full exposing process on a photoresist located in other regions so as to form a fully-exposed region.
11. The method according to claim 10, wherein the steps of performing the etching process and an ashing process comprises the steps of:
performing an etching process on a second transparent electrically-conductive layer in the photosensor with the photodiode structure so as to etch off the second transparent electrically-conductive layer in the fully-exposed region;
performing an etching process on the semiconductor layer in the photosensor with the photodiode structure so as to etch off the semiconductor layer in the photosensor with the photodiode structure in the fully-exposed region;
performing an etching process on the gate-electrode layer so as to etch off the gate-electrode layer in the fully-exposed region;
removing the photoresist in the partially-exposed region in an ashing process;
performing an etching process on the second transparent electrically-conductive layer in the photosensor with the photodiode structure so as to etch off the second transparent electrically-conductive layer in the partially-exposed region;
performing an etching process on the semiconductor layer in the photosensor with the photodiode structure so as to etch off the semiconductor layer in the photosensor with the photodiode structure in the partially-exposed region; and
stripping off the residual photoresist on the substrate completely.
12. The method according to claim 3, wherein the step of performing a first patterning process so that patterns of a gate-electrode layer, a photosensor with the photodiode structure and a contact layer located below the photosensor are formed on a substrate comprises following steps of:
forming the gate-electrode layer, a semiconductor layer, a transparent electrically-conductive layer and a photoresist on the substrate; and
performing an exposure-and-development-process, an etching process and an ashing process on the resultant substrate of the previous step so that the gate-electrode layer, the gate-line contact layer and the photosensor are formed.
13. The method according to claim 12, wherein the step of performing the exposure-and-development-process comprises the steps of:
performing a partial exposing process on a photoresist located above the gate-electrode layer, the gate line and a region of the contact layer which is not covered by the photosensor, so as to form a partially-exposed region;
performing no exposing process on a photoresist located above the photosensor, so as to form a non-exposed region; and
performing full exposing process on a photoresist located in other regions so as to form a fully-exposed region.
14. The method according to claim 13, wherein the steps of performing the etching process and an ashing process comprises the steps of:
performing an etching process on a second transparent electrically-conductive layer in the photosensor with the photodiode structure so as to etch off the second transparent electrically-conductive layer in the fully-exposed region;
performing an etching process on the semiconductor layer hi the photosensor with the photodiode structure so as to etch off the semiconductor layer in the photosensor with the photodiode structure hi the fully-exposed region;
performing an etching process on the gate-electrode layer so as to etch off the gate-electrode layer in the fully-exposed region;
removing the photoresist in the partially-exposed region in an ashing process;
performing an etching process on the second transparent electrically-conductive layer in the photosensor with the photodiode structure so as to etch off the second transparent electrically-conductive layer in the partially-exposed region;
performing an etching process on the semiconductor layer in the photosensor with the photodiode structure so as to etch off the semiconductor layer in the photosensor with the photodiode structure in the partially-exposed region; and
stripping off the residual photoresist on the substrate completely.