Author: claimsbot

1. A method comprising:
receiving, by a host adapter, a hardware IO command block including a target IO command for a target IO device;
modifying said hardware IO command block to include an abort command; and
checking a state of a flag in said hardware IO command block to determine whether both said abort command and said target IO command have completed.
2. The method of claim 1 further comprising:
scheduling said hardware IO command block for execution by said host adapter following said modifying.
3. The method of claim 1 wherein said modifying does not affect information is said hardware IO command block for said target IO command.
4. The method of claim 1 wherein said modifying is performed by a host adapter manager executing on a host system.
5. The method of claim 1 wherein said modifying is performed by a sequencer of said host adapter.
6. The method of claim 1 further comprising:
notifying a host system of completion of both said abort command and said target IO command when said flag has an asserted state.
7. The method of claim 6 further comprising:
leaving said flag asserted only following completion of execution of both said abort command and said target IO command.
8. A method comprising:
receiving, by a host adapter, a hardware IO command block including a target IO command for a target IO device;
modifying said hardware IO command block to include an abort command;
scheduling said hardware IO command block for execution by said host adapter following said modifying;
checking a state of a flag in said hardware IO command block to determine whether both said abort command and said target IO command have completed; and
notifying a host system of completion of both said abort command and said target IO command when said flag has an asserted state.
9. The method of claim 8 wherein said modifying does not affect information is said hardware IO command block for said target IO command.
10. The method of claim 8 wherein said modifying is performed by a host adapter manager executing on a host system.
11. The method of claim 8 wherein said modifying is performed by a sequencer of said host adapter.
12. The method of claim 8 further comprising:
leaving said flag asserted only following completion of execution of both said abort command and said target IO command.
13. A method comprising:
configuring a done flag in a hardware IO control block, which includes a target IO command, to a first state wherein said first state indicates said target IO command has not been executed by a host adapter; and
configuring said hardware IO control block to include an abort command for said target IO command wherein said hardware IO control block includes both said target IO command and said abort command.
14. The method of claim 13 further comprising:
configuring said done flag to a second state upon completion of said target IO command and said abort command.
15. The method of claim 13 further comprising:
scheduling said hardware IO command block for execution by said host adapter following said configuring said hardware IO control block to include said abort command.
16. The method of claim 13 further comprising:
determining whether both said abort command and said target IO command have completed.
17. The method of claim 16 wherein said determining further comprises:
checking a state of said done flag in said hardware IO command block.
18. The method of claim 17 further comprising:
notifying a host system of completion of both said abort command and said target IO command when said done flag has a second state.
19. A method comprising:
configuring a done flag in a hardware IO control block, which includes a target IO command, to a first state wherein said first state indicates said target IO command has not been executed by a host adapter;
configuring said hardware IO control block to include an abort command for said target IO command wherein said hardware IO control block includes both said target IO command and said abort command;
scheduling said hardware IO command block for execution by said host adapter following said configuring said hardware IO control block to include said abort command;
determining whether both said abort command and said target IO command have completed; and
configuring said done flag to a second state upon completion of said target IO command and said abort command.
20. The method of claim 19 wherein said determining further comprises:
checking a state of said done flag in said hardware IO command block.
21. The method of claim 20 further comprising:
notifying a host system of completion of both said abort command and said target IO command when said done flag has a second state.
22. A method comprising:
determining whether a hardware IO command block including a target IO command to be aborted is in a host adapter execution queue;
removing said hardware IO command block from said execution queue upon said determining finding that said hardware IO command block is in said host adapter execution queue; and
determining a state of a done flag in said hardware IO command block upon said determining finding that said hardware IO command block is not in said host adapter execution queue.
23. The method of claim 22 further comprising:
modifying said hardware IO command block to include an abortion command for said target IO command upon said determining said state of said done flag finding that said done flag is unasserted.
24. The method of claim 23 further comprising:
scheduling said hardware IO command block for execution by said host adapter following said modifying said hardware IO control block to include said abort command.
25. A method comprising:
using a single hardware IO command block structure for both a target IO command and an abortion command for said target IO command; and
asserting a done flag in said single hardware IO command block structure when both said target IO command and said abortion command for said target IO command are completed.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A process for converting respective sets of sheets having voids or notches formed inwardly from each page into a device for one by one separation or turning of each sheet without missing a sheet, the sheets of each set having the notches or voids in matching configurations and offset from the notches or voids of the sheets not included in the same set, the process comprising:
i. providing a first supply of sheets of a first set of the sheets;
ii. providing a second supply of sheets of a second set of the sheets;
iii. advancing an nth sheet from the first supply in a feed path;
iv. advancing an nth+1 sheet from the second supply into stacked relation to one surface of the nth sheet;
v. advancing an nth+2 sheet from the first supply into stacked relation to the nth+1 sheet opposite the nth sheet; and
vi. repeating (iv) and (v) with n incremented by two in each instance for completing the device as a stack of sheets having the void or notch shapes alternating in position with each successive sheet in the stack.
2. The process of claim 1, wherein the first and second supplies of sheets comprise respective first and second stacks of sheets, the advancing of the nth and nth+2 sheets comprising moving the sheets from one end of the first stack, and the advancing of the nth+1 sheet comprising moving the sheets from an opposite end of the second stack.

1. A dielectric composition comprising:
(a) barium titanate having a specific surface area of 2.5 m2g to 6.0 m2g;
(b) a mixture containing at least one or more materials selected from the group consisting of any one oxide of Mg, Ca, Sr, Ba and Zr, and any one carbide thereof;
(c) oxide containing at least one or more materials selected from the group consisting of Sc, Y, La, Ac, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu;
(d) oxide containing at least one or more material selected from the group consisting of Cr, Mn, Fe, Co, and Ni;
(e) oxide containing at least one or more material selected from the group consisting of V, Nb, and Ta; and
(f) oxide containing at least one or more material selected from the group consisting of Si and Al.
2. The dielectric composition according to claim 1,
wherein the barium titanate is expressed as BamTiO3, where 0.995\u2266m\u22661.010.
3. The dielectric composition according to claim 1,
wherein the content of the (b) component is 3 mol to 10 mol relative to 100 mol of the (a) component;
the content of the (c) component is 1 mol to 9 mol relative to 100 mol of the (a) component;
the content of the (d) component is 0.01 mol to 1 mol relative to 100 mol of the (a) component;
the content of the (e) component is 0.01 mol to 1 mol relative to 100 mol of the (a) component; and
the content of the (f) component is 1.5 mol to 5 mol relative to 100 mol of the (a) component.
4. The dielectric composition according to claim 1,
wherein a value of ((total number of moles of the (b) component)\u2212(number of moles of the Zr oxide))(number of moles of the (f) component) is in a range of 1 to 1.5.
5. The dielectric composition according to claim 1,
wherein a value of (number of moles of the (c) component)(number of moles of the (f) component) is in a range of 1.5 to 3.
6. The dielectric composition according to claim 1,
wherein a specific surface area of a mixture containing the (b) component, the (c) component, the (d) component, the (e) component, and the (f) component is in a range of 5.0 m2g to 100 m2g.
7. The dielectric composition according to claim 1, further comprising:
(g) Li oxide, wherein the content of the (g) component is 0.01 mol to 0.6 mol relative to 100 mol of the (a) component.
8. The dielectric composition according to claim 7,
wherein a specific surface area of a mixture containing the (b) component, the (c) component, the (d) component, the (e) component, the (f) component, and the (g) component is in a range of 5.0 m2g to 100 m2g.
9. The dielectric composition according to claim 1,
wherein the (b) component and the (e) component have a single oxide form.
10. A ceramic electronic component comprising:
a dielectric layer formed of a dielectric composition, the composition including:
(a) barium titanate having a specific surface area of 2.5 m2g to 6.0 m2g;
(b) a mixture containing at least one or more materials selected from the group consisting of any one oxide of Mg, Ca, Sr, Ba and Zr, and any one carbide thereof;
(c) oxide containing at least one or more materials selected from the group consisting of Sc, Y, La, Ac, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu;
(d) oxide containing at least one or more material selected from the group consisting of Cr, Mn, Fe, Co, and Ni;
(e) oxide containing at least one or more material selected from the group consisting of V, Nb, and Ta; and
(f) oxide containing at least one or more material selected from the group consisting of Si and Al.
11. The ceramic electronic component according to claim 10,
wherein the content of the (b) component is 3 mol to 10 mol relative to 100 mol of the (a) component;
the content of the (c) component is 1 mol to 9 mol relative to 100 mol of the (a) component;
the content of the (d) component is 0.01 mol to 1 mol relative to 100 mol of the (a) component;
the content of the (e) component is 0.01 mol to 1 mol relative to 100 mol of the (a) component; and
the content of the (f) component is 1.5 mol to 5 mol relative to 100 mol of the (a) component.
12. The ceramic electronic component according to claim 10,
wherein a specific surface area of a mixture containing the (b) component, the (c) component, the (d) component, the (e) component, and the (f) component is in a range of 5.0 m2g to 100 m2g.
13. The ceramic electronic component according to claim 10, further comprising:
(g) Li oxide, wherein the content of the (g) component is 0.01 mol to 0.6 mol relative to 100 mol of the (a) component.
14. The ceramic electronic component according to claim 13,
wherein a specific surface area of a mixture containing the (b) component, the (c) component, the (d) component, the (e) component, the (f) component, and the (g) component is in a range of 5.0 m2g to 100 m2g.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. Antenna system with a diversity order of 2 comprising, on a same substrate provided with a metallization plane, first and second radiating elements positioned on two adjacent sides of the substrate near edges of the said substrate, the first and second radiating elements being each constituted by an F-inverted type antenna printed on the metallization plane side of the substrate, the first and second radiating elements being positioned on the substrate at the level of the corner formed by the two adjacent sides and being linked to each other at an extremity of the F-inverted, said extremity being connected to the metallization plane.
2. System according to claim 1, wherein each F-inverted type antenna is etched in the metallization plane.
3. System according to claim 1, wherein each F-inverted type antenna is etched in at least two metallization planes of the substrate, the strands thus etched being connected by means of vias or metallized holes.
4. System according to claim 1, wherein the F-inverted type antenna comprises a conductive strand parallel to one side of the substrate, the conductive strand extending by one extremity part connected to the metallization plane of the substrate, the antenna being connected to an impedance matched feeder line perpendicular to the conductive strip.
5. System according to claim 4, wherein the antenna has a resonant frequency obtained by using the equation:
D
\ue89e
\ue89e
1

+
H

=

c

4
\xb7
Fres
\xb7
\u025b
eff
wherein c is the speed of light in a vacuum, \u03b5eff the effective permittivity of the propagation environment, Fres the resonant frequency, D1 the length of the conductive strand between its free extremity and the point of connection with the feeder line and H the height between the conductive strand and the metallization plane of the substrate.
6. System according to claim 4, wherein the length of the conductive strands of the two radiating elements is identical.
7. System according to claim 4, wherein the length of the conductive strands of the two radiating elements is different.
8. System according to claim 1, wherein a slot is realized between the two radiating elements at the level of their extremities connected to the metallization plane.
9. System according to claim 8, wherein the length of the slot is chosen so that its resonant frequency matches the resonant frequency of at least one antenna.
10. Electronic card for wireless communication device, featuring an antenna system with a diversity order of 2 according to comprising, on a same substrate provided with a metallization plane, first and second radiating elements positioned on two adjacent sides of the substrate near edges of the said substrate, the first and second radiating elements being each constituted by an F-inverted type antenna printed on the metallization plane side of the substrate, the first and second radiating elements being positioned on the substrate at the level of the corner formed by the two adjacent sides and being linked to each other at an extremity of the F-inverted, said extremity being connected to the metallization plane.