Author: claimsbot

1. A press mold comprising:
a lower mold formed with a molding surface;
an upper mold formed with a molding surface facing the molding surface of said lower mold;
a first sleeve allowing said upper and lower molds to be inserted thereinto from its both end sides; and
a second sleeve provided inside said first sleeve,
said press mold adapted to press-mold a molding material between said upper and lower molds,
wherein said first sleeve regulates a horizontal relative position between said upper and lower molds, and
said second sleeve surrounds an outer periphery of the molding surface of said lower mold and supports at least part of an outer peripheral portion of the molding material placed on the molding surface of said lower mold, thereby preventing position offset of said molding material.
2. A press mold according to claim 1, wherein the molding surface of said lower mold is provided with a convex surface and said second sleeve supports at least part of the outer peripheral portion of the molding material placed on the molding surface of said lower mold to thereby prevent slip-off of said molding material.
3. A press mold according to claim 2, further comprising holding means for holding together said second sleeve and said lower mold.
4. A press mold according to claim 3, wherein said holding means has a suction vent hole formed in said lower mold, said suction vent hole adapted for tightly abutting said second sleeve to said lower mold by sucking of an atmospheric gas, thereby holding together said second sleeve and said lower mold.
5. A press mold according to claim 4, wherein said second sleeve is held on a stepped portion of said lower mold, said stepped portion formed at a position around and below the molding surface of said lower mold.
6. A press mold according to claim 5, wherein said second sleeve has a vent hole at a position intermediate between the molding surface of said lower mold and said stepped portion in an axial direction of said second sleeve.
7. A press mold according to claim 6, wherein said lower mold is provided with a suction vent hole which establishes communication between a bottom surface of said lower mold and said stepped portion.
8. An optical element manufacturing method that uses a press mold comprising a lower mold formed with a molding surface, an upper mold formed with a molding surface facing the molding surface of said lower mold, a first sleeve allowing said upper and lower molds to be inserted thereinto from its both end sides, and a second sleeve provided inside said first sleeve, thereby press-molding a molding material between said upper and lower molds,
wherein, in the state where said upper and lower molds are separated from each other, the molding material is placed on the molding surface of said lower mold and at least part of an outer peripheral portion of said molding material is supported by said second sleeve surrounding an outer periphery of the molding surface of said lower mold, thereby preventing position offset of said molding material, and
said molding material is press-molded by causing said upper and lower molds to approach each other while regulating a horizontal relative position between said upper and lower molds by said first sleeve.
9. An optical element manufacturing method according to claim 8, wherein, after press molding, said lower mold and said second sleeve are held together and separated from said upper mold and said first sleeve, and then a molded article is removed from the molding surface of said lower mold.
10. An optical element manufacturing method according to claim 9, wherein, when removing said molded article after the press molding, said upper mold and said first sleeve are held together and separated from said lower mold and said second sleeve.
11. An optical element manufacturing method according to claim 9, wherein, after the press molding, said press mold is placed on a platform and said platform, said lower mold, and said second sleeve are held together by tightly abutting said platform and said lower mold to each other and tightly abutting said lower mold and said second sleeve to each other by sucking an atmospheric gas, and
said platform, said lower mold, and said second sleeve are separated from said upper mold and said first sleeve and then the molded article is removed from the molding surface of said lower mold.
12. An optical element manufacturing method according to claim 8, wherein the molding material placed inside said press mold is press-molded by transferring said press mold to a plurality of process chambers including a heating chamber, a press chamber, and a cooling chamber and applying thereto processes including heating, pressing, and cooling in the respective process chambers.
13. An optical element manufacturing method according to claim 9, wherein the molding material placed inside said press mold is press-molded by transferring said press mold to a plurality of process chambers including a heating chamber, a press chamber, and a cooling chamber and applying thereto processes including heating, pressing, and cooling in the respective process chambers.
14. An optical element manufacturing method according to claim 11, wherein the molding material placed inside said press mold is press-molded by transferring said press mold to a plurality of process chambers including a heating chamber, a press chamber, and a cooling chamber and applying thereto processes including heating, pressing, and cooling in the respective process chambers.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A system operative to communicate digital data symbols with higher than quadrature phase shift keying (QPSK) modulation, the system comprising a transmitter and a receiver comprising:
the transmitter comprising a modulator and means to split and encode the data into a first block of more significant bits of symbols and a second block of less significant bits of the symbols for modulating by the modulator;
the receiver being operative to receive digital data bits by iterative determination of soft estimates of bits followed by a hard decision as to what bit was intended, the receiver comprising:
a first processor operative to provide first soft estimates of bits of the received signal;
a second processor operative to decode the first soft estimates and to provide second soft estimates of the bits;
a first combiner operative to provide adapted first soft estimates to the second processor, the adapted first soft estimates of each bit being dependent upon a respective first soft estimate and a respective previous first soft estimate; and
a second combiner operative to provide third soft estimates back to the first processor for subsequent further decoding, the third soft estimates of each bit being dependent upon a respective second soft estimate and a respective previous second soft estimate;
wherein the more significant bits are detected in the received signal in a first series of iterations, their estimated contribution to the received signal being subtracted to provide a modified received signal from which the less significant bits are detected by a second series of iterations.
2. A system according to claim 1, wherein the means comprises a first convolutional encoder operative to produce blocks of the more significant bits, a second convolutional encoder operative to produce blocks of less significant bits, and respective interleavers each operative to interleave the blocks from the associated encoder into a respective data stream for modulating.
3. A system according to claim 1, wherein the soft estimates of multiple data streams multiplexed into one stream at the output of the first processor, and provided to the first combiner to provide the adapted first soft estimates are deinterleaved by a deinterleaver before being passed to the second processor, and the third soft estimates provided by the second combiner interleaved by an interleaver before being passed back to the first processor.
4. A system according to claim 1, wherein the first processor is a successive interference cancellation SIC multiple input multiple output MIMO detector and the second processor is a convolutional decoder, the soft estimates being log likelihood ratios.
5. A system according to claim 4, wherein the SIC MIMO detector includes matched filters for detection.
6. A system according to claim 1, wherein the modulation scheme is 16 Quadrature amplitude modulation, the first two bits of a symbol being provided, by the first convolutional encoder, and the last two bits of a symbol being provided by the second convolutional encoder.
7. A system according to claim 1, wherein, a plurality of detection iterations each involving the first processor, second processor and the combiners are performed whereupon a hard decision is made.
8. A method of communicating digital data symbols with higher than quadrature phase shift keying (\u201cQPSK\u201d) modulation method comprising the steps of:
splitting and encoding the data into a first block of more significant bits and a second block of less significant bits for modulating by a modulator;
receiving digital data bits by iterative determination of soft estimates of symbols or bits followed by a hard decision as to what bit was intended, by:
providing first soft estimates of bits of the received signal;
decoding the first soft estimates and providing second soft estimates of the bits;
providing adapted first soft estimates, the adapted first soft estimates of each bit being dependent upon a respective first soft estimate and a respective previous first soft estimate;
providing third soft estimates back for subsequent further decoding, the third soft estimates of each bit being dependent upon a respective second soft estimate and a respective previous second soft estimate;
wherein the more significant bits are detected in the received signal in a first series of iterations, their estimated contribution to the received signal being subtracted to provide a modified received signal from which the less significant bits are detected by a second series of iterations.

1. A semiconductor device comprising:
a substrate including isolation regions and active regions;
a high-k dielectric layer proximate the substrate, the high-k dielectric layer comprising a mixture formed by annealing at least one high-k material and at least one metal, the annealing to oxidize the metal; and
a gate electrode proximate the high-k dielectric layer,
wherein the high-k dielectric layer has a k value within a range of 30 to 70.
2. The semiconductor device of claim 1, wherein the mixture is formed by annealing a first high-k material layer and a first metal layer proximate the first high-k material layer.
3. The semiconductor device of claim 1, wherein the high-k dielectric layer has a thickness within a range of 20 \u212b to 100 \u212b.
4. The semiconductor device of claim 1, wherein the high-k material comprises one of Si3N4, Al2O3, Ta2O5, HfO2, TiO2, HfSiOx, ZrO2, ZrSiOx, La2O3, CeO2, Bi4Si2O12, WO3, Y2O3, LaAlO3, BST, PST, PZN, PZT, and PMN.
5. The semiconductor device of claim 4, wherein the metal comprises one of TiN, HfN, TaN, ZrN, and LaN.
6. A semiconductor device comprising:
a substrate including isolation regions and active regions;
a high-k dielectric layer proximate the substrate, the high-k dielectric layer comprising a mixture formed by annealing at least one high-k material and at least one metal, the annealing to oxidize the metal; and
a gate electrode proximate the high-k dielectric layer,
wherein the high-k dielectric layer comprises HfTaTiOc.
7. The semiconductor device of claim 6, wherein the high-k dielectric layer is incorporated with N.
8. A transistor comprising:
a gate electrode;
a high-k dielectric layer proximate the gate electrode, the high-k dielectric layer comprising a mixture formed by annealing a high-k material and a metal, the annealing to oxidize the metal; and
a substrate comprising an active region, the substrate proximate the high-k dielectric layer,
wherein the high-k dielectric layer has a k value greater than 30.
9. The transistor of claim 8, wherein the high-k material comprises one of Si3N4, Al2O3, Ta2O5, HfO2, TiO2, HfSiOx, ZrO2, ZrSiOx, La2O3, CeO2, Bi4Si2O12, WO3, Y2O3, LaAlO3, BST, PST, PZN, PZT, and PMN.
10. The transistor of claim 9, wherein the metal comprises one of TiN, HfN, TaN, ZrN, and LaN.
11. The transistor of claim 8, wherein the gate electrode comprises one of aluminum, polysilicon, TiN, TaN, HfN, RuN, WN, W, MoN, TaSiN, RuSiN, WSiN, HfSiN, and TiSiN.
12. A transistor comprising:
a gate electrode;
a high-k dielectric layer proximate the gate electrode, the high-k dielectric layer comprising a mixture formed by annealing a high-k material and a metal, the annealing to oxidize the metal; and
a substrate comprising an active region, the substrate proximate the high-k dielectric layer,
wherein the high-k dielectric layer comprises HfTaTiOx.
13. The transistor of claim 12, wherein the high-k dielectric layer is incorporated with N.
14. The transistor of claim 8, wherein the transistor is an NMOS transistor.
15. The transistor of claim 8, wherein the transistor is a PMOS transistor.
16. A semiconductor device comprising:
a substrate including isolation regions and active regions;
a high-k dielectric layer proximate the substrate, the high-k dielectric layer having a first k value and comprising a mixture formed by annealing at least a first layer of material having a second k value and a second layer of material having a third k value, the first k value greater than the second k value and the third k value; and
a gate electrode proximate the high-k dielectric layer,
wherein the first k value is greater than 30.
17. The semiconductor device of claim 16, wherein the first layer of material comprises a high-k material and the second layer of material comprises a metal.
18. The semiconductor device of claim 16, wherein the first layer of material comprises a high-k material and the second layer of material comprises a material that acts as a metal.
19. The semiconductor device of claim 16, wherein the high-k dielectric layer is incorporated with N.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An organic light emitting diode (OLED) display comprising:
a substrate;
a thin film transistor on the substrate;
a first insulation layer on the thin film transistor;
a second insulation layer on the first insulation layer, the second insulation layer having a first opening exposing a portion of the first insulation layer;
a first electrode electrically connected with the thin film transistor and contacting the second insulation layer and contacting the first insulation layer through the first opening;
a pixel defining layer disposed on the first electrode and having a second opening exposing a portion of the first electrode in a region corresponding to the first opening, the second opening being smaller than the first opening, wherein the pixel defining layer comprises a plurality of inclined surfaces forming the second opening;
an organic emission layer on the first electrode in a region corresponding to the second opening, the organic emission layer covering at least one of the plurality of inclined surfaces of the pixel defining layer; and
a second electrode on the organic emission layer in a region corresponding to the second opening.
2. The OLED display of claim 1, wherein at least one of the organic emission layer and the second electrode is disposed on fewer than all of the plurality of inclined surfaces.
3. The OLED display of claim 1, wherein the first electrode is a light reflective electrode and the second electrode is a light transmissive electrode.
4. The OLED display of claim 1, wherein the organic emission layer has a refractive index that is different from the refractive indexes of the first electrode, the pixel defining layer, and the second electrode.
5. The OLED display of claim 1, wherein the second opening is in a shape of a flat quadrangle, and
wherein the pixel defining layer forms the second opening and further comprises:
first and second inclined surfaces that are disposed opposite to each other; and
third and fourth inclined surfaces that are disposed opposite to each other.
6. The OLED display of claim 5, wherein the third inclined surface connects first ends of the first and second inclined surfaces, and the fourth inclined surface connects second ends of the first and second inclined surfaces.
7. The OLED display of claim 5, wherein the first and second inclined surfaces are longer than the third and fourth inclined surfaces.
8. The OLED display of claim 5, wherein the organic emission layer and the second electrode are disposed only on the third and fourth inclined surfaces among the first, second, third, and fourth inclined surfaces.
9. The OLED display of claim 5, wherein the second electrode is disposed only on the third and fourth inclined surfaces among the first, second, third, and fourth inclined surfaces.
10. The OLED display of claim 9, wherein the organic emission layer is disposed on the first, second, third, and fourth inclined surfaces.
11. The OLED display of claim 5, wherein the organic emission layer is disposed only on the third and fourth inclined surfaces among the first, second, third, and fourth inclined surfaces.
12. The OLED display of claim 11, wherein the second electrode is disposed on the first, second, third, and fourth inclined surfaces.