Author: claimsbot

1. A machine implemented method at a debug host device, the method comprising:
accessing, via a hardware integrated debug framework, data in volatile random access memory of a debug target device;
accessing, via the hardware integrated debug framework, data in nonvolatile random access electrically erasable semiconductor memory of the debug target device;
accessing, via the hardware integrated debug framework, one or more registers of one or more processors on the debug target device; and
creating, on the debug host device, a debug target system snapshot comprising the volatile memory data, nonvolatile memory data, and data from one or more registers of one or more processors on the debug target device, wherein the debug target device has malfunctioned due to a failure.
2. The machine implemented method as in claim, 1 wherein accessing data in volatile memory of a debug target device comprises:
accessing, through an external debug interface, the hardware integrated debug framework;
copying, via the hardware integrated debug framework, one or more page tables on one or more processors from the debug target device to the debug host device, through the external debug interface;
accessing one or more physical memory addresses on the debug target device using virtual memory mappings listed in one or more page tables copied from one or more processors on the debug target device; and
copying, to the debug host device, one or more blocks of memory stored at the one or more physical memory addresses on the debug target device.
3. The machine implemented method as in claim 2, wherein the hardware integrated debug framework is accessed through an external debug interface by a hardware debug device coupled to the external debug interface and the debug host device, and wherein the accessing occurs by the debug host device pulling the data from the debug target device.
4. The machine implemented method as in claim 1, wherein accessing data in nonvolatile electronically erasable semiconductor memory on a debug target device comprises:
accessing, via the hardware integrated debug framework, the input and output pins of the electrically erasable semiconductor memory;
accessing, via the input and output pins of the electrically erasable semiconductor memory, one or more stored data blocks; and
copying, through the external debug interface, one or more data blocks from the electrically erasable semiconductor memory to the debug host device.
5. The machine implemented method as in claim 4, wherein the input and output pins of the electrically erasable semiconductor memory device are accessed via a general-purpose input-output controller using the command protocol of the semiconductor memory device.
6. The machine implemented method as in claim 5, wherein the general-purpose input-output controller is commanded by a memory controller device programmed with the command protocol of the electrically erasable semiconductor memory.
7. The machine implemented method as in claim 6, wherein the memory controller device for the electronically erasable semiconductor memory is controlled by a direct memory access controller, wherein the direct memory access controller is controlled via the hardware integrated debug framework.
8. A machine implemented method at a debug host device, the method comprising:
accessing, through an external debug interface on a debug target device, a hardware integrated debug framework of a system on a chip integrated circuit;
copying, via the hardware integrated debug framework, a page table on one or more processors from the debug target device, to the debug host device, through the external debug interface;
analyzing the page table entries to determine the subset of page mapped virtual addresses that contain kernel memory allocations;
accessing, via the debug framework, one or more physical memory addresses containing kernel memory allocations on the debug target device; and
copying, through the debug interface, one or more blocks of memory stored at the one or more physical memory addresses on the debug target device.
9. The machine implemented method as in claim 8, wherein analyzing the page table entries to determine the subset of page mapped virtual addresses that contain kernel memory allocations comprises applying an algorithm to the set of page mapped virtual addresses to find a pattern of mappings that indicate one or more kernel memory allocations.
10. The machine implemented method as in claim 8, wherein analyzing the page table entries to determine the subset of page mapped virtual addresses that contain kernel memory allocations further comprises reading a bit in the page table entry data structure.
11. A non-transitory machine-readable storage medium having instructions stored therein, which when executed by a machine cause the machine to perform operations, the operations comprising:
accessing data in the volatile random access system memory of a debug target device via a hardware integrated debug framework;
accessing data on a nonvolatile random access electrically erasable semiconductor memory device of the debug target device via the hardware integrated debug framework;
accessing one or more registers of one or more processors on the debug target device; and
creating a debug target system snapshot on a debug host device, the debug target system snapshot comprising at least the system memory data, the nonvolatile memory data, and the data from one or more registers of one or more processors on the debug target device, wherein the debug target device has malfunctioned due to a failure.
12. The machine-readable storage of claim 11, wherein accessing data in system memory of a debug target device comprises:
accessing the hardware integrated debug framework through an external debug interface;
copying, to the debug host device, one or more page tables from on one or more processors on the debug target device using the hardware integrated debug framework;
accessing one or more physical memory addresses on the debug target device using virtual memory mappings listed in one or more page tables copied from one or more processors on the debug target device; and
copying, to the debug host device, one or more blocks of memory stored at the one or more physical system memory addresses on the debug target device.
13. The machine-readable storage of claim 11, wherein accessing data in nonvolatile electrically erasable semiconductor memory on a debug target device comprises:
accessing, via the hardware integrated debug framework, the input and output pins of the electrically erasable semiconductor memory;
reading one or more data blocks from the electrically erasable semiconductor memory using a command protocol specific to the electrically erasable semiconductor memory device; and
copying, through the debug interface, one or more blocks of data stored on the electrically erasable semiconductor memory of the debug target device, to the debug host device, using the command protocol of the electrically erasable semiconductor memory device.
14. The machine readable storage of claim 13, wherein the input and output pins of the nonvolatile electronically erasable semiconductor memory device are driven via a general purpose input-output controller, which is controlled via the hardware integrated debug framework.
15. The machine readable storage of claim 14, wherein the general purpose input-output controller is commanded by a memory controller device specific to the nonvolatile electronically erasable semiconductor memory, and wherein the memory controller device is controlled by a hardware debugger using the hardware integrated debug framework.
16. The machine readable storage of claim 15, wherein the memory controller device for the electronically erasable semiconductor memory is controlled by a direct memory access controller, wherein the direct memory access controller is controlled via the hardware integrated debug framework.
17. A non-transitory machine-readable storage medium having instructions stored therein, which when executed by a machine cause the machine to perform operations, the operations comprising:
accessing, through an external debug interface, a hardware integrated debug framework;
copying, via the hardware integrated debug framework, a page table on one or more processors from the debug target device to the debug host device, through the external debug interface;
analyzing the page table entries to determine the subset of page mapped virtual addresses that contain kernel memory allocations by applying an algorithm to the set of page mapped virtual addresses, the algorithm comprising analyzing the set of page mapped virtual addresses to find a pattern of mappings, the pattern of mappings to indicate the presence of one or more kernel memory allocations.
accessing, via the debug framework, one or more physical memory addresses containing kernel memory allocations on the debug target device; and
copying, through the debug interface, one or more blocks of memory stored at the one or more physical memory addresses on the debug target device.
18. The machine readable storage of claim 17, wherein analyzing the page table entries to determine the subset of page mapped virtual addresses that contain kernel memory allocations further comprises reading a bit in the page table entry data structure.
19. A debugging system for embedded devices, the system comprising:
a debug host device comprising one or more processors, a main system memory, and a nonvolatile storage device;
a hardware debug device coupled with the debug host device, the hardware debug device to provide a debug interface between a debug host device and one or more debug target devices;
a debug target device comprising a system on a chip integrated circuit, volatile DRAM memory, and nonvolatile electrically erasable semiconductor memory, wherein the system on a chip integrated circuit comprises one or more processors and a hardware integrated debug framework, the hardware integrated debug framework to allow the hardware debug device and debug host device to control the one or more processors of the system on a chip integrated circuit after the debug target device malfunctions due to an operating system level failure; and
a debug console, attached to the debug host device, to monitor debug output from the debug target device.
20. The system as in claim 19, wherein the debug target device further comprises a general purpose input-output controller, to control the input and output pins of the nonvolatile electronically erasable semiconductor memory device.
21. The system as in claim 20, wherein the debug host device is coupled to the debug target device through at least one network.
22. The system as in claim 20, wherein the general-purpose input-output controller is controlled by a semiconductor memory controller device, the semiconductor memory device controlled via the hardware integrated debug framework.
23. The system as in claim 22, wherein the semiconductor memory controller device is controlled by a direct memory access controller, the direct memory access controller controlled by the debug host device via the hardware integrated debug framework.
24. The system as in claim 23, wherein the debug host device uses a device driver stored in system memory to control hardware on the debug target device via the hardware integrated debug framework.
25. The system as in claim 23, wherein a software simulation of one or more hardware components on the debug target device substitutes for one or more components of the debug target device.
26. The system as in claim 23, wherein external hardware that duplicates the functionality of one or more internal hardware components of the debug target device substitutes for one or more components of the debug target device.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of identifying a connection error when a first module is electrically connected to a plurality of second modules, said method comprising the steps of:
distinguishing said second modules connected to said first module;
determining whether said distinguished second modules are preliminarily registered or not; and
judging that there is a connection error if said distinguished second modules are not preliminarily registered;
wherein each of said steps is carried out by one of the modules selected from the group consisting of said first module and said plurality of second modules.
2. The method of claim 1 wherein said first module has a plurality of connectors, each of said second modules being mounted to a corresponding different one of said connectors, wherein said second modules are preliminarily registered for each of said connectors, and wherein said step of judging comprises judging for each of said connectors whether said distinguished second module is not preliminarily registered.
3. The method of claim 2 wherein a plurality of second modules are preliminarily registered as a combination corresponding to a plurality of said connectors and wherein said step of judging comprises judging whether or not the distinguished second modules are preliminarily registered as said combination.
4. The method of claim 1 wherein said step of judging comprises judging a connection error also if a module cannot be distinguished in said step of distinguishing.
5. The method of claim 1 further comprising the step of making a report when it is judged in said step of judging that there is a connection error.
6. An electronic apparatus comprising:
a first module having a plurality of connectors;
a plurality of second modules each connected to said first module through a different one of said connectors;
a registration part where a plurality of types of second modules are preliminarily registered;
a distinguishing part for distinguishing second modules connected to said connectors;
a determining part for determining whether the distinguished second modules are of a type preliminarily registered in said registration part; and
a judging part for judging that there is a connection error of said second module if said distinguished second modules are determined to be not registered in said registration part.
7. The electronic apparatus of claim 6 wherein said types of second modules are registered corresponding to each of said connectors and wherein said determining part determines whether the distinguished second modules are each of a type preliminarily registered corresponding to each of said connectors.
8. The electronic apparatus of claim 7 wherein said types of second modules are preliminarily registered in said registration part as combinations corresponding to said connectors and said determining part determines whether or not the distinguished second modules are preliminarily registered as one of said combinations.
9. The electronic apparatus of claim 6 wherein said judging part judges that there is a connection error also when said distinguishing part fails to distinguish said second module.
10. The electronic apparatus of claim 6 further comprising a reporting part for making a report when said judging part judges that there is a connection error.
11. The electronic apparatus of claim 6 further comprising a limiting part that limits at least a portion of operations by said electronic apparatus when said judging part judges that there is connection error.
12. The electronic apparatus of claim 6 wherein said first module comprises a base substrate having common wiring that is connected to each of said connectors, said second modules each comprising a mounting substrate having a dedicated circuit corresponding to a specified function, said dedicated circuit becoming connected to said common wiring as said mounting substrate is connected to said connector, said second modules each further comprising a control circuit which is mounted either to said base substrate or to said mounting board and is connected to said common wiring, said control circuit including at least said distinguishing part, said determining part and said judging part, said control circuit serving to identify said mounting board connected to said connector of said base substrate and to function accordingly as a specified one of a plurality of types of apparatus.

1. An apparatus comprising:
a multiplexed bus interface to interface with a multiplexed bus;
a cache control circuit to drive a row address portion of an address on said multiplexed bus interface and a command to open a memory page containing data for a plurality of ways, said cache control circuit to drive a column address portion on said multiplexed bus interface subsequent to said row address portion, said column address portion comprising a way indicator and a most critical chunk indicator to indicate a sub-portion of a requested cache line to be returned first.
2. The apparatus of claim 1 wherein said row address portion is to specify a bank number and a row to open the memory page, wherein each one of a plurality of banks contains data for said plurality of ways.
3. The apparatus of claim 1 wherein said row address is to specify a single row in a single bank memory array, wherein said single bank memory array is to contain data for each of said plurality of ways.
4. The apparatus of claim 3 wherein said row address is also to specify a single row in a second single bank memory array, wherein said second single bank memory array is also to contain data for each of said plurality of ways, and wherein both said single bank memory array and said second single bank memory array are configured to return data in response to said command.
5. The apparatus of claim 1 wherein said column address portion is to specify a bank number, wherein said bank number maps to one of said plurality of ways.
6. The apparatus of claim 1 wherein said multiplexed bus is an address and command bus and further comprising a data bus interface to receive data returned in response to said command, said row address portion, and said column address portion.
7. The apparatus of claim 6 further comprising: address translation logic to generate the address; a tag memory to lookup a tag portion of said address and to generate said way indicator if a hit occurs.
8. The apparatus of claim 7 further comprising a memory array coupled to said multiplexed bus, and a first data bus coupling said cache data bus interface to said memory array.
9. The apparatus of claim 8 further comprising a main memory to return data associated with said address if said tag memory indicates a miss.
10. The apparatus of claim 8 further comprising a second memory array, a second data bus, and a second data bus interface, wherein said command, said row address portion, and said column address portion are send to both said memory array and said second memory array, and wherein said memory array returns a first portion of data to satisfy said command and said second memory array returns second portion of data to satisfy said command.
11. The apparatus of claim 1, wherein said apparatus is in the form of a machine readable medium.
12. An apparatus comprising:
a memory array;
a cache control circuit to initiate transmission of a first address portion of an address including a plurality of translated bits, to said memory array to open a memory page containing data for a plurality of ways prior to determining a second address portion by performing a tag lookup on a tag portion of said address, the second address portion comprising a most critical chunk indicator, and wherein the memory array is to return a portion of a cache line indicated by the most critical chunk indicator first.
13. The apparatus of claim 12 further comprising a multiplexed address and command bus coupling said cache control circuit to said memory array, wherein said cache control logic is to transmit said second address portion to said memory array on said multiplexed address bus after said first address portion is transmitted with a command to open said memory page on said multiplexed bus to said memory array.
14. The apparatus of claim 13 further comprising: a processor portion that includes said cache control circuit, a processor core, a first level cache, and a tag array to perform said Lookup; a data bus coupling said memory array to said processor portion, said data bus to return data from said memory array to said processor portion.
15. The apparatus of claim 12 wherein said first address portion is a row address portion and wherein said second address portion is a column address portion.
16. The apparatus of claim 15 wherein said column address portion comprises way Information from said tag lookup.
17. The apparatus of claim 16 wherein said memory array comprises a bank, said bank to contain data for each of a plurality of cache ways.
18. The apparatus of claim 16 wherein said memory array comprises a plurality of banks, wherein each of said plurality of banks is to contain data for each of a plurality of cache ways.
19. The apparatus of claim 16 wherein said memory array comprises a plurality of banks and each bank maps to a cache way.
20. The apparatus of claim 19 wherein said memory array further comprises a selector and wherein each bank is enabled in response to said row address portion to read out a page of data to the selector, and wherein said selector selects a hit way based on said tag lookup.
21. The apparatus of claim 16 wherein said memory array comprises a plurality of banks, wherein a selected one of said plurality of banks is to be enabled according to a portion of said row address, and further wherein each of said plurality of banks is to contain data for a plurality of cache ways, wherein a hit way of said plurality of cache ways is to be selected according to said column address.
22. The apparatus of claim 12 wherein said cache control circuit is to generate an auto-precharge command if the tag lookup indicates a cache miss.
23. The apparatus of claim 12 wherein said cache control circuit is to specify a column address but ignore returned data if the tag lockup indicates a cache miss.
24. The apparatus of claim 12 wherein said cache control circuit is to initiate the opening of a memory page in response to said first address portion prior to determining if a cache hit occurs.
25. The apparatus of claim 12 wherein said cache control circuit is to request opening of a page in said memory array designated by said first address portion regardless of presence or absence of data cached at said address in said memory array.
26. The apparatus of claim 14 wherein said memory array comprises a plurality of single transistor memory cells.
27. The apparatus of claim 26 wherein said apparatus is a processing system that further comprises a main memory to store data not found cached in said memory array.
28. The apparatus of claim 27 wherein said processing system is a server computer system.
29. A processor comprising:
a processor core to generate a memory request requesting a memory location specified by an address;
address translation logic to generate a translated address corresponding to said memory location;
a first level cache to provide data for said memory location if said first level cache caches said memory location;
a higher level cache comprising:
a memory array;
a multiplexed address and command bus;
a data bus;
a tag array;
a cache control circuit coupled to said memory array by said multiplexed address and command bus and by said data bus, said cache control circuit to transmit on said multiplexed address and command bus a command a row address portion of said translated address to said memory array in response to said memory request regardless of whether said memory array caches a memory location associated with said translated address, and prior to transmitting a column address portion determined by performing a tag lookup in said tag array on a tag portion of said translated address, said cache control circuit to transmit said column address portion comprising a way indication, the cache control circuit to transmit a most critical chunk indicator on said multiplexed address and command bus, wherein said memory array is to return a most critical chunk indicated by said most critical chunk indicator to said cache controller first.
30. The processor of claim 29 wherein said row address portion is to specify a bank number and a row to open a memory page in the memory array, wherein each one of a plurality of banks contains data for a plurality of ways.
31. The apparatus of claim 29 wherein the memory array is a single bank memory array and wherein said row address is to specify a single row in the single bank memory array, wherein said single bank memory array is to contain data for each of said plurality of ways.
32. The apparatus of claim 29 wherein said column address portion is to specify a bank number, wherein said bank number maps to one of a plurality of ways.
33. A method comprising:
driving a row address indicative of a first address portion to open a page to start a cache read;
driving a way indicator as at least a portion of a column address if a hit is detected, wherein the column address comprises a most critical chunk indicator;
aborting the cache read if a miss is detected.
34. The method of claim 33 wherein aborting comprises driving a pre-charge command if a miss is detected.
35. The method of claim 33 wherein aborting comprises: driving a bogus way even if a miss occurs; ignoring data returned.
36. A method comprising:
generating an activate command and a row address on a multiplexed address and command bus during a first clock cycle;
performing a tag lookup to determine a way indicator;
generating a read command and a column address containing a way indicator on said multiplexed address and command bus in a subsequent clock cycle;
generating a most critical chunk indicator on the multiplexed address and command bus.
37. The method of claim 36 further comprising: generating a bogus way number as said way indicator in response to said tag lookup generating a miss.
38. The method of claim 36 wherein said row address comprises a bank number and a row Indicator.
39. The method of claim 36 wherein said column address comprises a bank number.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for controlling a global navigation satellite system (GNSS) receiver, wherein the GNSS receiver is operated in a first operation state, comprising:
providing a state switching criterion;
obtaining at least one positioning information;
determining whether to switch from the first operation state to a second operation state according to the obtained positioning information and the state switching criterion, wherein a power consumption of the GNSS receiver operating under the first operation state and the second operation state is different.
2. The method of claim 1, wherein the obtained positioning information includes a speed value of the GNSS receiver and the state switching criterion includes a first predetermined threshold value, wherein the determining step determines to switch from the first operation state to the second operation state when the speed value of the GNSS receiver is lower than the first predetermined threshold value.
3. The method of claim 2, wherein the speed value is one of a current speed value of the GNSS receiver and a resultant speed value that is recorded and calculated during a past time period.
4. The method of claim 1, wherein the obtained positioning information includes a speed value of the GNSS receiver and the state switching criterion includes a second predetermined threshold value, wherein the determining step determines to switch from the first operation state to the second operation state when the speed value of the GNSS receiver is higher than the second predetermined threshold value.
5. The method of claim 1, wherein the obtained positioning information includes a satellite distribution value of the GNSS receiver and the state switching criterion includes a third predetermined threshold value, wherein the determining step determines to switch from the first operation state to the second operation state when the satellite distribution value of the GNSS receiver is lower than the third predetermined threshold value.
6. The method of claim 1, wherein the obtained positioning information includes a satellite distribution value of the GNSS receiver and the state switching criterion includes a fourth predetermined threshold value, wherein the determining step determines to switch from one of the first and second operation states to a third operation state when the satellite distribution value of the GNSS receiver is lower than the fourth predetermined threshold value.
7. The method of claim 1, wherein the obtained positioning information includes a satellite signal strength value of the GNSS receiver and the state switching criterion includes a fifth predetermined threshold value, wherein the determining step determines to switch from the first operation state to the second operation state when the satellite signal strength value of the GNSS receiver is higher than the fifth predetermined threshold value.
8. The method of claim 1, wherein the obtained positioning information includes a satellite signal strength value of the GNSS receiver and the state switching criterion includes a sixth predetermined threshold value, wherein the determining step determines to switch from the first operation state to the second operation state when the satellite signal strength value of the GNSS receiver is lower than the sixth predetermined threshold value.
9. The method of claim 1, wherein the obtained positioning information includes a location identification of the GNSS receiver and the state switching criterion includes a predetermined location identification, wherein the determining step determines to switch from the first operation state to the second operation state when the obtained location identification of the GNSS receiver is substantially the same as the predetermined location identification.
10. The method of claim 1, further comprising:
reducing a power consumption of the GNSS receiver by disabling the GNSS receiver.
11. The method of claim 1, wherein the GNSS receiver includes a radio-frequency (RF) front-end circuit, an acquisition circuit and a tracking circuit, the method further comprising:
adjusting a power consumption of at least one of the RF front-end circuit, the acquisition circuit and the tracking circuit.
12. The method of claim 11, wherein the step of adjusting the power consumption comprises:
turning off power of the GNSS receiver.
13. The method of claim 11, wherein the adjusting step comprising:
adjusting a working period of one satellite information collection performed by the at least one circuit.
14. The method of claim 11, wherein the adjusting step comprising:
adjusting an interval between two satellite information collections performed by the at least one circuit.
15. The method of claim 11, wherein the adjusting step comprising:
adjusting a number of acquisition channels used for searching for information of satellites.
16. The method of claim 11, wherein the adjusting step comprising:
adjusting a number of tracking channels used for tracking satellites.
17. A global navigation satellite system (GNSS) receiver, wherein the GNSS receiver is operated in a first operation state, comprising:
a memory for providing a state switching criterion;
a positioning unit for obtaining a positioning information;
a controlling unit for determining whether to switch from the first operation state to a second operation state according to the obtained positioning information and the state switching criterion, wherein a power consumption of the GNSS receiver operating under the first operation state and the second operation state is different.
18. The GNSS receiver of claim 17, wherein the obtained positioning information includes a speed value of the GNSS receiver and the state switching criterion includes a first predetermined threshold value, wherein the controlling unit determines to switch from the first operation state to the second operation state when the speed value of the GNSS receiver is lower than the first predetermined threshold value.
19. The GNSS receiver of claim 18, wherein the positioning unit is arranged to record a current speed value of the GNSS receiver as the speed value or to record and calculate a resultant speed value during a past time period.
20. The GNSS receiver of claim 17, wherein the obtained positioning information includes a speed value of the GNSS receiver and the state switching criterion includes a second predetermined threshold value, wherein the controlling unit determines to switch from the first operation state to the second operation state when the speed value of the GNSS receiver is higher than the second predetermined threshold value.
21. The GNSS receiver of claim 17, wherein the obtained positioning information includes a satellite distribution value of the GNSS receiver and the state switching criterion includes a third predetermined threshold value, wherein the controlling unit determines to switch from the first operation state to the second operation state when the satellite distribution value of the GNSS receiver is lower than the third predetermined threshold value.
22. The GNSS receiver of claim 17, wherein the obtained positioning information includes a satellite distribution value of the GNSS receiver and the state switching criterion includes a fourth predetermined threshold value, wherein the controlling unit determines to switch from one of the first and second operation states to a third operation state when the satellite distribution value of the GNSS receiver is lower than the fourth predetermined threshold value.
23. The GNSS receiver of claim 17, wherein the obtained positioning information includes a satellite signal strength value of the GNSS receiver and the state switching criterion includes a fifth predetermined threshold value, wherein the controlling unit determines to switch from the first operation state to the second operation state when the satellite signal strength value of the GNSS receiver is higher than the fifth predetermined threshold value.
24. The GNSS receiver of claim 17, wherein the obtained positioning information includes a satellite signal strength value of the GNSS receiver and the state switching criterion includes a sixth predetermined threshold value, wherein the controlling unit determines to switch from the first operation state to the second operation state when the satellite signal strength value of the GNSS receiver is lower than the sixth predetermined threshold value.
25. The GNSS receiver of claim 17, wherein the obtained positioning information includes a location identification of the GNSS receiver and the state switching criterion includes a predetermined location identification, wherein the determining step determines to switch from the first operation state to the second operation state when the obtained location identification of the GNSS receiver is substantially the same as the predetermined location identification.
26. The GNSS receiver of claim 17, wherein power consumption of the GNSS receiver is reduced by disabling an operation of the GNSS receiver.
27. The GNSS receiver of claim 17, wherein the GNSS receiver includes a radio-frequency (RF) front-end circuit, an acquisition circuit and a tracking circuit, wherein a power consumption of at least one of the RF front-end circuit, the acquisition circuit and the tracking circuit is adjusted.
28. The GNSS receiver of claim 27, wherein power of the GNSS receiver is turned off when the power consumption is adjusted.
29. The GNSS receiver of claim 27, wherein a working period of one satellite information collection performed by the at least one of the RF front-end circuit, the acquisition circuit and the tracking circuit is adjusted.
30. The GNSS receiver of claim 27, wherein an interval between two satellite information collections performed by the at least one of the RF front-end circuit, the acquisition circuit and the tracking circuit is adjusted.
31. The GNSS receiver of claim 27, wherein a number of acquisition channels used for searching for information of satellites are adjusted.
32. The GNSS receiver of claim 27, wherein a number of tracking channels used for tracking satellites is adjusted.