Author: claimsbot

1. A process for making a block of cheese having reduced moisture variability, said process comprising providing a bulk container having a bottom and sidewalls; introducing cheese curd having an initial temperature of about 60 to 90\xb0 F. into the container to form a cheese curd block; pressing the cheese curd block to form a cheese block; controlled cooling of the cheese block to a final temperature of less than 45\xb0 F. over a total period of about 7 to about 13 days to form a final cheese block, wherein the controlled cooling is effective to provide a reduced moisture content variation between a geometric center and side edges of the final cheese block as compared to a similar cheese block cooled directly to 45\xb0 F. over the total period; wherein the final cheese block has a weight of at least about 500 pounds; wherein the controlled cooling comprises first cooling the cheese block at an intermediate temperature of about 10 to about 40\xb0 F. below the initial temperature and at least about 10\xb0 F. above the final temperature for a first cooling period of about 2 to about 5 days and then cooling the cheese block at the final temperature of less than about 45\xb0 F. for a second cooling period of about 5 to 7 days; and wherein the first and the second cooling periods are sufficient to cool the final cheese block to less than about 45\xb0 F.
2. The process of claim 1, wherein the initial temperature is about 60 to about 90\xb0 F., wherein the intermediate temperature is about 15 to about 25\xb0 F. below the initial temperature, and wherein the first cooling period is about 3 to about 4 days.
3. The process of claim 2, wherein the intermediate temperature is at least about 20\xb0 F. above the final temperature.
4. The process of claim 1, wherein the cheese block has a diameter of about 24 to about 30 inches, and the cheese block has a moisture content variation of no greater than 2.0 percent between a location at a geometric center thereof and a side edge portion.
5. The process of claim 4, wherein the moisture content variation is no more than 1.0 percent between the location at the geometric center and the side edge portion thereof.
6. The process of claim 4, wherein the moisture content variation is no more than 0.5 percent between the location at the geometric center and the side edge portion thereof.
7. The process of claim 2, wherein the cheese block has a diameter of about 24 to about 30 inches, and the cheese block has a moisture content variation of no greater than 2.0 percent between a location at a geometric center thereof and a side edge portion.
8. The process of claim 7, wherein the moisture content variation is no more than 1.0 percent between the location at the geometric center and the side edge portion thereof.
9. The process of claim 7, wherein the moisture content variation is no more than 0.5 percent between the location at the geometric center and the side edge portion thereof.
10. The process of claim 1, wherein the final cheese block has a substantially symmetrical cross-sectional shape selected from the group consisting of square, rectangular, triangular, and circular and wherein the final cheese block is a cheese selected from the group consisting of Cheddar, Monterey Jack, and Colby.
11. The process of claim 2, wherein the final cheese block has a substantially symmetrical cross-sectional shape selected from the group consisting of square, rectangular, triangular, and circular and wherein the final cheese block is a cheese selected from the group consisting of Cheddar, Monterey Jack, and Colby.
12. A cheese block having a moisture content variation of no greater than 2.0 percent between a location at a geometric center and a side edge portion thereof, wherein the cheese block is prepared by controlled cooling of a block of cheese curd to a final temperature of less than 45\xb0 F. over a total period of about 7 to about 13 days; wherein the cheese block has a weight of at least about 500 pounds; wherein the controlled cooling comprises first cooling the cheese block at an intermediate temperature of about 10 to about 40\xb0 F. below the initial temperature and at least about 10\xb0 F. above the final temperature for a first cooling period of about 2 to about 5 days and then cooling the cheese block at the final temperature of less than about 45\xb0 F. for a second cooling period of about 5 to 7 days; and wherein the first and the second cooling periods are sufficient to cool the final cheese block to less than about 45\xb0 F.
13. The cheese block of claim 10, wherein the moisture content variation is no more than 1.0 percent between the location at the geometric center and the side edge portion thereof.
14. The cheese block of claim 10, wherein the moisture content variation is no more than 0.5 percent between the location at the geometric center and the side edge portion thereof.
15. The cheese block of claim 10, wherein the cheese block has a substantially symmetrical cross-sectional shape selected from the group consisting of square, rectangular, triangular, and circular and wherein the cheese block is a cheese selected from the group consisting of Cheddar, Monterey Jack, and Colby.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An integrated circuit comprising:
a processor comprising:
a floating-point arithmetic logic unit (ALU) comprising input checkoutput correction floating-point division logic responsive to a floating-point division fix-up instruction executable by the floating-point ALU that causes the input checkoutput correction floating-point division logic to:
examine a first input representing a numerator and a second input representing a denominator of the input checkoutput correction floating-point division logic to determine whether a special case of floating-point division occurs; and
provide an output representing a floating-point division result of the input checkoutput correction floating-point division logic based on the determined special case of floating-point division and a third input representing a candidate quotient of the input checkoutput correction floating-point division logic.
2. The integrated circuit of claim 1, wherein the input checkoutput correction floating-point division logic comprises:
a plurality of special case test circuits operative to examine the first input representing the numerator and the second input representing the denominator of the input checkoutput correction floating-point division logic to determine whether the special case of floating-point division occurs; and
a priority multiplexer operative to provide the output representing the floating-point division result of the input checkoutput correction floating-point division logic based on the determined special case of floating-point division and the third input representing the candidate quotient of the input checkoutput correction floating-point division logic; and
wherein the processor further comprises a plurality of registers, operatively connected to the input checkoutput correction floating-point division logic, operative to store the numerator, the denominator, the candidate quotient, and the floating-point division result.
3. The integrated circuit of claim 1, wherein the floating-point division fix-up instruction is a single instruction that is executed in one clock cycle.
4. The integrated circuit of claim 1, wherein the floating-point division fix-up instruction is comprised of an input check instruction and an output correction instruction; and wherein each one of the input check instruction and output correction instruction is executed in one clock cycle.
5. The integrated circuit of claim 2, wherein the floating-point ALU further comprises at least one floating-point addersubtractor and at least one floating-point multiplier; and
wherein the at least one floating-point addersubtractor and floating-point multiplier are responsive to a plurality of instructions executable by the floating-point ALU that causes the at least one floating-point addersubtractor and floating-point multiplier to numerically calculate the candidate quotient based on the numerator and the denominator without regard to the special case of floating-point division.
6. The integrated circuit of claim 5, wherein the input checkoutput correction floating-point division logic is further responsive to the floating-point division fix-up instruction executable by the floating-point ALU that causes the input checkoutput correction floating-point division logic to, if the special case of floating-point division does not occur, provide the candidate quotient as the output representing the floating-point division result of the input checkoutput correction floating-point division logic.
7. The integrated circuit of claim 2, wherein the input checkoutput correction floating-point division logic is further responsive to the floating-point division fix-up instruction executable by the floating-point ALU that causes the input checkoutput correction floating-point division logic to, if the special case of floating-point division occurs, provide a corresponding special value of floating-point division as the output representing the floating-point division result of the input checkoutput correction floating-point division logic.
8. The integrated circuit of claim 7, wherein the plurality of special case test circuits comprise:
a not-a-number (NaN) test circuit operative to determine whether the numerator or the denominator is NaN;
a zero test circuit operative to determine whether the numerator or the denominator is zero;
an infinity test circuit operative to determine whether the numerator or the denominator is infinity; and
an overflowunderflow test circuit operative to determine whether an overflow or an underflow occurs based on the numerator and the denominator; and
wherein the special value of floating-point division is selected from at least one of NaN, zero, infinity, maximum float constant, and minimum float constant.
9. The integrated circuit of claim 2, wherein the input checkoutput correction floating-point division logic further comprises sign bit setting logic, operatively connected to the priority multiplexer, operative to set a sign bit of the output representing the floating-point division result based on a sign bit of the first input representing the numerator and a sign bit of the second input representing the denominator of the input checkoutput correction floating-point division logic.
10. The integrated circuit of claim 2, wherein the output representing the floating-point division result is a first output of the input checkoutput correction floating-point division logic; and
wherein the input checkoutput correction floating-point division logic further comprises exception flag logic operative to:
determine an exception status flag based on the first input representing the numerator and the second input representing the denominator of the input checkoutput correction floating-point division logic; and
provide a second output representing the exception status flag of the input checkoutput correction floating-point division logic.
11. The integrated circuit of claim 2, wherein the input checkoutput correction floating-point division logic further comprises an arbitrary bit pattern encoder operative to:
encode an arbitrary bit pattern indicating whether the special case of floating-point division occurs; and
store the arbitrary bit pattern into one of the plurality of registers.
12. The integrated circuit of claim 1, wherein the input checkoutput correction floating-point division logic is part of a graphic processing unit (GPU).
13. The integrated circuit of claim 1, wherein the processor is operative to generate at least a portion of an image based on the output representing the floating-point division result of the input checkoutput correction floating-point division logic.
14. A method comprising:
processing a floating-point division fix-up instruction; and
based on the processed floating-point division fix-up instruction, causing input checkoutput correction floating-point division logic to:
examine a first input representing a numerator and a second input representing a denominator of the input checkoutput correction floating-point division logic to determine whether a special case of floating-point division occurs; and
provide an output representing a floating-point division result of the input checkoutput correction floating-point division logic based on the determined special case of floating-point division and a third input representing a candidate quotient of the input checkoutput correction floating-point division logic.
15. The method of claim 14, wherein causing comprises causing the input checkoutput correction floating-point division logic to receive the third input representing the candidate quotient of the input checkoutput correction floating-point division logic, the candidate quotient being numerically calculated based on the numerator and the denominator without regard to the special case of floating-point division.
16. The method of claim 14, wherein the floating-point division fix-up instruction is a single instruction that is executed in one clock cycle.
17. The method of claim 14, wherein the floating-point division fix-up instruction is comprised of an input check instruction and an output correction instruction; and wherein each one of the input check instruction and output correction instruction is executed in one clock cycle.
18. The method of claim 15, wherein causing comprises causing the input checkoutput correction floating-point division logic to, if the special case of floating-point division does not occur, provide the candidate quotient as the output representing the floating-point division result of the input checkoutput correction floating-point division logic.
19. The method of claim 14, wherein causing comprises causing the input checkoutput correction floating-point division logic to, if the special case of floating-point division occurs, provide a corresponding special value of floating-point division as the output representing the floating-point division result of the input checkoutput correction floating-point division logic.
20. The method of claim 14, wherein causing comprises causing the input checkoutput correction floating-point division logic to set a sign bit of the output representing the floating-point division result of the input checkoutput correction floating-point division logic based on a sign bit of the first input representing the numerator and a sign bit of the second input representing the denominator of the input checkoutput correction floating-point division logic.
21. The method of claim 14, wherein the output representing the floating-point division result is a first output of the input checkoutput correction floating-point division logic; and
wherein causing comprises causing the input checkoutput correction floating-point division logic to:
determine an exception status flag based on the first input representing the numerator and the second input representing the denominator of the input checkoutput correction floating-point division logic; and
provide a second output representing the exception status flag of the input checkoutput correction floating-point division logic.
22. The method of claim 14, wherein causing comprises causing the input checkoutput correction floating-point division logic to:
encode an arbitrary bit pattern indicating whether the special case of floating-point division occurs; and
store the arbitrary bit pattern into a register.
23. An apparatus comprising:
a floating-point arithmetic logic unit (ALU) comprising input checkoutput correction floating-point division logic responsive to a floating-point division fix-up instruction executable by the floating-point ALU that causes the input checkoutput correction floating-point division logic to:
examine a first input representing a numerator and a second input representing a denominator of the input checkoutput correction floating-point division logic to determine whether a special case of floating-point division occurs; and
provide an output representing a floating-point division result of the input checkoutput correction floating-point division logic based on the determined special case of floating-point division and a third input representing a candidate quotient of the input checkoutput correction floating-point division logic; and

wherein the apparatus is operative to generate at least a portion of the image based on the output representing the floating-point division result of the input checkoutput correction floating-point division logic.
24. A computer readable medium storing instructions executable by one or more integrated circuit design systems that causes the one or more integrated circuit design systems to design an integrated circuit comprising a processor comprising:
a floating-point arithmetic logic unit (ALU) comprising input checkoutput correction floating-point division logic responsive to a floating-point division fix-up instruction executable by the floating-point ALU that causes the input checkoutput correction floating-point division logic to:
examine a first input representing a numerator and a second input representing a denominator of the input checkoutput correction floating-point division logic to determine whether a special case of floating-point division occurs; and
provide an output representing a floating-point division result of the input checkoutput correction floating-point division logic based on the determined special case of floating-point division and a third input representing a candidate quotient of the input checkoutput correction floating-point division logic.

What is claimed is:

1. A wavelength multiplexing method for use in an optical network that adopts a wavelength multiplexing system comprising the steps of:
driving a semiconductor laser by direct current modulation in response to an input electric signal; and
obtaining at least one signal carrier wavelength by dividing output wavelengths of the multi-mode oscillation semiconductor laser using an optical filter which passes at least one wavelength in said output wavelengths of said semiconductor laser.
2. A wavelength multiplexing method according to claim 1, wherein said wavelength multiplexing method has a function of outputting an optical signal by converting an electric signal introduced into a driving circuit, which is provided for carrying out direct current modulation of said multi-mode oscillation semiconductor laser.
3. A wavelength multiplexing optical transmitter comprising:
a multi-mode oscillation semiconductor laser;
a laser driving circuit for driving said semiconductor laser by an input electric signal; and
an optical filter having at least one passing band in an optical output from said multi-mode oscillation semiconductor laser; wherein at least one or more than one signal carrier wavelength is obtained by filtering the output of said semiconductor laser for slicing the output wavelength region of said semiconductor laser.
4. A wavelength multiplexing optical transmitter according to claim 3, wherein said transmitter has a function of outputting an optical signal by converting the introduced electric signal after the electric signal is subjected to a forward error correction by a forward error correction circuit disposed in front of said laser driving circuit.
5. A wavelength multiplexing optical transmitter according to claim 3, wherein said transmitter outputs an NRZ coded wavelength multiplexing optical signal by use of an NRZ coded electrical signal as the input electric signal
6. A wavelength multiplexing optical transmitter according to claim 3, wherein said transmitter outputs an RZ coded wavelength multiplexing optical signal by use of an RZ coded electrical signal as the input electric signal.
7. A wavelength adjusting apparatus using a wavelength multiplexing optical transmitter according to claim 3, wherein the signal carrier wavelength is changed by changing the transmitting wavelength region of said optical filter.
8. A wavelength adjusting apparatus according to claim 7, wherein said wavelength adjusting apparatus further comprises a laser driving circuit for directly modulating said multi-mode oscillation semiconductor by an electric current and said driving circuit converts the electric signal introduced in said driving circuit into optical signals having more than one signal carrier wavelength, and wherein said driving circuit changes said signal carrier wavelength by changing the transmitting wavelength region of said optical filter.
9. A wavelength adjusting apparatus according to claim 8, wherein said wavelength adjusting apparatus further comprises a forward error correction circuit for applying a correction code to the electric signal introduced into said laser driving circuit, wherein said wavelength adjusting apparatus outputs an optical signal by driving said semiconductor laser after the introduced electric signal is subjected to a forward error correction by said forward error correction circuit.
10. A wavelength adjusting apparatus according to claim 8, wherein said wavelength adjusting apparatus outputs an NRZ coded adjustable wavelength optical signal by introducing the NRZ coded electric signal to said laser driving circuit.
11. A wavelength adjusting apparatus according to claim 9, wherein said wavelength adjusting apparatus outputs an RZ coded adjustable wavelength optical signal by introducing the RZ coded electric signal to said laser driving circuit.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A curtain airbag device, comprising:
a curtain portion provided at a window, the curtain portion being configured so as to be fixed to at least a window side at a portion thereof, accommodated at a peripheral portion of the window in a folded state thereof and cover the window in an inflated state thereof; and
a gas supply device operative to supply gas to an inflatable portion of said curtain portion to inflate said curtain portion in a specified condition,
wherein said curtain portion includes a tip side portion that is located at a tip of a side portion thereof and a tension portion that is located at the side portion thereof away from the tip side portion, said curtain portion in the folded state is accommodated in such a manner that the tip side portion is positioned near a support portion that is provided at a window edge and the tension portion is positioned near said window side to which the curtain portion is fixed, and said curtain portion is configured such that when the curtain portion is inflated with the inflation of the inflatable portion, the tip side portion is moved in an inflation direction and the tension portion is moved to the support portion so as to engage with the support portion,
wherein said curtain portion is configured so as to be fixed to a first window side at a portion thereof and accommodated at the first window side, a second window side and a third window side, the second and third window sides being located at both sides of the first window side, said curtain portion includes a second-window-side tip side portion that is located at a tip of a side portion thereof located at a side of the second window side and a third-window-side tip side portion that is located at a tip of a side portion thereof located at a side of the third window side, and a second-window-side tension portion that is located at the side portion thereof at the side of the second window side away from the second-window-side tip side portion and a third-window-side tension portion that is located at the side portion thereof at the side of the third window side away from the third-window-side tip side portion, said curtain portion in the folded state is accommodated in such a manner that the second-window-side tip side portion is positioned near a second-window-side support portion that is provided at the second window side and the third-window-side tip side portion is positioned near a third-window-side support portion that is provided at the third window side, and the second-window-side tension portion and the third-window-side tension portion are positioned near the first window side, and said curtain portion is configured such that when the curtain portion is inflated with the inflation of the inflatable portion, the second-window-side and third-window-side tip side portions are moved in the inflation direction, respectively, and the second-window-side and third-window-side tension portions are moved to the second-window-side and third-window-side support portions so as to engage with the second-window-side and third-window-side support portions, respectively.
2. The curtain airbag device of claim 1, wherein an angle formed between said window side to which the curtain portion is fixed and an adjacent window side is configured to be obtuse.
3. The curtain airbag device of claim 1, wherein said tip side portion and said tension portion are interconnected by a band, and the band is provided so as to become away from said window side to which the curtain portion is fixed.
4. The curtain airbag device of claim 3, wherein said band is provided at an outer side of said curtain portion in the folded state.
5. The curtain airbag device of claim 1, wherein said curtain portion has a lobe portion at which a slot is formed, and said tip side portion and said tension portion are connected by said lobe portion and said support portion engages with the slot.
6. The curtain airbag device of claim 1, wherein said window is a vehicle window, and said specified condition includes at least a vehicle-crash detection, a vehicle-crash prediction, or a vehicle-rollover detection.
7. The curtain airbag device of claim 6, wherein said support portion forms a tension line at the curtain portion when the curtain portion is inflated, and the tension line is formed at a location in which a center of an occupant’s head is located at a side of said window side to which the curtain portion is fixed relative to the tension line.
8. The curtain airbag device of claim 1, wherein said inflatable portion is formed near said tension portion.
9. The curtain airbag device of claim 1, wherein said inflatable portion is formed on a tension line of the curtain portion that is formed by said tension portion.
10. The curtain airbag device of claim 1, wherein said inflatable portion has a tip portion, and when the curtain portion is inflated, the tip portion of the inflatable portion extends beyond a window side other than said first, second and third window sides.
11. The curtain airbag device of claim 10, wherein an angle formed between said window side to which the curtain portion is fixed and an adjacent window side is configured to be obtuse.
12. The curtain airbag device of claim 10, wherein said inflatable portion is configured so as to be inflated in a substantially pole shape, extending beyond said window side.
13. The curtain airbag device of claim 12, wherein said inflatable portion is inflated in the substantially pole shape so as to be located close to either one of said second and third window sides.
14. The curtain airbag device of claim 10, wherein said window is a side window provided at a vehicle side, said specified condition includes at least a vehicle-crash detection, a vehicle-crash prediction, or a vehicle-rollover detection, and said inflatable portion is configured so as to be inflated, extending from the first window side located at an upper side of the vehicle beyond a belt line of a lower window side of the side window, in such a manner that the inflatable portion in the inflated state overlaps with a vertically-extending window pillar of the vehicle.