Author: claimsbot

1. A radar for acquiring a synthetic aperture image of a scene, said scene having one or more radar scatterers located on a horizontal flat {circumflex over (x)},\u0177 plane, said radar system mounted on a moving platform moving at an angle \u03b8tilt with respect to said {circumflex over (x)},\u0177 plane, with a component of motion in a {circumflex over (z)} direction, said {circumflex over (z)} direction perpendicular to said {circumflex over (x)},\u0177 plane, said radar comprising:
a radar receiver for digitizing radar returns having a phase from said scene, and
a computer for adjusting said phase of said radar returns in response to said \u03b8tilt to generate phase adjusted returns and computing said synthetic aperture image from said phase adjusted returns.
2. A radar system as described in claim 1 wherein said phase of said radar returns is adjusted by computing a nominal aircraft track xac,o(s) given by
xac,o(s)=s cos(\u03b8tilt){circumflex over (x)}+yac,o\u0177+zac,o{circumflex over (z)}+s sin (\u03b8tilt){circumflex over (z)};

an aircraft position parameter s given by
s
=
1

cos
\u2062
\u2062

(

\u03b8
tilt

)
\u2061
x
o

+
x
ac

–

x
o
y
ac

–

y
o
\u2062

(
y

ac
,
o
–

y
o
)
;
a Fast Time Scale Factor SFRI given by
SF
RI

=
y

ac
,
o
–

y
o
y
ac

–

y
o
\xb7
\uf603
x
ac

–

x
o
\uf604
\uf603
x

ac
,
o
\u2061

(
s
)
–

x
o
\uf604
;
a Range Offset Rp given by
R
p

=
\uf603
x
ac

–

x
o
\uf604

–
1

SF
RI
\u2061
\uf603
x

ac
,
o
\u2061

(
s
)
–

x
o
\uf604

–

R
s
;
a phase adjustment given by
r
\u2062
\u2062

(
x

ac
,
o
\u2061

(
s
)
,

x
T
)
=
\u2147

\u2148
\u2062
\u2062

(

SF
RI

)

\u2062
\u2062
\u03d5
real

\u2061

(
x
ac

,

x
T
)
\u2062

\u2147
–
\u2148

\u2062
4
\u2062
\u03c0

\u03bb

\u2062

R
p
;
\u2003where
xac,o yac,o and zac,o show an aircraft position,
xo yo and zo show an initial aircraft position in the {circumflex over (x)},\u0177,{circumflex over (z)} direction respectively, and
\u03bb is an operating wavelength of said radar, xT is radar target location and Rs is an initial range.
3. A method for acquiring a synthetic aperture image of a scene using a radar system, said scene having one or more radar scatterers located on a horizontal flat {circumflex over (x)},\u0177 plane, said radar system mounted on a moving platform moving at an angle \u03b8tilt with respect to said {circumflex over (x)},\u0177 plane, with a component of motion in a {circumflex over (z)} direction, said {circumflex over (z)} direction perpendicular to said {circumflex over (x)},\u0177 plane, said method comprising the steps of:
digitizing radar returns having a phase from said scene;
adjusting said phase of said radar returns in response to said \u03b8tilt to generate phase adjusted returns;
computing said synthetic aperture image from said phase adjusted returns.
4. A method as described in claim 3 wherein said phase of said radar returns is adjusted by computing a nominal aircraft track xac,o(s) given by
xac,o(s)=s cos(\u03b8tilt){circumflex over (x)}+yac,o\u0177+zac,o{circumflex over (z)}+s sin (\u03b8tilt){circumflex over (z)};

an aircraft position parameter s given by
s
=
1

cos
\u2062
\u2062

(

\u03b8
tilt

)
\u2061
x
o

+
x
ac

–

x
o
y
ac

–

y
o
\u2062

(
y

ac
,
o
–

y
o
)
;
a Fast Time Scale Factor SFRI given by
SF
RI

=
y

ac
,
o
–

y
o
y
ac

–

y
o
\xb7
\uf603
x
ac

–

x
o
\uf604
\uf603
x

ac
,
o
\u2061

(
s
)
–

x
o
\uf604
;
a Range Offset Rp given by
R
p

=
\uf603
x
ac

–

x
o
\uf604

–
1

SF
RI
\u2061
\uf603
x

ac
,
o
\u2061

(
s
)
–

x
o
\uf604

–

R
s
;
a phase adjustment given by
\u0393(xac,o(s), xT)=ei(SFRI)\u03a6real(xac,xT)e\u2212i4\u03c0\u03bbRp;
\u2003where
xac,o yac,o and zac,o show an aircraft position,
xo yo and zo show an initial aircraft position in the {circumflex over (x)},\u0177,{circumflex over (z)} direction respectively, and
\u03bb is an operating wavelength of said radar, xT is radar target location and Rs is an initial range.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for managing a plurality of different middleware transport modules, the method comprising:
starting a first middleware transport module of the plurality of different middleware transport modules as a root service of the application;
identifying at least one additional middleware transport module of the plurality of different middleware transport modules to be managed contemporaneously with the first middleware transport module;
starting the at least one additional middleware transport module; and
managing the first middleware transport module and the at least one additional middleware transport module by managing only the first middleware transport module within the application.
2. The method according to claim 1, in which the first middleware transport module interfaces to a piece of business logic, the method further comprising:
providing the business logic to the at least one additional middleware transport module.
3. The method according to claim 2, in which the business logic is provided to the at least one additional middleware transport module after starting the at least one additional middleware transport module within the application.
4. The method according to claim 1, in which the plurality of different middleware transport modules comprise a Java Message Service (JMS) application and a Common Object Request Broker Application (CORBA) application.
5. The method according to claim 1, in which managing the first middleware transport module and the at least one additional middleware transport module comprises closing the first middleware transport module and the at least one additional middleware transport module.
6. The method according to claim 5, in which closing the at least one additional middleware transport module comprises calling an equivalent of a closing instruction of the at least one additional middleware transport module based upon closing the first middleware transport module.
7. The method according to claim 5, in which closing the at least one additional middleware transport module comprises deregistering from at least one of a directory service and a name service.
8. The method according to claim 1, in which each of the first middleware transport module and the at least one additional middleware transport module functions according to its corresponding nature after being started.
9. The method according to claim 1, further comprising:
selecting the first middleware transport module as a main thread, the main thread being started as the root service.
10. The method according to claim 9, in which the at least one additional middleware transport module comprises a slave thread.
11. A computer readable medium that stores a program for managing a plurality of different middleware transport modules within an application, the computer readable medium comprising:
a first starting code segment for starting a first middleware transport module of the plurality of different middleware transport modules as a root service;
an identifying code segment for identifying at least one additional middleware transport module of the plurality of different middleware transport modules to be managed contemporaneously with the first middleware transport module;
a second starting code segment for starting the at least one additional middleware transport module; and
a managing code segment for managing the first middleware transport module and the at least one additional middleware transport module by managing only the first middleware transport module.
12. The computer readable medium according to claim 11, further comprising:
a business logic code segment for providing a business logic, with which the first middleware transport module interfaces, to the at least one additional middleware transport module.
13. The computer readable medium according to claim 12, in which the business logic code segment provides the business logic to the at least one additional middleware transport module after starting the at least one additional middleware transport module.
14. The computer readable medium according to claim 11, in which the plurality of different middleware transport modules comprise a Java Message Service (JMS) application and a Common Object Request Broker Application (CORBA) application.
15. The computer readable medium according to claim 11, in which the managing code segment closes the first middleware transport module and the at least one additional middleware transport module.
16. The computer readable medium according to claim 15, in which closing the at least one additional middleware transport module comprises calling an equivalent of a closing instruction of the at least one additional middleware transport module based upon closing the first middleware transport module.
17. The computer readable medium according to claim 15, in which closing the at least one additional middleware transport module comprises deregistering from at least one of a directory service and a name service.
18. The computer readable medium according to claim 11, in which each of the first middleware transport module and the at least one additional middleware transport module functions according to its corresponding nature after being started.
19. A computer readable medium that stores a program for managing a plurality of types of middleware transport modules for accessing business logic, the computer readable medium comprising:
a first starting code segment for starting a first middleware transport module of the plurality of types of middleware transport modules as a main thread;
a second starting code segment for starting a second middleware transport module as a slave thread; and
a managing code segment for managing the main thread and the slave thread, the slave thread being managed in accordance with the managing of the main thread;
wherein a functionality of the slave thread remains independent of a functionality of the main thread.
20. The computer readable medium to claim 19, wherein managing the slave thread comprises shutting down the slave thread in response to shutting down the main thread.

1. A method comprising:
forming a first trench in a substrate, the first trench having a first width;
forming a first oxide layer on side surfaces of the first trench;
forming a second trench in the substrate, below the first trench, the second trench having a second width less than the first width;
forming a second oxide layer on side and bottom surfaces of the second trench;
forming spacers on sides of the first and second trenches;
removing a portion of the second oxide layer from the bottom surface of the second trench between the spacers;
filling the first and second trenches with a first poly-silicon to form a drain region;
removing the spacers, exposing side surfaces of the first poly-silicon;
forming a third oxide layer on the side surfaces and a top surface of the first poly-silicon; and
filling a remainder of the first and second trenches with a second poly-silicon to form a gate region on each side of the drain region.
2. The method according to claim 1, comprising:
doping the substrate around the second trench, after forming the second trench, to form a drift region.
3. The method according to claim 1, comprising:
doping the substrate beneath the bottom surface of the second trench, after forming the spacers, to form a N+ region.
4. The method according to claim 1, comprising:
forming nitride spacers on the sides of the first trench after forming the first oxide layer; and
forming the second trench using the nitride spacers as a hard mask.
5. The method according to claim 1, comprising:
forming a poly-silicon layer on the sides and bottom of the first and second trenches before forming the spacers.
6. The method according to claim 5, comprising:
forming the third oxide layer and a fourth oxide layer on side surfaces of the first and second trenches by respectively oxidizing the first poly-silicon and the poly-silicon layer; and
removing the fourth oxide layer and the nitride spacers before filling the remainder with the second poly-silicon.
7. The method according to claim 6, comprising:
forming a fifth oxide layer on the substrate after filling the remainder with the second poly-silicon; and
forming a low voltage transistor andor a medium voltage transistor on the fifth oxide layer.
8. The method according to claim 1, comprising:
forming the second oxide layer to be 500 \u212b to 20,000 \u212b in thickness; and
forming the third oxide layer to be 500 \u212b to 20,000 \u212b in thickness.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A integrated circuit device comprising:
a processor; and
Integrated InputOutput (IIO) logic coupled to the processor,
wherein at least a portion of the IIO logic is to enter a lower power consumption state based on a power reduction sequence, wherein the processor and the IIO logic are to each comprise sideband control logic to provide sideband communication support in lieu of removal of a physical link layer circuitry.
2. The device of claim 1, further comprising a power management unit, coupled to the IIO logic to cause the portion of the IIO logic to enter lower power consumption state.
3. The device of claim 1, wherein the power reduction sequence is based on coarse clock gating and a plurality of power sequence gating modes.
4. The device of claim 3, wherein the plurality of power sequence gating modes are to comprise: static clock gating, dynamic clock gating, full clock gating, pre-sleep, light sleep, or deep sleep modes.
5. The device of claim 4, wherein the static clock gating mode is to comprise clock gating one or more inactive blocks of the IIO logic based on: one or more features being disabled during operation or one or more interfaces not being supported.
6. The device of claim 4, wherein the dynamic clock gating mode is to comprise clock gating one or more inactive blocks of the IIO logic when the one or more blocks become inactive during runtime.
7. The device of claim 4, wherein the full clock gating mode is to comprise full coarse clock gating one or more blocks of the IIO logic.
8. The device of claim 4, wherein the pre-sleep mode is to comprise preparing a phase locked loop of the IIO logic for shut down.
9. The device of claim 4, wherein the light sleep mode is to comprise shutting down a phase locked loop of the IIO logic.
10. The device of claim 4, wherein the deep sleep mode is to comprise power gating one or more blocks of the IIO logic.
11. The device of claim 3, wherein the coarse clock gating corresponds to gating off an entire cluster or block of IIO hardware when idle or not in use.
12. The device of claim 1, wherein one or more inactive blocks of the IIO are to be coarse clock gated.
13. The device of claim 12, wherein the one or more inactive blocks are to be determined based on: one or more features being disabled during operation, one or more interfaces not being supported, or one or more blocks are idle as no traffic or transaction is occurring during runtime.
14. The device of claim 1, wherein the processor is to comprise one or more processor cores.
15. A method comprising:
generating a signal from a power management unit of IIO logic to cause at least a portion of an IIO logic to enter a lower power consumption state based on a power reduction sequence,
wherein the power reduction sequence is based on coarse clock gating and a plurality of power sequence gating modes and wherein the IIO logic comprises sideband control logic to provide sideband communication support in lieu of removal of a physical link layer circuitry.
16. The method of claim 15, wherein the plurality of power sequence gating modes are to comprise: static clock gating, dynamic clock gating, full clock gating, pre-sleep, light sleep, or deep sleep modes.
17. The method of claim 15, further comprising clock gating one or more inactive blocks of the IIO logic based on: one or more features being disabled during operation or one or more interfaces not being supported.
18. The method of claim 15, further comprising clock gating one or more inactive blocks of the IIO logic when the one or more blocks become inactive during runtime.
19. The method of claim 15, further comprising full coarse clock gating one or more blocks of the IIO logic.
20. The method of claim 15, further comprising preparing a phase locked loop of the IIO logic for shut down.
21. The method of claim 15, further comprising shutting down a phase locked loop of the IIO logic.
22. The method of claim 15, further comprising power gating one or more blocks of the IIO logic.
23. The method of claim 15, wherein the coarse clock gating corresponds to gating off an entire cluster or block of IIO hardware when idle or not in use.
24. The method of claim 15, further comprising communicating data between a system memory and one or more IO devices via the IIO logic.
25. A system comprising:
a system memory to store data;
a processor to access the stored data; and
Integrated InputOutput (IIO) logic coupled to the processor,
wherein at least a portion of the IIO logic is to enter a lower power consumption state based on a power reduction sequence, wherein the processor and the IIO logic are to each comprise sideband control logic to provide sideband communication support in lieu of removal of a physical link layer circuitry.
26. The system of claim 25, further comprising a power management unit, coupled to the IIO logic to cause the portion of the IIO logic to enter lower power consumption state.
27. The system of claim 25, wherein the power reduction sequence is based on coarse clock gating and a plurality of power sequence gating modes.
28. The system of claim 27, wherein the plurality of power sequence gating modes are to comprise: static clock gating, dynamic clock gating, full clock gating, pre-sleep, light sleep, or deep sleep modes.
29. The system of claim 28, wherein the static clock gating mode is to comprise clock gating one or more inactive blocks of the IIO logic based on: one or more features being disabled during operation or one or more interfaces not being supported.
30. The system of claim 28, wherein the light sleep mode is to comprise shutting down a phase locked loop of the IIO logic.