1. A drilling machine comprising:
a rotary drive system;
a dual-member drill string operatively connected to the rotary drive system;
wherein the dual-member drill string comprises a hollow outer member and an inner member positioned longitudinally therein, wherein the inner member is movable independently of the outer member; and
at least one downhole tool supported within the dual-member drill string and operable in response to relative movement between the outer member and the inner member of the dual-member drill string.
2. The drilling machine of claim 1 wherein the dual-member drill string comprises a plurality of dual-member pipe sections, each dual member pipe section comprising a hollow outer member and an inner member positioned therein, wherein the outer member is connectable with the outer members of adjacent pipe sections, wherein the inner member of the pipe section is connectable with the inner members of adjacent pipe sections.
3. The drilling machine of claim 1 wherein the downhole tool comprises a power generator operable in response to relative rotational movement between the outer member and the inner member of the dual-member drill string.
4. The drilling machine of claim 3 wherein the power generator comprises a hydraulic pump.
5. The drilling machine of claim 4 further comprising a hammer assembly supported by the drill string and operable in response to hydraulic pressure generated by the hydraulic pump.
6. The drilling machine of claim 1 wherein the drill string comprises an uphole end and a downhole end, wherein a boring head is supported at the downhole end of the drill string and operable in response to movement of the inner member of the drill string.
7. The drilling machine of claim 6 wherein the outer member of the drill string comprises a steering member disposed proximate to the boring head and adapted to steer the boring head.
8. The drilling machine of claim 7 further comprising a processor and at least an orientation sensor adapted to detect an orientation of the boring head and to transmit an orientation signal to the processor, wherein the processor processes the orientation signal and transmits a control signal to actuate the steering member.
9. The drilling machine of claim 1 further comprising a transmitter supported by the dual-member drill string and wherein the downhole tool comprises an electric generator electrically connected to the transmitter and operable in response to relative movement between the outer member and the inner member of the dual-member drill string.
10. A method for drilling a borehole using a drilling machine, the machine including a rotary drive system attached to a drill string having a hollow outer member and an inner member positioned longitudinally therein, wherein the inner member is movable independently of the outer member, the method comprising:
moving the two members relative to each other; and
converting the relative movement into an output power within the outer member.
11. The method of claim 10 wherein a downhole tool is attached to the drill string, the method further comprising:
axially advancing the downhole tool; and
operating the downhole tool in response to movement of the inner member relative to the outer member.
12. The method of claim 10 wherein a steering mechanism is operatively supported on the outer member of the drill string, the method comprising:
selectively moving the outer member of the drill string to position the steering mechanism.
13. The method of claim 12 further comprising activating the steering mechanism in response to movement of the inner member of the drill string.
14. The method of claim 10 wherein the drilling machine comprises an orientation sensor assembly adapted to transmit a control signal, wherein the method further comprises activating the steering mechanism in response to a control signal transmitted from the orientation sensor assembly.
15. The method of claim 11 wherein the drilling machine comprises an orientation sensor supported by the drill string and adapted to detect the orientation of the downhole tool, the method comprising powering the orientation sensor with the output power.
16. The method of claim 15 further comprising processing an orientation signal from the orientation sensor to control operation of the drilling machine.
17. The method of claim 10 wherein moving the two members relative to each other comprises rotating the inner member.
18. The method of claim 16 wherein converting the relative movement into an output power within the outer member comprises transmitting rotation of the inner member into an axial force.
19. An output power-generating apparatus comprising:
a hollow outer member connectable with an outer member of a dual-member drill string;
a bi-directionally movable inner member positioned within the outer member;
wherein the inner member is moveable independently of the outer member; and
an output power generator supported within the outer member and operatively connectable to the inner member for converting movement of the inner member relative to the outer member into an output power.
20. The apparatus of claim 19 wherein the output power generator is an electric generator.
21. The apparatus of claim 20 further comprising an orientation sensor and a transmitter, wherein operation of the orientation sensor and the transmitter is driven by the electric generator.
22. The apparatus of claim 19 wherein the output power generator comprises a hydraulic pump.
23. The apparatus of claim 22 further comprising a hammer assembly supported by the outer member and driven by the hydraulic pump.
24. A pipe section assembly for use in a drill string, the pipe section assembly comprising:
a hollow outer member interconnectable with the outer member of at least one of the pipe sections in the drill string;
an inner member arranged longitudinally within the outer member and moveable independently of the outer member; and
a downhole tool supported within the outer member and operatively connectable with the inner member so that movement of the inner member relative to the outer member drives operation of the downhole tool.
25. The pipe section assembly of claim 24 further comprising a power generator operable in response to relative movement between the outer member and the inner member.
26. The pipe section assembly of claim 25 further comprising an orientation sensor supported within the outer member, powered by the power generator, and adapted to detect the orientation of the downhole tool.
27. The pipe section assembly of claim 25 further comprising a transceiver powered by the generator.
28. The pipe section assembly of claim 24 wherein the downhole tool comprises a hammer assembly.
29. The pipe section assembly of claim 24 further comprising:
a hydraulic pump assembly operable in response to movement of the inner member relative to the outer member; and
a hammer assembly supported within the outer member and operable in response to hydraulic pressure generated by the hydraulic pump.
30. The pipe section assembly of claim 24 further comprising a steering member supported by the outer member and operable in response to movement of the inner member relative to the outer member.
31. The pipe section assembly of claim 24 comprising:
an electric generator supported by the outer member and operable in response to the relative movement of the inner member and outer member;
a transmitter supported by the outer member and electrically connected to the electric generator.
32. The pipe section assembly of claim 24 wherein movement of the inner member relative to the outer member comprises rotating the inner member.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A circuit to convert three input bits (A, B and C) to a redundant format, comprising:
a first block comprising at least one transmission gate, the first block to receive the three bits and to output a sum bit; and
a second block comprising at least one static mirror, the second block to receive the three bits and to output a carry bit.
2. A circuit according to claim 1, wherein the sum bit is equal to A XOR B XOR C.
3. A circuit according to claim 1, the first block comprising:
a first transmission gate comprising a first inverted control node, a first non-inverted control node, a first input and a first output, the first inverted control node to receive input bit B, the first non-inverted control node to receive B#, and the first output to receive input bit A;
a second transmission gate comprising a second inverted control node, a second non-inverted control node, a second input and a second output, the second inverted control node to receive B#, the second non-inverted control node to receive input bit B, and the second output connected to the first output;
a third transmission gate comprising a third input to receive input bit C, a third inverted control node, a third non-inverted control node, and a third output; and
a fourth transmission gate comprising a fourth input to receive C#, a fourth inverted control node connected to the third non-inverted control node and to the first input, a fourth non-inverted control node connected to the third inverted control node and to the second input, and a fourth output connected to the third output.
4. A circuit according to claim 3, the second block comprising:
a first p-channel transistor, a source of the first p-channel transistor connected to a supply voltage and a gate of the first p-channel transistor to receive input bit A;
a second p-channel transistor, a source of the second p-channel transistor connected to the supply voltage, a gate of the second p-channel transistor to receive input bit B, and a drain of the second p-channel transistor connected to a drain of the first p-channel transistor;
a third p-channel transistor, a source of the third p-channel transistor connected to the supply voltage and a gate of the third p-channel transistor to receive input bit A;
a fourth p-channel transistor, a source of the fourth p-channel transistor connected to the drain of the first p-channel transistor, and a gate of the fourth p-channel transistor to receive input bit C;
a fifth p-channel transistor, a source of the fifth p-channel transistor connected to the drain of the third p-channel transistor, a gate of the fifth p-channel transistor to receive input bit B, and a drain of the fifth p-channel transistor connected to a drain of the fourth p-channel transistor;
a first n-channel transistor, a source of the first n-channel transistor connected to ground and a gate of the first n-channel transistor to receive input bit A;
a second n-channel transistor, a source of the second n-channel transistor connected to ground, a gate of the second n-channel transistor to receive input bit B, and a drain of the second n-channel transistor connected to a drain of the first n-channel transistor;
a third n-channel transistor, a source of the third n-channel transistor connected to ground and a gate of the third n-channel transistor to receive input bit A;
a fourth n-channel transistor, a source of the fourth n-channel transistor connected to the drain of the first n-channel transistor, a gate of the fourth n-channel transistor to receive input bit C, and a drain of the fourth n-channel transistor connected to a drain of the fourth p-channel transistor; and
a fifth n-channel transistor, a source of the fifth n-channel transistor connected to the drain of the third n-channel transistor, a gate of the fifth n-channel transistor to receive input bit B, and a drain of the fifth n-channel transistor connected to a drain of the fifth p-channel transistor,
wherein the drain of the fifth n-channel transistor, the drain of the fifth p-channel transistor, the drain of the fourth n-channel transistor, and the drain of the fourth p-channel transistor are connected to one another.
5. A circuit according to claim 1, the second block comprising:
a first p-channel transistor, a source of the first p-channel transistor connected to a supply voltage and a gate of the first p-channel transistor to receive input bit A;
a second p-channel transistor, a source of the second p-channel transistor connected to the supply voltage, a gate of the second p-channel transistor to receive input bit B, and a drain of the second p-channel transistor connected to a drain of the first p-channel transistor;
a third p-channel transistor, a source of the third p-channel transistor connected to the supply voltage and a gate of the third p-channel transistor to receive input bit A;
a fourth p-channel transistor, a source of the fourth p-channel transistor connected to the drain of the first p-channel transistor, and a gate of the fourth p-channel transistor to receive input bit C;
a fifth p-channel transistor, a source of the fifth p-channel transistor connected to the drain of the third p-channel transistor, a gate of the fifth p-channel transistor to receive input bit B, and a drain of the fifth p-channel transistor connected to a drain of the fourth p-channel transistor;
a first n-channel transistor, a source of the first n-channel transistor connected to ground and a gate of the first n-channel transistor to receive input bit A;
a second n-channel transistor, a source of the second n-channel transistor connected to ground, a gate of the second n-channel transistor to receive input bit B, and a drain of the second n-channel transistor connected to a drain of the first n-channel transistor;
a third n-channel transistor, a source of the third n-channel transistor connected to ground and a gate of the third n-channel transistor to receive input bit A;
a fourth n-channel transistor, a source of the fourth n-channel transistor connected to the drain of the first n-channel transistor, a gate of the fourth n-channel transistor to receive input bit C, and a drain of the fourth n-channel transistor connected to a drain of the fourth p-channel transistor; and
a fifth n-channel transistor, a source of the fifth n-channel transistor connected to the drain of the third n-channel transistor, a gate of the fifth n-channel transistor to receive input bit B, and a drain of the fifth n-channel transistor connected to a drain of the fifth p-channel transistor,
wherein the drain of the fifth n-channel transistor, the drain of the fifth p-channel transistor, the drain of the fourth n-channel transistor, and the drain of the fourth p-channel transistor are connected to one another.
6. A circuit according to claim 1, further comprising:
a third block comprising at least one transmission gate, the third block to receive at least one of the sum bit and the carry bit and to output a second sum bit; and
a fourth block comprising at least one static mirror, the fourth block to receive at least one of the sum bit and the carry bit and to output a second carry bit.
7. A method to convert three input bits (A, B and C) to a redundant format, comprising:
receiving the three input bits at a first block comprising at least one transmission gate;
outputting a sum bit from the first block based at least on the three input bits;
receiving the three input bits at a second block comprising at least one static mirror;
outputting a carry bit from the second block based at least on the three input bits.
8. A method according to claim 7, wherein the sum bit is equal to A XOR B XOR C.
9. A method according to claim 7, further comprising:
receiving a second three input bits at a third block comprising at least one transmission gate, the second three input bits comprising at least one of the sum bit and the carry bit;
outputting a second sum bit from the third block based at least on the second three input bits;
receiving the second three input bits at a fourth block comprising at least one static mirror;
outputting a second carry bit from the fourth block based at least on the second three input bits.
10. A method according to claim 7, further comprising:
receiving input bit B at a first inverted control node of a first transmission gate of the first block, the first transmission gate comprising a first non-inverted control node, a first input and a first output, the first non-inverted control node to receive B#, and the first output to receive input bit A;
receiving input bit B at a second non-inverted control node of a second transmission gate of the first block, the second transmission gate comprising a second inverted control node, a second input and a second output, the second inverted control node to receive B#, and the second output connected to the first output;
receiving input bit C at a third input of a third transmission gate of the first block, the third transmission gate comprising a third inverted control node, a third non-inverted control node, and a third output; and
receiving C# at a fourth input of a fourth transmission gate of the first block, the fourth transmission gate comprising a fourth inverted control node connected to the third non-inverted control node and to the first input, a fourth non-inverted control node connected to the third inverted control node and to the second input, and a fourth output connected to the third output.
11. A method according to claim 10, further comprising:
receiving input bit A at a gate of a first p-channel transistor of the second block, a source of the first p-channel transistor connected to a supply voltage;
receiving input bit B at a gate of a second p-channel transistor of the second block, a source of the second p-channel transistor connected to the supply voltage, and a drain of the second p-channel transistor connected to a drain of the first p-channel transistor;
receiving input bit A at a gate of a third p-channel transistor of the second block, a source of the third p-channel transistor connected to the supply voltage;
receiving input bit C at a gate of a fourth p-channel transistor of the second block, a source of the fourth p-channel transistor connected to the drain of the first p-channel transistor;
receiving input bit B at a gate of a fifth p-channel transistor of the second block, a source of the fifth p-channel transistor connected to the drain of the third p-channel transistor, and a drain of the fifth p-channel transistor connected to a drain of the fourth p-channel transistor;
receiving input bit A at a gate of a first n-channel transistor of the second block, a source of the first n-channel transistor connected to ground;
receiving input bit B at a gate of a second n-channel transistor of the second block, a source of the second n-channel transistor connected to ground, and a drain of the second n-channel transistor connected to a drain of the first n-channel transistor;
receiving input bit A at a gate of a third n-channel transistor of the second block, a source of the third n-channel transistor connected to ground;
receiving input bit C at a gate of a fourth n-channel transistor of the second block, a source of the fourth n-channel transistor connected to the drain of the first n-channel transistor, and a drain of the fourth n-channel transistor connected to a drain of the fourth p-channel transistor; and
receiving input bit B at a gate of a fifth n-channel transistor of the second block, a source of the fifth n-channel transistor connected to the drain of the third n-channel transistor, and a drain of the fifth n-channel transistor connected to a drain of the fifth p-channel transistor,
wherein the drain of the fifth n-channel transistor, the drain of the fifth p-channel transistor, the drain of the fourth n-channel transistor, and the drain of the fourth p-channel transistor are connected to one another.
12. A method according to claim 7, further comprising:
receiving input bit A at a gate of a first p-channel transistor of the second block, a source of the first p-channel transistor connected to a supply voltage;
receiving input bit B at a gate of a second p-channel transistor of the second block, a source of the second p-channel transistor connected to the supply voltage, and a drain of the second p-channel transistor connected to a drain of the first p-channel transistor;
receiving input bit A at a gate of a third p-channel transistor of the second-block, a source of the third p-channel transistor connected to the supply voltage;
receiving input bit C at a gate of a fourth p-channel transistor of the second block, a source of the fourth p-channel transistor connected to the drain of the first p-channel transistor;
receiving input bit B at a gate of a fifth p-channel transistor of the second block, a source of the fifth p-channel transistor connected to the drain of the third p-channel transistor, and a drain of the fifth p-channel transistor connected to a drain of the fourth p-channel transistor;
receiving input bit A at a gate of a first n-channel transistor of the second block, a source of the first n-channel transistor connected to ground;
receiving input bit B at a gate of a second n-channel transistor of the second block, a source of the second n-channel transistor connected to ground, and a drain of the second n-channel transistor connected to a drain of the first n-channel transistor;
receiving input bit A at a gate of a third n-channel transistor of the second block, a source of the third n-channel transistor connected to ground;
receiving input bit C at a gate of a fourth n-channel transistor of the second block, a source of the fourth n-channel transistor connected to the drain of the first n-channel transistor, and a drain of the fourth n-channel transistor connected to a drain of the fourth p-channel transistor; and
receiving input bit B at a gate of a fifth n-channel transistor of the second block, a source of the fifth n-channel transistor connected to the drain of the third n-channel transistor, and a drain of the fifth n-channel transistor connected to a drain of the fifth p-channel transistor,
wherein the drain of the fifth n-channel transistor, the drain of the fifth p-channel transistor, the drain of the fourth n-channel transistor, and the drain of the fourth p-channel transistor are connected to one another.
13. A system comprising:
a processor comprising a circuit to convert three input bits (A, B and C) to a redundant format, the circuit comprising:
a first block comprising at least one transmission gate, the first block to receive the three bits and to output a sum bit; and
a second block comprising at least one static mirror, the second block to receive the three bits and to output a carry bit; and
a double data rate memory coupled to the processor.
14. A system according to claim 13, wherein the sum bit is equal to A XOR B XOR C.
15. A system according to claim 13, the first block comprising:
a first transmission gate comprising a first inverted control node, a first non-inverted control node, a first input and a first output, the first inverted control node to receive input bit B, the first non-inverted control node to receive B#, and the first output to receive input bit A;
a second transmission gate comprising a second inverted control node, a second non-inverted control node, a second input and a second output, the second inverted control node to receive B#, the second non-inverted control node to receive input bit B, and the second output connected to the first output;
a third transmission gate comprising a third input to receive input bit C, a third inverted control node, a third non-inverted control node, and a third output; and
a fourth transmission gate comprising a fourth input to receive C#, a fourth inverted control node connected to the third non-inverted control node and to the first input, a fourth non-inverted control node connected to the third inverted control node and to the second input, and a fourth output connected to the third output.
16. A system according to claim 15, the second block comprising:
a first p-channel transistor, a source of the first p-channel transistor connected to a supply voltage and a gate of the first p-channel transistor to receive input bit A;
a second p-channel transistor, a source of the second p-channel transistor connected to the supply voltage, a gate of the second p-channel transistor to receive input bit B, and a drain of the second p-channel transistor connected to a drain of the first p-channel transistor;
a third p-channel transistor, a source of the third p-channel transistor connected to the supply voltage and a gate of the third p-channel transistor to receive input bit A;
a fourth p-channel transistor, a source of the fourth p-channel transistor connected to the drain of the first p-channel transistor, and a gate of the fourth p-channel transistor to receive input bit C;
a fifth p-channel transistor, a source of the fifth p-channel transistor connected to the drain of the third p-channel transistor, a gate of the fifth p-channel transistor to receive input bit B, and a drain of the fifth p-channel transistor connected to a drain of the fourth p-channel transistor;
a first n-channel transistor, a source of the first n-channel transistor connected to ground and a gate of the first n-channel transistor to receive input bit A;
a second n-channel transistor, a source of the second n-channel transistor connected to ground, a gate of the second n-channel transistor to receive input bit B, and a drain of the second n-channel transistor connected to a drain of the first n-channel transistor;
a third n-channel transistor, a source of the third n-channel transistor connected to ground and a gate of the third n-channel transistor to receive input bit A;
a fourth n-channel transistor, a source of the fourth n-channel transistor connected to the drain of the first n-channel transistor, a gate of the fourth n-channel transistor to receive input bit C, and a drain of the fourth n-channel transistor connected to a drain of the fourth p-channel transistor; and
a fifth n-channel transistor, a source of the fifth n-channel transistor connected to the drain of the third n-channel transistor, a gate of the fifth n-channel transistor to receive input bit B, and a drain of the fifth n-channel transistor connected to a drain of the fifth p-channel transistor,
wherein the drain of the fifth n-channel transistor, the drain of the fifth p-channel transistor, the drain of the fourth n-channel transistor, and the drain of the fourth p-channel transistor are connected to one another.