All The Claims

1. A device for enhancing performance of a portable wireless communication device within a mobile vehicle, comprising:
a housing to enclose the portable wireless communication device, the housing including an exterior reflective layer and an interior nonreflective layer;
an RF coupling device positioned within the housing; and
a transceiver positioned on an exterior surface of the vehicle, the transceiver operably connected to the RF coupling device,
wherein the exterior reflective layer reflects extraneous noise signals away from the housing.
2. The device of claim 1 wherein the RF coupling device is a quarter-wave antenna.
3. The device of claim 1 wherein the transceiver is an antenna.
4. The device of claim 1 wherein the RF coupling device and the transceiver are operably connected using a coaxial cable.
5. The device of claim 1 wherein the nonreflective layer comprises foam.
6. The device of claim 1 wherein the reflective layer comprises metal.
7. The device of claim 6 wherein the metal comprises aluminum.
8. The device of claim 1 wherein the housing includes a closable opening through which the portable wireless communication device may be inserted or removed.
9. The device of claim 1 further comprising:
an RF signal amplifier.
10. The device of claim 1 further comprising:
a second transceiver operably positioned within the housing, the second transceiver operably connected to a vehicle sound system.
11. The device of claim 1 further comprising:
a power source positioned within the housing, the power source compatible with the portable wireless communication device.
12. A method for enhancing performance of a portable wireless communication device within a mobile vehicle, comprising:
enclosing the portable wireless communication device within a housing;
reflecting noise signals from outside the housing;
reducing reflection of communication signals within the housing; and
transmitting and receiving signals between the enclosed communication device and a transceiver operably positioned on an exterior surface of the vehicle.
13. The method of claim 12 further comprising:
transmitting and receiving signals between the enclosed communication device and a sound system within the vehicle.
14. The method of claim 12 further comprising:
amplifying the transmitted and received signals.
15. The method of claim 12 further comprising;
providing power to the portable wireless communication device.
16. A system for enhancing performance of a portable wireless communication device within a mobile vehicle, comprising:
means for enclosing the portable wireless communication device;
means for reflecting noise from outside the enclosing means;
means for reducing reflection of communication signals within the enclosing means; and
means for transmitting and receiving signals between the enclosed communication device and a transceiver operably positioned on an exterior surface of the vehicle.
17. The system of claim 16 further comprising:
means for transmitting and receiving signals between the enclosed communication device and a sound system within the vehicle.
18. The system of claim 16 further comprising:
means for amplifying the transmitted and received signals.
19. The system of claim 16 further comprising;
means for providing power to the portable wireless communication device.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1-10. (canceled)
11. A method for substitute switching of spatially separated switching systems, comprising:
providing a pair of switching systems having one-to-one redundancy, comprising a first switching system in an active operating state in terms of switching, and a second switching system in a hot-standby operating state in terms of switching, the second switching system geographically separated from the first switching system;
establishing communication between a monitoring system and at least one of the paired switching systems; and
changing over in terms of switching from the active switching system to the hot-standby switching system in the event of a loss of communication to the switching system in the active operating state,
wherein the change over occurs in real time.
12. The method as claimed in claim 11,
wherein each switching system comprising a central controller,
the method further comprising exchanging test messages between the monitoring system and the central controllers of the paired switching systems.
13. The method as claimed in claim 12, wherein the messages are exchanged periodically.
14. The method as claimed in claim 12, wherein the exchange of the test messages between the monitoring system and the switching system in the active operating state is controlled via the switching system by sending a test request to the monitoring system and receiving a positive acknowledgement.
15. The method as claimed in claim 12, wherein the exchange of the test message between the monitoring system and the switching system in the hot-standby operating state is controlled via the switching system by sending a test request to the monitoring system and receiving a negative acknowledgement.
16. The method as claimed in claim 12, wherein the exchange of the test messages between the monitoring system and the switching system in the hot-standby operating state is controlled via the switching system by sending a test request to the monitoring system and receiving no acknowledgement.
17. The method as claimed in 12, further comprising:
reporting to the network management system by the monitoring system the loss of communication with the switching system in the active operating state; and
sending changeover instructions to the monitoring system.
18. The method as claimed in 12,
wherein the change over is controlled by the monitoring system by sending a positive acknowledgement to a test request sent by the switching system in hot-standby operating state, and
wherein the switching system in the hot-standby operating state is changed to the active operating state by the central controller after receiving the positive acknowledgement.
19. The method as claimed in 18, wherein the switching system with the communication loss is changed to the hot-standby operating state and is not automatically switched back to the active operating state following a resolution of the communication loss.
20. The method as claimed in 11, further comprising:
reporting to the network management system by the monitoring system the loss of communication with the switching system in the active operating state; and
sending changeover instructions to the monitoring system.
21. The method as claimed in 11,
wherein the change over is controlled by the monitoring system by sending a positive acknowledgement to a test request, and
wherein the switching system in the hot-standby operating state is changed to the active operating state after receiving the positive acknowledgement.
22. The method as claimed in 21, wherein the switching system with the communication loss is changed to the hot-standby operating state and is not automatically switched back to the active operating state following a resolution of the communication loss.
23. A monitoring system for monitoring a failure of an active switching system, comprising:
a first monitor comprising:
a first communication link to the active switching system, the active switching system in an active operating state in terms of switching,
a second communication link to a second switching system that is geographically separated from the first switching system, the second switching system in a hot-standby operating state in terms of switching;

a second monitor that is geographically separated from the first monitor, the second monitor comprising:
a first communication link to the active switching system, the active switching system in an active operating state in terms of switching,
a second communication link to a second switching system that is geographically separated from the first switching system, the second switching system in a hot-standby operating state in terms of switching; and

a communication link between the first and second monitors,
wherein a failure on the first communication link triggers the second switching system to change over to the active operating state, and
wherein the change over is in real time.
24. The monitoring system as claimed in claim 23, wherein the a communication loss between the first monitor and the active switching system causes a synchronization between the monitoring systems in order to trigger the second switching system to change over to the active operating state.
25. The monitoring system as claimed in claim 24, wherein the active switching system determined by both the first and second monitors is maintained active if a communication fault between the first and second monitors occurs.

1. A nonvolatile semiconductor memory device comprising:
a memory cell array having a first sub-bank in which a plurality of nonvolatile memory cells are arranged in a form of a matrix, first terminals of the memory cells of the same row are connected to a common word line, and second terminals of the memory cells of the same column are connected to a common bit line and a second sub-bank having the same configuration as that of the first sub-bank;
a writeread control unit that performs write or read control for a target memory cell corresponding to a designated address;
a decoder unit that applies a voltage to the bit line and the word line based on an instruction from the writeread control unit to apply a write voltage or a read voltage to the target memory cell;
a read circuit that reads written data from the target memory cell to which the read voltage is applied; and
a comparing unit that compares a plurality of data to be input, wherein,
when respectively designated write target data are written in the plurality of target memory cells located in the first-sub-bank and the second sub-bank, the decoder unit executes, in the same time zone,
a first operation in which a read voltage is applied to a first target memory cell in the first sub-bank, and
a second operation in which a write voltage is applied to a second target memory cell only when a comparison result between the written data of the second target memory cell in the second sub-bank and the write target data to the second target memory cell by the comparing unit represents mismatching.
2. The nonvolatile semiconductor memory device according to claim 1, wherein,
when the respectively designated write target data are written in the plurality of target memory cells located in the first sub-bank and the second sub-bank,
the decoder unit is configured to execute an operation step including the first operation and the second operation two or more times while changing the first target memory cell and the second target memory cell, and
the second target memory cell in each of the operation steps is the first target memory cell in the previously executed operation step.
3. The nonvolatile semiconductor memory device according to claim 1, wherein
the decoder unit includes
a row decoder that is arranged in common in the first sub-bank and the second sub-bank and simultaneously applies a voltage to the corresponding word lines in the first sub-bank and the second sub-bank,
a first column decoder that applies a voltage to the bit line of the first sub-bank,
a second column decoder that applies a voltage to the bit line of the second sub-bank,
the first operation is an operation in which the first column decoder applies the read voltage to the bit line connected to the first target memory cell in a state in which the row decoder applies a voltage to the word line connected to the first target memory cell, and
the second operation is an operation in which the second column decoder applies the write voltage to the bit line connected to the second target memory cell located at the same row as the first target memory cell only when a comparison result between the written data in the second target memory cell and the write target data to the second target memory cell represents mismatching.
4. The nonvolatile semiconductor memory device according to claim 1, wherein
the memory cell array includes a plurality of memory units each configured by the first sub-bank and the second sub-bank, and
the decoder unit is provided for each of the memory units,
when the respectively designated write target data are written in the plurality of target memory cells arranged across the plurality of memory units,
the decoder units provided in the memory units in which the target memory cells are present execute the first operation and the second operation in the same time zone.
5. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell comprises a variable resistive element a resistance of which is reversibly changed depending on an applied voltage and is configured to store information depending on the resistance of the variable resistive element.
6. A method of driving a nonvolatile semiconductor memory device including a memory cell array having a first sub-bank in which a plurality of nonvolatile memory cells are arranged in a form of a matrix, first terminals of the memory cells of the same row are connected to a common word line, and second terminals of the memory cells of the same column are connected to a common bit line, and a second sub-bank having the same configuration as that of the first sub-bank, wherein
when respectively designated write target data are written in the plurality of target memory cells located in the first-sub-bank and the second sub-bank,
a first operation in which a read voltage is applied to a first target memory cell in the first sub-bank, and a second operation in which a write voltage is applied to a second target memory cell only when a comparison result between written data of the second target memory cell in the second sub-bank and the write target data to the second target memory cell represents mismatching are executed in the same time zone.
7. The method of driving a nonvolatile semiconductor memory device according to claim 6, wherein
an operation step including the first operation and the second operation is executed two or more times while changing the first target memory cell and the second target memory cell, and
the second target memory cell in each of the operation steps is the first target memory cell in the previously executed operation step.
8. The method of driving a nonvolatile semiconductor memory device according to claim 6, wherein
the memory cell array includes a plurality of memory units each configured by the first sub-bank and the second sub-bank, and,
when the respectively designated write target data are written in the plurality of target memory cells arranged across the plurality of memory units,
in each of the memory units in which the target memory cells are present, the first operation and the second operation are executed in the same time zone.
9. A nonvolatile semiconductor memory device comprising:
a memory cell array having a first sub-bank in which a plurality of memory cells are arranged in a form of a matrix, first terminals of the memory cells of the same row are connected to a common word line, and second terminals of the memory cells of the same column are connected to a common bit line and a second sub-bank having the same configuration as that of the first sub-bank;
a writeread control unit that performs write or read control for a target memory cell corresponding to a designated address;
a decoder unit that performs a write process or a read process in the target memory cell based on an instruction from the writeread control unit;
a read circuit that reads written data from the target memory cell; and
a comparing unit that compares a plurality of data to be input, wherein,
when respectively designated write target data are written in the plurality of target memory cells located in the first-sub-bank and the second sub-bank,
the decoder unit executes, in the same time zone
a first operation in which a read process is performed in a first target memory cell in the first sub-bank and
a second operation in which a write process is performed in a second target memory cell only when a comparison result between the written data of the second target memory cell in the second sub-bank and the write target data to the second target memory cell by the comparing unit represents mismatching.
10. The nonvolatile semiconductor memory device according to claim 2, wherein
the decoder unit includes
a row decoder that is arranged in common in the first sub-bank and the second sub-bank and simultaneously applies a voltage to the corresponding word lines in the first sub-bank and the second sub-bank,
a first column decoder that applies a voltage to the bit line of the first sub-bank,
a second column decoder that applies a voltage to the bit line of the second sub-bank,
the first operation is an operation in which the first column decoder applies the read voltage to the bit line connected to the first target memory cell in a state in which the row decoder applies a voltage to the word line connected to the first target memory cell, and
the second operation is an operation in which the second column decoder applies the write voltage to the bit line connected to the second target memory cell located at the same row as the first target memory cell only when a comparison result between the written data in the second target memory cell and the write target data to the second target memory cell represents mismatching.
11. The nonvolatile semiconductor memory device according to claim 2, wherein
the memory cell array includes a plurality of memory units each configured by the first sub-bank and the second sub-bank, and
the decoder unit is provided for each of the memory units,
when the respectively designated write target data are written in the plurality of target memory cells arranged across the plurality of memory units,
the decoder units provided in the memory units in which the target memory cells are present execute the first operation and the second operation in the same time zone.
12. The nonvolatile semiconductor memory device according to claim 2, wherein the memory cell comprises a variable resistive element a resistance of which is reversibly changed depending on an applied voltage and is configured to store information depending on the resistance of the variable resistive element.
13. The method of driving a nonvolatile semiconductor memory device according to claim 7, wherein
the memory cell array includes a plurality of memory units each configured by the first sub-bank and the second sub-bank, and,
when the respectively designated write target data are written in the plurality of target memory cells arranged across the plurality of memory units,
in each of the memory units in which the target memory cells are present, the first operation and the second operation are executed in the same time zone.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An ice making machine comprising:
a heat exchange system comprising an evaporator and a condenser configured to make ice pieces with water applied to said evaporator during a freeze cycle; and
a controller that controls a start time and an end time of the freeze cycle, wherein the start time begins only if a temperature of said water is 32 degrees F. or lower and the end time is based on a temperature of refrigerant exiting said condenser when the start time begins.
2. The ice making machine of claim 1, wherein the end time is determined from a table of time versus condenser refrigerant exit temperatures at a time when the water is approximately 32 degrees F.
3. The ice making machine of claim 1, wherein said heat exchanger system further comprises one or more sprayers that spray the water on the evaporator.
4. The ice making machine of claim 1, further comprising a first temperature sensor located in the water and a second temperature sensor located to sense the temperature of the refrigerant exiting the condenser, and wherein the start and end times are determined based on temperatures sensed by the first and second temperature sensors.
5. The ice making machine of claim 1, further comprising a processor and program module associated with the controller, wherein the processor executes instructions of the program module to determine the start time and the end time of the freeze cycle.
6. A method of controlling ice making of an ice making machine comprising:
configuring an evaporator and a condenser to make ice pieces with water applied to said evaporator during a freeze cycle;
controlling a start time of the freeze cycle to begin only if a temperature of said water is 32 degrees F. or lower; and
controlling an end time of the freeze cycle based on a temperature of refrigerant exiting said condenser when the start time begins.
7. The method of claim 6, further comprising:
determining the end time from a table of time versus condenser refrigerant exit temperatures at a time when the water is approximately 32 degrees F.
8. The method of claim 6, further comprising:
locating a first temperature sensor to sense a temperature of the water;
locating a second temperature sensor to sense a temperature of refrigerant exiting the condenser, and wherein the start and end times are determined based on the temperatures sensed by the first and second temperature sensors.
9. The method of claim 6, further comprising:
executing instructions of a program module to determine the start time and end time of the freeze cycle.
10. The method of claim 6, further comprising:
spraying the water on the evaporator.