All The Claims

What is claimed is:

1. A frequency voltage converter comprising:
a first transmission line comprised of one signal line which branches off from a signal line for transmitting an input signal corresponding to a modulated wave signal;
a second transmission line comprised of the other signal line which branches off from said input signal transmitting signal line;
a mixer circuit having a first input terminal connected to said first transmission line and a second input terminal connected to said second transmission line;
a delay-amount variable first delay line circuit placed in said second transmission line between a portion where said first transmission line and said second transmission line branch off from each other and the second input terminal of said mixer circuit;
a third transmission line comprised of one signal line which branches of f from a signal line for transmitting a reference signal having a predetermined frequency;
a fourth transmission line comprised of the other signal line which branches off from said reference signal transmitting signal line;
a delay-amount variable second delay line circuit placed in said fourth transmission line between a portion where said third transmission line and said fourth transmission line branch off from each other and a portion where said third transmission line and said fourth transmission line are joined to each other; and
delay amount control means connected to said third transmission line, said fourth transmission line, a control section of said first delay line circuit and a control section of said second delay line circuit and for outputting the same control signal to the control section of said second delay line circuit and the control section of said first delay line circuit so that the reference signal passing through said fourth transmission line is delayed by a predetermined cycle with respect to the reference signal passing through said third transmission line.
2. The frequency voltage converter according to claim 1, wherein said first delay line circuit comprises a plurality of stages of unit delay circuits, said second delay line circuit comprises a plurality of stages of unit delay circuits, and the unit delay circuits constituting said first delay line circuit and the unit delay circuits constituting the second delay line circuit respectively have the same circuit configuration.
3. The frequency voltage converter according to claim 2, wherein when the number of stage of the unit delay circuits series-connected in said first delay line circuit, the number of stage of the unit delay circuits series-connected in said second delay line circuit, the center frequency of the input signal, and the frequency of the reference signal are respectively defined as a, b, fc and fr, the numbers of stage for said first delay line circuit and said second delay line circuit are respectively set so that abfr4fc is established, and the frequency of the reference signal is adjusted.
4. The frequency voltage converter according to claim 2, wherein when the number of stages of the unit delay circuits series-connected in said first delay line circuit, the number of stages of the unit delay circuits series-connected in said second delay line circuit, the center frequency of the input signal, and the frequency of the reference signal are respectively defined as a, b, fc and fr, the numbers of the stages for said first delay line circuit and said second delay line circuit are respectively set so that abfr2fc is established, and the frequency of the reference signal is adjusted.
5. The frequency voltage converter according to claim 2, further including:
a first buffer and a second buffer disposed in order from the side close to the branch portion between the branch portion and the first input terminal of said mixer circuit in said first transmission line,
a third buffer disposed between the branch portion and said first delay line circuit in said second transmission line,
a fourth buffer disposed between said first delay line circuit and the second input terminal of said mixer circuit in said second transmission line,
a fifth buffer and a sixth buffer disposed in order from the side close to the branch portion between the branch portion and the joined portion in said third transmission line,
a seventh buffer disposed between the branch portion and said second delay line circuit in said fourth transmission line, and
an eighth buffer disposed between said second delay line circuit and the joined portion in said fourth transmission line,
wherein said first buffer, said third buffer, said fifth buffer and said seventh buffer respectively have the same circuit configuration as an output buffer of said each unit delay circuit, and said second buffer, said fourth buffer, said sixth buffer and said eighth buffer respectively have the same circuit configuration as an input buffer of said each unit delay circuit.
6. A frequency voltage converter comprising:
a first transmission line comprised of one signal line which branches off from a signal line for transmitting an input signal corresponding to a modulated wave signal;
a second transmission line comprised of the other signal line which branches off from said input signal transmitting signal line;
a mixer circuit having a first input terminal connected to said first transmission line and a second input terminal connected to said second transmission line;
a delay-amount variable delay line circuit placed in said second transmission line between a portion where said first transmission line and said second transmission line branch off from each other and the second input terminal of said mixer circuit;
a signal line for transmitting a reference signal having a predetermined frequency;
a ring oscillator capable of varying an oscillation frequency; and
delay amount control means connected to the signal line for transmitting the reference signal, a signal line for transmitting a signal outputted from said ring oscillator, and a control section of said delay line circuit and a control section of said ring oscillator and for outputting the same control signal to the control section of said ring oscillator and the control section of said delay line circuit so that the frequency of the signal outputted from said ring oscillator coincides with that of the reference signal,
wherein said delay line circuit comprises a plurality of stages of unit delay circuits, said ring oscillator comprises a plurality of stages of unit delay circuits disposed in ring form, and the unit delay circuits constituting said delay line circuit and the unit delay circuits constituting said ring oscillator respectively have the same circuit configuration.
7. A frequency voltage converter comprising:
a first transmission line comprised of one signal line which branches off from a signal line for transmitting an input signal corresponding to a modulated wave signal;
a second transmission line comprised of the other signal line which branches off from said input signal transmitting signal line;
a mixer circuit having a first input terminal connected to said first transmission line and a second input terminal connected to said second transmission line;
a delay-amount variable delay line circuit placed in said second transmission line between a portion where said first transmission line and said second transmission line branch off from each other and the second input terminal of said mixer circuit;
a signal line for transmitting a reference signal having a predetermined frequency;
a ring oscillator capable of varying an oscillation frequency;
a divider for inputting a signal outputted from said ring oscillator; and
delay amount control means connected to the signal line for transmitting the reference signal, a signal line for transmitting a signal outputted from said divider, and a control section of said delay line circuit and a control section of said ring oscillator and for outputting the same control signal to the control section of said ring oscillator and the control section of said delay line circuit so that the frequency of the signal outputted from said divider coincides with that of the reference signal,
wherein said delay line circuit comprises a plurality of stages of unit delay circuits, said ring oscillator comprises a plurality of stages of unit delay circuits disposed in ring form, and the unit delay circuits constituting said delay line circuit and the unit delay circuits constituting said ring oscillator respectively have the same circuit configuration.
8. The frequency voltage converter according to claim 2, wherein each of delay-amount variable delay element circuits which are connected and provided by a predetermined number within said each unit delay circuit so as to constitute said unit delay circuit, is a differential circuit provided with current amount control means and output amplitude control means.
9. The frequency voltage converter according to claim 2, wherein each of delay-amount variable delay element circuits which are connected and provided by a predetermined number within said each unit delay circuit so as to constitute said unit delay circuit, is configured so that amount-of -current control means are connected in series with CMOS inverter circuits.
10. The frequency voltage converter according to claim 2, wherein a phase detector having a first input terminal connected to said first transmission line and a second input terminal connected to said second transmission line is disposed in place of said mixer circuit.
11. The frequency voltage converter according to claim 10, wherein said phase detector is a phase detecting circuit for detecting only delayed phase.
12. The frequency voltage converter according to claim 6, wherein each of delay-amount variable delay element circuits which are connected and provided by a predetermined number within said each unit delay circuit so as to constitute said unit delay circuit, is a differential circuit provided with current amount control means and output amplitude control means.
13. The frequency voltage converter according to claim 6, wherein each of delay-amount variable delay element circuits which are connected and provided by a predetermined number within said each unit delay circuit so as to constitute said unit delay circuit, is configured so that amount-of-current control means are connected in series with CMOS inverter circuits.
14. The frequency voltage converter according to claim 6, wherein a phase detector having a first input terminal connected to said first transmission line and a second input terminal connected to said second transmission line is disposed in place of said mixer circuit.
15. The frequency voltage converter according to claim 14, wherein said phase detector is a phase detecting circuit for detecting only delayed phase.
16. The frequency voltage converter according to claim 7, wherein each of delay-amount variable delay element circuits which are connected and provided by a predetermined number within said each unit delay circuit so as to constitute said unit delay circuit, is a differential circuit provided with current amount control means and output amplitude control means.
17. The frequency voltage converter according to claim 7, wherein each of delay-amount variable delay element circuits which are connected and provided by a predetermined number within said each unit delay circuit so as to constitute said unit delay circuit, is configured so that amount-of-current control means are connected in series with CMOS inverter circuits.
18. The frequency voltage converter according to claim 7, wherein a phase detector having a first input terminal connected to said first transmission line and a second input terminal connected to said second transmission line is disposed in place of said mixer circuit.
19. The frequency voltage converter according to claim 18, wherein said phase detector is a phase detecting circuit for detecting only delayed phase.
20. The frequency voltage converter according to claim 2, wherein when the number of stage of the unit delay circuits series-connected in said first delay line circuit, the number of stage of the unit delay circuits series-connected in said second delay line circuit, the center frequency of the input signal, and the frequency of the reference signal are respectively defined as a, b, fc and fr, the numbers of stage for said first delay line circuit and said second delay line circuit are respectively set so that ab3fr4fc or 3fr2fc is established, and the frequency of the reference signal is adjusted.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of handling secure data in a secure system, wherein the secure data is passed between a processor and memory external to the processor, comprising:
maintaining, in an encrypted form in the external memory, a set of metadata used to encrypt and decrypt the secure data;
maintaining, in a decrypted form in a cache internal to the processor, a limited subset of the metadata;
receiving a request to access a block of the secure data;
retrieving the block of secure data from the external memory in encrypted form;
determining whether a first portion of metadata needed to decrypt the block of secure data is in the cache;
when the first portion of metadata is not in the cache:
retrieving the first portion of metadata from the external memory;
determining whether a second portion of metadata is in the cache; and
when the second portion is not in the cache, retrieving the second portion of metadata from the external memory and decrypting the second portion of metadata using a third portion of metadata maintained in the cache;
decrypting the first portion of metadata using the second portion of metadata in the cache; and
decrypting the block of secure data using the first portion of metadata.
2. The method of claim 1, further comprising, when the first portion of metadata is in the cache:
calculating an address corresponding to a location of the first portion of metadata in the external memory; and
examining one or more tag ram entries for a match with the calculated address.
3. The method of claim 1, further comprising:
retrieving a portion of metadata from the external memory and decrypting the portion of metadata using metadata maintained in hardware on the processor.
4. The method of claim 1, further comprising:
validating the block of secure data by comparing an integrity value calculated on the secure block of data with an integrity value contained in the first portion of metadata.
5. The method of claim 4, further comprising:
placing a copy of the secure block of data in the cache; and
modifying the block of secure data in the cache without writing the block of secure data to the external memory until a cache line containing the block of secure data is cast out.
6. The method of claim 5, further comprising receiving a memory access request requiring the cache line containing the block of secure data to be cast out and, prior to casting the cache line out:
updating a security version value contained in the first portion of metadata;
updating an integrity value contained in the first portion of data based on the modified block of secure data;
encrypting the modified block of secure data using the updated security version value; and
writing the modified block of secure data to the external memory in encrypted form.
7. A method of handling secure data in a secure system, wherein the secure data is passed between a processor and memory external to the processor, comprising:
maintaining, in the external memory in an encrypted form, an authentication tree containing a first level of metadata comprising security version values for use in encrypting blocks of secure data and integrity values for use in authenticating blocks of secure data encrypted using the security version values and at least a second level containing security version values for use in encrypting portions of the first level of metadata;
maintaining, in external memory, blocks of secure data encrypted using the security version values contained in the first level of metadata;
maintaining, in a decrypted form in a cache internal to the processor, a limited subset of the authentication tree spanning multiple levels;
maintaining blocks of secure data in the cache; and
modifying a block of secure data in the cache without writing the block of secure data to the external memory until a cache line containing the block of secure data is cast out.
8. The method of claim 7, wherein modifying the block of secure data in the cache comprises modifying the block of secure data multiple times before writing the block of secure data to the external memory.
9. The method of claim 7, further comprising:
receiving a request to access secure data;
determining whether the requested secure data is contained in the cache; and when the requested secure data is contained in the cache, returning the secure data from the cache without accessing the external memory.
10. The method of claim 9, further comprising, when the requested secure data is not contained in the cache:
determining whether first metadata required to decrypt a block of secure data containing the requested data is contained in the first level of metadata maintained in the cache; and
when the first level metadata is maintained in the cache, retrieving the block of secure data containing the requested data and decrypting the block of secure data using the first level metadata.
11. The method of claim 10, further comprising when first metadata required to decrypt a block of secure data containing the requested data is not contained in the first level of metadata maintained in the cache:
determining whether second metadata required to decrypt a block of data containing the first metadata is contained in a second level of metadata maintained in the cache; and
when the second metadata is maintained in the cache, retrieving the block of data containing the first metadata and decrypting the block of data containing the first metadata using the second metadata.
12. The method of claim 10, further comprising initiating a read of the secure block of data prior to completion of decrypting the block of data containing the first metadata.
13. The method of claim 7, further comprising:
modifying at least one of data or metadata maintained in the cache without writing blocks of data containing the modified data or metadata to external memory until cache lines containing the blocks of modified data or metadata are cast out.
14. A method of handling secure data in a secure system, wherein the secure data is passed between a processor and memory external to the processor, comprising:
maintaining, in an encrypted form in the external memory, a set of metadata used to encrypt and decrypt the secure data;
maintaining, in a decrypted form in a cache internal to the processor, a limited subset of the metadata;
receiving a request to access a block of the secure data;
retrieving the block of secure data from the external memory in encrypted form;
determining when a first portion of metadata needed to decrypt the block of secure data is in the cache;
when the first portion of metadata is not in the cache:
retrieving the first portion of metadata from the external memory;
determining whether a second portion of metadata is in the cache; and
when the second portion is not in the cache, retrieving the second portion of metadata from the external memory and decrypting the second portion of metadata using a third portion of metadata maintained in the cache;
decrypting the first portion of metadata using the second portion of metadata; and

decrypting the block of secure data using the first portion of metadata in the cache, wherein:
(i) the first portion of metadata comprises one or more security version values used to affect encryption of secure data and one or more integrity values used to authenticate secure data encrypted using the one or more security version values; and
(ii) the second portion of metadata comprises one or more security version values used to affect encryption of the first portion of metadata.

1. Compounds of formula 1:
29
wherein
R is a group of formula
30
wherein
B is a C6-C10 aryl group, optionally substituted at the ortho-, meta- or para-positions with one or more substituents, which are the same or different, selected from the group consisting of C1-C3 alkoxy, C1-C2 halo alkyl, C1-C3 alkyl, halogens, carboxy, cyano, nitro; a C5-C7 cycloalkyl group, a 5 or 6 membered heterocyclic aromatic group, optionally benzofused, having at least one heteroatom selected from nitrogen, oxygen, sulfur; said heterocyclic group optionally having one or more substituents as described above for the aryl group;
R2 is hydrogen, C1-C4 alkyl, C5-C7 cycloalkyl or a phenyl group optionally substituted as indicated above;

R1 is a straight or branched C2-C8 acyl group
and the pharmaceutically acceptable salts thereof
2. Compounds as claimed in claim 1 wherein R is a group of formula
31
and B is an optionally substituted phenyl group as defined in claim 1, or a naphthyl group or a benzofused heterocyclic group.
3. Compounds as claimed in claim 1 wherein R is a group of formula
32
4. Compounds as claimed in claims 1-3 as central analgesic agents.
5. The use of the compounds of claims 1-3 for the preparation of analgesic medicaments.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An image display apparatus comprising:
a liquid crystal display element in which a plurality of display units including at least a pixel that displays an image for a first eyepoint and a pixel that displays an image for a second eyepoint are arranged in a matrix shape;
optical means which distributes light emitted from the pixel that displays the image for the first eyepoint and light emitted from the pixel that displays the image for the second eyepoint in mutually different directions;
a first control electrode and a second control electrode disposed on each pixel in the display units; and
a plurality of domain regions of which an orientation of liquid crystal molecules is controlled by a diagonal electric field or a lateral electric field formed by the first control electrode and the second control electrode and which have different liquid crystal molecule orientation states,
wherein, assuming that a direction of the light distributed by the optical means is a first direction and a direction orthogonal to the first direction is a second direction,
the optical principal axis of the optical means effectively passes through the center points of the display units and extends in the second direction;
each pixel in the display units is disposed along the first direction;
overlapping regions which overlap each other in the second direction are formed on each pixel adjacent to the first direction; and
the display units arranged in the second direction in the overlapping regions comprise different electric field structures which are formed depending on the display units, and respective domain regions disposed according to the electric field structures are disposed along the optical principal axis, and
wherein
the second control electrode disposed on an upper layer of the first control electrode via an insulating film comprises a plurality of slits extending in the first direction;
any one of the control electrodes is composed of a pixel electrode which can be independently driven in each of the pixels; and
a section between the pixel electrodes adjacent to each other in the first direction tilts in a direction different from the second direction in the overlapping region and is repeatedly disposed across the optical principal axis in each of the display units arranged in the second direction,
wherein
assuming that an angle between the second direction and a liquid crystal initial orientation direction \u03b8LC is (90-\u03b8) degree(s) and an angle between the second direction and a tilt direction between the pixel electrodes is \u03c6, a first region in which an angle between a liquid crystal initial orientation direction \u03b8LC and a liquid crystal driving electric field direction \u03c6E satisfies (90-\u03b8) degree(s), a second region in which an angle between a liquid crystal initial orientation direction \u03b8LC and a liquid crystal driving electric field direction \u03c6E satisfies (\u03c6+\u03b8) degree(s), and a third region in which an angle between a liquid crystal initial orientation direction \u03b8LC and a liquid crystal driving electric field direction \u03c6E satisfies (\u03c6-\u03b8) degree(s) are disposed on at least the optical principal axis and are periodically disposed along the second direction.
2. The image display apparatus according to claim 1, wherein
the first control electrode is a pixel electrode which can be controlled in each of the pixels;
the second control electrode is a common electrode in which a plurality of slits arranged in the second direction are disposed on an upper layer of the first control electrode depending on the pixel electrode;
the common electrode has a common potential in each pixel;
the orientation of the liquid crystal molecules is controlled by a potential of the pixel electrode disposed on each pixel; and
some of the slits are disposed across the optical principal axis in the overlapping region.
3. The image display apparatus according to claim 1, wherein
a control wiring line disposed across the optical principal axis in the overlapping region is disposed without overlapping the first control electrode.
4. The image display apparatus according to claim 3, wherein
the second control electrode is disposed to cover the control wiring line.
5. The image display apparatus according to claim 1, further comprising
a first row in which the display units comprising pixels displaying a data signal with same polarity of a positive polarity or a negative polarity are alternately repeatedly disposed in the first direction, and
a second row in which the display units comprising pixels with different polarities are repeated in the first direction,
wherein the first row and the second row are alternately disposed in the second direction.
6. The image display apparatus according to claim 1, wherein
assuming that a region in which respective pixels in the display units do not overlap each other in the second direction is a non-overlapping region, a domain region composed of the same electric field structure is disposed in each display unit arranged in the second direction in the non-overlapping region; and
a width, in the first direction, of the domain region in the non-overlapping region is set to be larger than widths, in the first direction, of the plurality of the domain regions disposed in the overlapping region.
7. The image display apparatus according to claim 1, wherein the ends of the slits disposed in the second control electrode are shifted and disposed in the first direction and the second direction in a boundary between pixels adjacent to each other in the first direction.
8. The image display apparatus according to claim 1, wherein the ends of the slits are formed in a non-rectangular shape and are disposed along the overlapping region.
9. The image display apparatus according to claim 1, wherein the ends of the slits are formed in a rectangular shape.
10. The image display apparatus according to claim 1, wherein the ends of the slits are curved.
11. The image display apparatus according to claim 1, wherein each of the pixels has an opening with a trapezoidal shape and is disposed to be symmetric with respect to the center points of the display units.
12. The image display apparatus according to claim 1, wherein each of the pixels has an opening with a parallelogram shape.
13. The image display apparatus according to claim 1, wherein an expanded width, in an image separation direction, of the overlapping region enlarged by the optical means is set to be equal or smaller than a width between both eyes of an observer at an observation distance where a three-dimensional vision range is maximum.
14. The image display apparatus according to claim 1, wherein a tilt angle between the pixel electrodes adjacent to each other in the first direction is a tilt angle \u03c6 or -\u03c6 with respect to the second direction; and
a range of the tilt angle \u03c6 is set at zero degree or more and 55 degrees or less.
15. The image display apparatus according to claim 1, wherein
the pixel comprises switching means connected to the first control electrode; a gate line for controlling the switching means; and a data line for inputting an image signal into the first control electrode through the switching means;
an adjacent pixel pair comprising two pixels disposed across one gate line and arranged in the second direction is composed as a base unit for driving; and
the respective switching means included in the two pixels are controlled by the common gate line sandwiched between the two pixels and are connected to different data lines.
16. The image display apparatus according to claim 1, wherein
the pixel comprises switching means connected to the first control electrode; a gate line for controlling the switching means; and a data line for inputting an image signal into the first control electrode through the switching means;
an adjacent pixel pair comprising two pixels disposed across one data line and arranged in the second direction is composed as a base unit for driving; and
the respective switching means included in the two pixels are connected to the common data line sandwiched between the two pixels and are controlled by different gate lines.
17. A method for driving the image display apparatus according to claim 15, comprising:
scanning the gate lines every two gate lines;
reversing the voltage polarity of each pixel every one gate line; and
reversing the polarity of each transmitted display data every one data line.
18. A method for driving the image display apparatus according to claim 16, comprising:
scanning the gate lines every two gate lines;
reversing the voltage polarity of each pixel every one gate line; and
reversing the polarity of each transmitted display data every one data line.
19. The image display apparatus according to claim 1, wherein
assuming that a region in which respective pixels in the display units do not overlap each other in the second direction is a non-overlapping region, a width, in the second direction, of a light shielding section in the non-overlapping region is set depending on the average transmittance of a liquid crystal layer in the overlapping region.
20. The image display apparatus according to claim 19, wherein
the light shielding section is curved in the non-overlapping region; and
the width of the light shielding section in the second direction is largest in the center of the pixels.
21. An image display apparatus comprising:
a liquid crystal display element in which a plurality of display units including at least a pixel that displays an image for a first eyepoint and a pixel that displays an image for a second eyepoint are arranged in a matrix shape;
optical means which distributes light emitted from the pixel that displays the image for the first eyepoint and light emitted from the pixel that displays the image for the second eyepoint in mutually different directions depending on a predetermined signal;
a first control electrode and a second control electrode disposed on each pixel in the display units; and
a plurality of domain regions of which an orientation of liquid crystal molecules is controlled by a diagonal electric field or a lateral electric field formed by the first control electrode and the second control electrode and which have different liquid crystal molecule orientation states,
wherein, assuming that a direction of the light distributed by the optical means is a first direction and a direction orthogonal to the first direction is a second direction, a region in which respective pixels in the display units overlap each other in the second direction is an overlapping region, a case in which a predetermined signal is input into the optical means is a 3D mode, and the other case is a 2D mode,
the optical means comprises an optical principal axis that effectively passes through a center point of the display units and extends in the second direction;
the control electrodes in the overlapping region are disposed in a direction different from the second direction;
the overlapping region is repeatedly bent and disposed to be across the optical principal axis in each of the display units arranged in the second direction;
each of the regions in different liquid crystal molecule orientation states is disposed in each of the display units arranged in the second direction along the overlapping region;
the regions in different liquid crystal molecule orientation states are disposed effectively periodically disposed along the optical principal axis; and
the driving polarity of a pixel is different between the 3D mode and the 2D mode,
wherein
the second control electrode disposed on an upper layer of the first control electrode via an insulating film comprises a plurality of slits extending in the first direction;
any one of the control electrodes is composed of a pixel electrode which can be independently driven in each of the pixels; and
a section between the pixel electrodes adjacent to each other in the first direction tilts in a direction different from the second direction in the overlapping region and is repeatedly disposed across the optical principal axis in each of the display units arranged in the second direction,
wherein
assuming that an angle between the second direction and a liquid crystal initial orientation direction \u03b8LC is (90-\u03b8) degree(s) and an angle between the second direction and a tilt direction between the pixel electrodes is \u03c6, a first region in which an angle between a liquid crystal initial orientation direction \u03b8LC and a liquid crystal driving electric field direction \u03c6E satisfies (90-\u03b8) degree(s), a second region in which an angle between a liquid crystal initial orientation direction \u03b8LC and a liquid crystal driving electric field direction \u03c6E satisfies (\u03c6+\u03b8) degree(s), and a third region in which an angle between a liquid crystal initial orientation direction \u03b8LC and a liquid crystal driving electric field direction \u03c6E satisfies (\u03c6-\u03b8) degree(s) are disposed on at least the optical principal axis and are periodically disposed along the second direction.
22. The image display apparatus according to claim 21, wherein
a display state in the 2D mode leads to a driving polarity in which display units comprising pixels with the same polarity are arranged in the second direction; and
a display state in the 3D mode leads to a driving polarity in which display units comprising pixels with different polarities and display units comprising pixels with the same polarity are alternately arranged in the second direction.
23. A liquid crystal display element in which a plurality of square pixels, which comprises at least two subpixels and in which a plurality of display units comprising subpixels having the same color are arranged, are arranged in a matrix shape, wherein
a control electrode pair comprising a first control electrode and a second control electrode disposed in each pixel in the display units and a plurality of domain regions in different liquid crystal molecule orientation states, of which an orientation of liquid crystal molecules is controlled by a diagonal electric field or a lateral electric field formed by the first control electrode and the second control electrode are included;
assuming that a direction in which the subpixels are arranged is a first direction, a direction orthogonal to the first direction is a second direction, and a region in which respective subpixels in the display units overlap each other in the second direction is an overlapping region,
the control electrodes in the overlapping region are disposed in a direction different from the second direction;
the overlapping region is bent and repeatedly disposed in each of the display units arranged in the second direction; and
each of the regions in different liquid crystal molecule orientation states is disposed in each display unit arranged in the second direction in the overlapping region,
wherein
the second control electrode disposed on an upper layer of the first control electrode via an insulating film comprises a plurality of slits extending in the first direction;
any one of the control electrodes is composed of a pixel electrode which can be independently driven in each of the pixels; and
a section between the pixel electrodes adjacent to each other in the first direction tilts in a direction different from the second direction in the overlapping region and is repeatedly disposed across the optical principal axis in each of the display units arranged in the second direction,
wherein
assuming that an angle between the second direction and a liquid crystal initial orientation direction \u03b8LC is (90-\u03b8) degree(s) and an angle between the second direction and a tilt direction between the pixel electrodes is \u03c6, a first region in which an angle between a liquid crystal initial orientation direction \u03b8LC and a liquid crystal driving electric field direction \u03c6E satisfies (90-\u03b8) degree(s), a second region in which an angle between a liquid crystal initial orientation direction \u03b8LC and a liquid crystal driving electric field direction \u03c6E satisfies (\u03c6+\u03b8) degree(s), and a third region in which an angle between a liquid crystal initial orientation direction \u03b8LC and a liquid crystal driving electric field direction \u03c6E satisfies (\u03c6-\u03b8) degree(s) are disposed on at least the optical principal axis and are periodically disposed along the second direction.
24. A portable device comprising the image display apparatus according to claim 1.
25. A portable device comprising the image display apparatus according to claim 21.