All The Claims

1. A three-dimensional air-adsorbing structure that has a volume, comprising:
(i) a three-dimensional, unitary, skeletal, porous scaffold;
(ii) air-adsorbing material particles; and
(iii) one or more hydrophobic binders that couple air-adsorbing material particles to each other to form agglomerates and couples particles and agglomerates to the scaffold;
wherein the structure has structure openings in the agglomerates and structure openings between agglomerates, such structure openings being open to the outside environment;
wherein the cumulative volume of the structure openings that have an apparent diameter larger than about 5 microns as measured by mercury porosimetry is greater than 0.2 mlg of the air-adsorbing structure.
2. The three-dimensional air-adsorbing structure of claim 1 wherein the air-adsorbing material and the agglomerates are coupled to the scaffold by creating a water-based emulsion of air-adsorbing material, agglomerates of the material, and binder, and then impregnating the scaffold with this emulsion.
3. The three-dimensional air-adsorbing structure of claim 1 wherein the cumulative volume of the structure openings that have an apparent diameter larger than about 0.01 microns as measured by mercury porosimetry is greater than 0.6 mlg of the air-adsorbing structure.
4. The three-dimensional air-adsorbing structure of claim 1 wherein the scaffold comprises an open-cell foam or an electrospun fibrous material.
5. The three-dimensional air-adsorbing structure of claim 4 wherein the open-cell foam has more than about 50 cells per inch and less than about 500 cells per inch.
6. The three-dimensional air-adsorbing structure of claim 1 wherein the scaffold openings make up at least about 90% of the volume of the scaffold.
7. The three-dimensional air-adsorbing structure of claim 1 wherein the scaffold comprises melamine foam or polyurethane foam.
8. The three-dimensional air-adsorbing structure of claim 1 wherein the air-adsorbing material comprises a silicon-based zeolite material.
9. The three-dimensional air-adsorbing structure of claim 1 where the acidity of the air-adsorbing structure, as determined by mixing one part by weight of the structure with five parts by weight of water and measuring the resulting pH, is such that the pH is greater than 4.
10. A three-dimensional air-adsorbing structure that has a volume, comprising:
(i) a three-dimensional, unitary, skeletal, porous scaffold having scaffold openings distributed within its volume, where the scaffold openings make up at least about 90% of the volume of the scaffold;
(ii) air-adsorbing material particles; and
(iii) one or more hydrophobic binders that couple air-adsorbing material particles to each other to form agglomerates and couples particles and agglomerates to the scaffold;
wherein the structure has structure openings in the agglomerates and structure openings between agglomerates, such structure openings being open to the outside environment;
wherein the structure further comprises closed volumes that are not open to the outside environment, and wherein the surface area of the structure openings plus the surface area of closed volumes, as measured by CT scanning with a resolution of at least 5 microns, is at least about 3 mm2mm3 of air-adsorbing structure.
11. The three-dimensional air-adsorbing structure of claim 10 wherein the cumulative volume of the structure openings that have an apparent diameter larger than about 5 microns as measured by mercury porosimetry is greater than 0.2 mlg of the air-adsorbing structure.
12. The three-dimensional air-adsorbing structure of claim 11 wherein the cumulative volume of the structure openings that have an apparent diameter larger than about 0.01 microns as measured by mercury porosimetry is greater than 0.6 mlg of the air-adsorbing structure.
13. The three-dimensional air-adsorbing structure of claim 10 wherein the volume of the structure openings is greater than the volume of the closed volumes.
14. The three-dimensional air-adsorbing structure of claim 10 wherein the scaffold comprises an open-cell foam or an electrospun fibrous material.
15. The three-dimensional air-adsorbing structure of claim 14 wherein the open-cell foam has more than about 50 cells per inch and less than about 500 cells per inch.
16. The three-dimensional air-adsorbing structure of claim 10 wherein the scaffold openings make up at least about 90% of the volume of the scaffold.
17. The three-dimensional air-adsorbing structure of claim 10 wherein the scaffold comprises melamine foam or polyurethane foam.
18. The three-dimensional air-adsorbing structure of claim 10 wherein the air-adsorbing material and the agglomerates are coupled to the scaffold by creating a water-based emulsion of air-adsorbing material, agglomerates of the material, and binder, and then impregnating the scaffold with this emulsion.
19. The three-dimensional air-adsorbing structure of claim 18 wherein the binder comprises an acrylic material or a polyurethane material or a polyacrylate material.
20. The three-dimensional air-adsorbing structure of claim 10 wherein the air-adsorbing material comprises a silicon-based zeolite material.
21. The three-dimensional air-adsorbing structure of claim 10 where the acidity of the air-adsorbing structure, as determined by mixing one part by weight of the structure with five parts by weight of water and measuring the resulting pH, is such that the pH is greater than 4.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A structure, comprising:
(a) a substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface;
(b) N semiconductor regions on the substrate, N being a positive integer,
wherein the N semiconductor regions comprise dopants;

(c) P semiconductor regions on the substrate, P being a positive integer,
wherein the P semiconductor regions do not comprise dopants; and

(d) M interconnect layers on top of the substrate, the N semiconductor regions, and the P semiconductor regions, M being a positive integer,
wherein the M interconnect layers include an inductor,
wherein all of the N semiconductor regions in the reference direction do not overlap the inductor,
wherein all of the P semiconductor regions in the reference direction overlap the inductor, and
wherein a plane perpendicular to the reference direction and intersecting a semiconductor region of the N semiconductor regions intersects a semiconductor region of the P semiconductor regions.
2. The structure of claim 1,
wherein each semiconductor region of the P semiconductor regions is not in direct physical contact with any silicide region, and
wherein each semiconductor region of the N semiconductor regions is in direct physical contact with a silicide region.
3. The structure of claim 1,
wherein the N semiconductor regions comprise N1 semiconductor regions and N2 semiconductor regions, N1 and N2 being positive integers,
wherein N1 plus N2 is equal to N,
wherein the N1 semiconductor regions of the N semiconductor regions comprise p-type dopants, and
wherein the N2 semiconductor regions of the N semiconductor regions comprise n-type dopants.
4. The structure of claim 1, further comprising Q semiconductor regions on the substrate, Q being a positive integer,
wherein the Q semiconductor regions do not comprise dopants, and
wherein the Q semiconductor regions do not overlap the inductor in the reference direction.
5. The structure of claim 1, wherein said inductor resides in a single interconnect layer of the M interconnect layers.
6. The structure of claim 1, wherein said inductor resides in multiple interconnect layers of the M interconnect layers.
7. A structure, comprising:
(a) a substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface;
(b) N semiconductor regions on the substrate, N being a positive integer,
wherein each semiconductor region of the N semiconductor regions is in direct physical contact with a silicide region;

(c) P semiconductor regions on top of the substrate, P being a positive integer,
wherein each semiconductor region of the P semiconductor regions is not in direct physical contact with any silicide region; and

(d) M interconnect layers on top of the substrate, the N semiconductor regions, and the P semiconductor regions, M being a positive integer,
wherein the M interconnect layers include an inductor,
wherein all of the N semiconductor regions in the reference direction do not overlap the inductor,
wherein each semiconductor region of the P semiconductor regions overlaps the inductor in the reference direction, and
wherein a plane perpendicular to the reference direction and intersecting a semiconductor region of the N semiconductor regions intersects a semiconductor region of the P semiconductor regions.
8. The structure of claim 7,
wherein each semiconductor region of the P semiconductor regions does not comprise dopants,
wherein each semiconductor region of the N semiconductor regions comprises dopants,
wherein the N semiconductor regions comprise N1 semiconductor regions and N2 semiconductor regions, N1 and N2 being positive integers,
wherein N1 plus N2 is equal to N,
wherein the N1 semiconductor regions of the N semiconductor regions comprise p-type dopants, and
wherein the N2 semiconductor regions of the N semiconductor regions comprise n-type dopants.
9. The structure of claim 7, further comprising Q semiconductor regions on the substrate, Q being a positive integer,
wherein each semiconductor region of the Q semiconductor regions is not in direct physical contact with any silicide region, and
wherein the Q semiconductor regions do not overlap the inductor in the reference direction.
10. The structure of claim 7, wherein said inductor resides in a single interconnect layer of the M interconnect layers.
11. The structure of claim 7, wherein said inductor resides in multiple interconnect layers of the M interconnect layers.

1. A method of manufacturing a thin film transistor, comprising:
depositing an amorphous silicon film on a substrate;
performing a laser irradiation to the amorphous silicon film so the amorphous film is melted and crystallized to form a polysilicon film;
etching the polysilicon film to form a predetermined pattern;
implanting impurities in the polysilicon film;
forming a gate insulation film on the polysilicon film;
forming a gate electrode on the gate insulation film;
forming a source region and a drain region in the polysilicon film; and
configuring the thin film transistor to operate as a pixel driving transistor of an organic electroluminescent element,
wherein the implanting of the impurities comprises implanting impurities of a p-type and impurities of an n-type into part of the polysilicon film to be used as a channel region of the driving transistor, and the implanting of the p-type impurity comprises implanting a dose of boron from 1\xd71012 to 1\xd71013 atmcm2 into the part of the polysilicon film to be used as the channel region of the driving transistor.
2. The method of claim 1, wherein the etching of the polysilicon film is performed prior to the implanting of the impurities.
3. The method of claim 1, wherein the etching of the polysilicon film is performed subsequent to the implanting of the impurities.
4. The method of claim 1, wherein the implanting of the impurities comprises implanting a dose of boron from 8\xd71012 to 1\xd71013 atmcm2.
5. The method of claim 1, wherein the dosage of the p-type impurity and a dosage of the n-type impurity are in the same order of magnitude.
6. An organic electroluminescent display device comprising a plurality of pixels arranged in a matrix on a substrate, each of the pixels comprising:
a pixel selecting thin film transistor;
an organic electroluminescent element; and
a driving thin film transistor driving the organic electroluminescent element in response to a display signal supplied through the pixel selecting thin film transistor, the driving thin film transistor comprising a channel region that contains impurities of a p-type impurity and an n-type impurity.
7. The organic electroluminescent display device of claim 6, wherein a dosage of the p-type impurity and a dosage of the n-type impurity are in the same order of magnitude.
8. A method of manufacturing a thin film transistor, comprising:
depositing an amorphous silicon film on a substrate; performing a laser irradiation on the amorphous silicon film so the amorphous film is melted and crystallized to form a polysilicon film; etching the polysilicon film to form a predetermined pattern; implanting impurities in the polysilicon film; forming a gate insulation film on the polysilicon film; forming a gate electrode on the gate insulation film; forming a source region and a drain region in the polysilicon film; and configuring the thin film transistor to operate as a pixel driving transistor of an organic electroluminescent element, wherein the implanting of the impurities comprises implanting impurities of p-type and impurities of n-type in to part of the polysilicon film to be used as a channel region of the driving transistor, and the implanting of the comprises implanting a dose of phosphorus from 1\xd71012 to 3\xd71012 atmcm2 into part of the polysilicon film to be used as a channel region of the driving transistor.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A test apparatus for semiconductor element structures on a semiconductor wafer, comprising a needle card which holds test probes within a test area located within a test area housing holding the needle card, wherein the test area is pressurized such that the test area housing floats on a gas cushion on the semiconductor wafer, wherein the test area housing comprises at least three distance sensors which detect the width of a gap between the test area housing and a semiconductor wafer upper face, and interact with at least three gap control elements, which are supported against a stiff test apparatus plate and maintain a predetermined gap width, and wherein the semiconductor wafer is arranged on a test table of the test apparatus.
2. The test apparatus according to claim 1, wherein the needle card is mechanically connected to the test area housing via needle card control elements.
3. The test apparatus according to claim 2, wherein the test area housing has a transparent test area covering disk for the area of the test probes.
4. The test apparatus according to claim 3, wherein the test apparatus plate is horizontally aligned and can be moved vertically, and has a central opening in the area of the transparent test area covering disk.
5. The test apparatus according to claim 2, wherein the needle card control elements have piezoelectric actuators.
6. The method according to claim 5, wherein different pressure differences are used between an internal pressure in the test area at different positions in the area of the gap and the external pressure, in order to readjust the gap width.
7. The method according to claim 5, wherein air, SF6 andor C02 at a pressure P of between 1.2\xd7105 Pa\u2266P\u22665\xd7105 Pa are used for the gas cushion in the test area.
8. The method according to claim 5, wherein the pressure difference between the external pressure and the pressure in at least one suction line is measured, and is adjusted such that the gas which is flowing through the gap is not emitted to the surrounding area.
9. The method according to claim 5, wherein the internal pressure in the test area and the gap width are matched to one another in such a manner that the breakdown voltage of the gas in the gap is greater than the maximum test voltage which can be used for the semiconductor element structure to be tested.
10. The test apparatus according to claim 1, wherein the test area housing has a housing wall which surrounds the test area and whose housing wall lower face floats above the semiconductor wafer upper face and the gap.
11. The test apparatus according to claim 1, wherein the test area housing has at least one gas inlet.
12. The test apparatus according to claim 1, wherein the test area housing has a gas pressure sensor for the test area, which is operatively connected to a gas pressure regulator.
13. The test apparatus according to claim 1, wherein the test area housing is resistant to high voltages and high currents.
14. The test apparatus according to claim 1, wherein the gap control elements have piezoelectric actuators.
15. The test apparatus according to claim 1, wherein the test table can be aligned horizontally and can be moved in two axis directions and in a rotation direction, arranged horizontally.
16. The test apparatus according to claim 1, wherein the gap width can be adjusted in micrometers between 5\u03bcm\u2266b\u2266120 \u03bcm by means of the gap control elements.
17. The test apparatus according to claim 1, wherein the housing wall has an annular suction groove in the area of its housing wall lower face, which suction groove is connected to a suction line in order to recover the gas emerging from the test area through the gap.
18. The test apparatus according to claim 1, wherein the housing wall has a plurality of grooves, arranged one behind the other, in the area of its lower face.
19. The test apparatus according to claim 1, wherein the housing wall has an annular elastomer buffer in the area of its lower face.
20. The test apparatus according to claim 1, wherein pressure sensors are arranged in the suction line and on the test housing, outside the test area.
21. The test apparatus according to claim 1, wherein the housing wall has an annular groove in the area of its lower face, within the test area, which annular groove is connected to the gas inlet and is designed in such a manner that a flow channel, which is directed obliquely outwards, is formed in the gap.
22. A test method using the test apparatus according to claims 1, wherein the method comprises the following method steps:
arranging a stiff test apparatus plate with a test housing which is held by gap control elements horizontally in a test apparatus rack;
applying a semiconductor wafer with semiconductor element structures to be tested to a horizontally aligned test table of the test apparatus;
moving the test apparatus plate and the test table vertically towards one another, wherein the semiconductor wafer and the test housing being aligned parallel except for a predetermined safety gap between the semiconductor wafer and the test housing for rough adjustment;
roughly adjusting one of the semiconductor element structures of the semiconductor wafer and the corresponding test probes of the needle card of the test housing, wherein the test table being rotated and moved laterally;
switching the gas supply for the test area on, forming a gas cushion in which the test housing, which floats above the semiconductor wafer, automatic gap width regulation is switched on with the aid of distance sensors and gap width control elements, which are supported on the stiff test apparatus plate, to a gap width, without the test probes making contact;
finely adjusting the semiconductor element structure of the semiconductor wafer and the corresponding test probes of the needle card of the test housing, wherein the test table being rotated and moved laterally;
testing the finely-adjusted semiconductor element structure, wherein the test points being placed on the semiconductor element structures to be tested.
23. The method according to claim 22, wherein the test probes make contact, wherein the gap width is reduced further by means of the gap width control elements.
24. The method according to claim 22, wherein the test probes make contact, with additional, independent needle card control elements being operated.