All The Claims

1. A programmable termination shunt comprising:
a multi-frequency shunt circuit comprising a plurality of selectable shunt frequencies defined by banks of inductor-capacitor circuit branches each having an associated inductance and capacitance;
a switching circuit connected to the multi-frequency shunt circuit; and
a processor coupled to the multi-frequency shunt circuit via said switching circuit, said processor adapted to set a termination frequency of the shunt by selecting a switch setting within the switching circuit that selects one of said selectable shunt frequencies in the multi-frequency shunt circuit.
2. The programmable termination shunt of claim 1, wherein the multi-frequency shunt circuit is adapted to be coupled between rails of a railroad track and said processor is adapted to receive a termination frequency programming signal from at least one of the rails.
3. The programmable termination shunt of claim 2, wherein the termination frequency programming signal comprises a new termination frequency.
4. The programmable termination shunt of claim 2, wherein the termination frequency programming signal comprises a desired inductance and capacitance of said multi-frequency shunt circuit.
5. The programmable termination shunt of claim 2, wherein the termination frequency programming signal comprises a switch setting for the switching circuit.
6. The programmable termination shunt of claim 2, wherein said processor and said multi-frequency shunt circuit are powered by signals transmitted over the rails.
7. The programmable termination shunt of claim 6, wherein said shunt further comprises an energy storage element for storing power transmitted over the rails.
8. The programmable termination shunt of claim 1, wherein said processor is adapted to receive a termination frequency programming signal from a wireless communication link.
9. The programmable termination shunt of claim 8, wherein the termination frequency programming signal comprises one of a new termination frequency, a desired inductance and capacitance of components within said multi-frequency shunt circuit or a switch setting for said switching circuit.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A patterned article, comprising:
a substrate;
a continuous ultra-thin metal-containing film or film stack disposed on a surface of the substrate; and
a plurality of discrete dewetted metal-containing islands disposed on a surface of the continuous ultra-thin metal-containing film or film stack;
wherein the plurality of discrete metal-containing dewetted islands have an average height of about 5 nanometers to about 300 nanometers, an average longest lateral cross-sectional dimension of about 10 nanometers to about 1000 nanometers, and are randomly oriented on the surface of the continuous ultra-thin metal-containing film or film stack so as to cover less than or equal to about 0.5 of an area fraction of the surface of the continuous ultra-thin metal-containing film or film stack.
2. The patterned article of claim 1, wherein the continuous ultra-thin metal-containing film or film stack has an average thickness of less than or equal to about 5 nanometers.
3. The patterned article of claim 1, wherein the substrate has an average thickness of about 0.02 millimeters to about 2 millimeters.
4. The patterned article of claim 1, wherein the plurality of discrete dewetted metal-containing islands comprise a metal in its elemental form or a metal that is a constituent of an alloy.
5. The patterned article of claim 1, wherein the average height of the plurality of discrete metal-containing dewetted islands is about 20 nanometers to about 100 nanometers.
6. The patterned article of claim 1, wherein the average longest lateral cross-sectional dimension of the plurality of discrete metal-containing dewetted islands is about 30 nanometers to about 200 nanometers.
7. The patterned article of claim 1, wherein the area fraction covered by the plurality of discrete metal-containing dewetted islands is less than or equal to about 0.25 of the surface of the continuous ultra-thin metal-containing film or film stack.
8. The patterned article of claim 1, wherein the patterned article is at least a portion of an anti-reflection coating, a metal mask, a localized surface plasmon resonance structure, a catalyst, a catalyst support, an anti-virus coating, or an antibacterial coating.
9. A patterned article, comprising
a strengthened alkali aluminosilicate glass substrate;
a continuous ultra-thin metal-containing film or film stack disposed on a surface of the strengthened alkali aluminosilicate glass substrate, wherein the continuous ultra-thin metal-containing film or film stack has an average thickness of less than or equal to about 5 nanometers; and
a plurality of discrete dewetted metal-containing islands disposed on a surface of the continuous ultra-thin metal-containing film or film stack;
wherein the plurality of discrete metal-containing dewetted islands have an average height of about less than or equal to about 130 nanometers, an average longest lateral cross-sectional dimension of about 50 nanometers to about 200 nanometers, and are randomly oriented on the surface of the continuous ultra-thin metal-containing film or film stack so as to cover less than or equal to about 0.1 of an area fraction of the surface of the continuous ultra-thin metal-containing film or film stack.
10. The patterned article of claim 9, wherein the plurality of discrete dewetted metal-containing islands comprise a metal in its elemental form or a metal that is a constituent of an alloy.

1. An apparatus comprising:
one or more storage devices storing machine readable code; and
one or more processors executing the machine readable code, the machine readable code comprising:
sound setting code that;
detects use of a microphone, and
sets sound characteristics that are suitable for conversation in response to detecting the use of the microphone; and

sound processing code that processes sound on the basis of the sound characteristics set by the sound setting code.
2. The apparatus of claim 1, wherein the sound characteristics include equalizing characteristics that are suitable for conversation.
3. The apparatus of claim 2, wherein the equalizing characteristics that are suitable for conversation comprise two peaks.
4. The apparatus of claim 1, wherein the sound characteristics comprise sound characteristics for a speaker.
5. The apparatus of claim 4, wherein the sound characteristics for the speaker comprise one or more of a speaker mute and a speaker volume.
6. The apparatus of claim 1, wherein the sound characteristics comprise sound characteristics for a microphone.
7. The apparatus of claim 6, wherein the sound characteristics for the microphone comprise one or more of a microphone mute and a microphone volume.
8. The apparatus of claim 1, wherein the sound setting code further detects that the use of the microphone is by a VOIP application program sets the sound characteristics that are suitable for conversation in response to the detection of the use of the microphone by the VOIP application program.
9. The apparatus of claim 1, wherein the sound setting code further detects an end of the use of the microphone and sets the sound characteristics to a previous setting in response to the detection of the end of the use of the microphone.
10. The apparatus of claim 1, wherein the sound setting code further detects an end of the use of the microphone and sets the sound characteristics to a normal setting in response to the detection of the end of the use of the microphone.
11. The apparatus of claim 1, wherein the sound characteristics comprise an echo cancelling function.
12. A method comprising:
detecting use of a microphone;
setting sound characteristics that are suitable for conversation in response to detecting the use of the microphone; and
processing sound on the basis of the sound characteristics set in the sound characteristics setting step.
13. The method of claim 12, wherein the sound characteristics include equalizing characteristics.
14. The method of claim 13, wherein the equalizing characteristics comprise two peaks.
15. The method of claim 12, wherein the sound characteristics comprise sound characteristics for a speaker.
16. The method of claim 15, wherein the sound characteristics for the speaker comprise one or more of a speaker mute and a speaker volume.
17. The apparatus of claim 12, wherein the sound characteristics comprise sound characteristics for a microphone.
18. The method of claim 17, wherein the sound characteristics for the microphone comprise one or more of a microphone mute and a microphone volume.
19. The method of claim 12, further comprising detecting that the use of the microphone is by a VOIP application program and wherein the sound characteristics are set in response to the detecting the use of the microphone by the VOIP application program.
20. A computer program product comprising a storage device storing machine readable code executed by a processor to perform the operations of:
detecting use of a microphone;
setting sound characteristics that are suitable for conversation in response to detecting the use of the microphone; and
processing sound on the basis of the sound characteristics set in the sound characteristics setting step.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor substrate, comprising:
a sapphire substrate including an a-plane main surface and comprising a groove in a surface thereof, the groove including side surfaces and a bottom surface; and
a Group III nitride semiconductor layer formed on the sapphire substrate,
wherein both side surfaces of the groove assume a c-plane of sapphire,
wherein an axis perpendicular to one of the side surfaces of the groove of the Group III nitride semiconductor layer assumes a c-axis of Group III nitride semiconductor, and
wherein a plane parallel to the main surface of the sapphire substrate of the Group III nitride semiconductor layer assumes an m-plane of Group III nitride semiconductor.
2. A semiconductor substrate, comprising:
a sapphire substrate including an m-plane main surface and comprising a groove in a surface thereof, the groove including side surfaces and a bottom surface; and
a Group III nitride semiconductor layer formed on the sapphire substrate;
wherein both side surfaces of the groove assumes a c-plane of sapphire;
wherein an axis perpendicular to one of the side surfaces of the groove of the Group III nitride semiconductor layer assumes a c-axis of Group III nitride semiconductor; and
wherein a plane parallel to the main surface of the sapphire substrate of the Group III nitride semiconductor layer assumes an a-plane of Group III nitride semiconductor.
3. A semiconductor substrate, comprising:
a sapphire substrate including a c-plane main surface and comprising a groove in a surface thereof, the groove including side surfaces and a bottom surface; and
a Group III nitride semiconductor layer formed on the sapphire substrate,
wherein both side surfaces of the groove assumes an a-plane of sapphire,
wherein an axis perpendicular to one of the side surfaces of the groove of the Group III nitride semiconductor layer assumes a c-axis of Group III nitride semiconductor, and
wherein a plane parallel to the main surface of the sapphire substrate of the Group III nitride semiconductor layer assumes an a-plane of Group III nitride semiconductor.
4. A semiconductor substrate according to claim 1, wherein the surface of the sapphire substrate is nitrided, and the Group III nitride semiconductor layer is formed without depositing a buffer layer.
5. A semiconductor substrate according to claim 2, wherein the surface of the sapphire substrate is nitrided, and the Group III nitride semiconductor layer is formed without depositing a buffer layer.
6. A semiconductor substrate according to claim 3, wherein the surface of the sapphire substrate is nitrided, and the Group III nitride semiconductor layer is formed without depositing a buffer layer.
7. A semiconductor substrate according to claim 1, wherein the sapphire substrate comprises a buffer film formed along an entire surface thereof, and the Group III nitride semiconductor layer is formed via a buffer film on the sapphire substrate.
8. A semiconductor substrate according to claim 2, wherein the sapphire substrate comprises a buffer film formed along an entire surface thereof, and the Group III nitride semiconductor layer is formed via a buffer film on the sapphire substrate.
9. A semiconductor substrate according to claim 3, wherein the sapphire substrate comprises a buffer film formed along an entire surface thereof, and the Group III nitride semiconductor layer is formed via a buffer film on the sapphire substrate.
10. A semiconductor substrate according to claim 1, wherein the groove is formed in a stripe pattern.
11. A semiconductor substrate according to claim 2, wherein the groove is formed in a stripe pattern.
12. A semiconductor substrate according to claim 3, wherein the groove is formed in a stripe pattern.
13. A semiconductor substrate according to claim 7, wherein the buffer film comprises AlxGa1-xN (0\u2266x\u22661).
14. A semiconductor substrate according to claim 8, wherein the buffer film comprises AlxGa1-xN (0\u2266x\u22661).
15. A semiconductor substrate according to claim 9, wherein the buffer film comprises AlxGa1-xN (0\u2266x\u22661).
16. A semiconductor substrate according to claim 13, wherein the buffer film has a thickness of 150 \u212b or less.
17. A semiconductor substrate according to claim 14, wherein the buffer film has a thickness of 150 \u212b or less.
18. A semiconductor substrate according to claim 15, wherein the buffer film has a thickness of 150 \u212b or less.