All The Claims

1. A semiconductor device structure, comprising:
a substrate;
a first dielectric layer, disposed on the substrate;
a second dielectric layer, disposed on the first dielectric layer, wherein a Young’s modulus of the second dielectric layer is smaller than a Young’s modulus of the first dielectric layer;
a semiconductor layer, disposed on the first dielectric layer or the second dielectric layer;
a first conductive layer, disposed adjacently to the first dielectric layer or the second dielectric layer; and
a second conductive layer, disposed on the second dielectric layer or the first dielectric layer.
2. The semiconductor device structure according to claim 1, wherein the first dielectric layer comprises a first patterned dielectric film and a second patterned dielectric film, the second patterned dielectric film is disposed on the first patterned dielectric film, the semiconductor layer and the first conductive layer are separated via the first patterned dielectric film, the second conductive layer is disposed on the second dielectric film and is electrically connected to at least one of the semiconductor layer and the first conductive layer via a contact hole.
3. The semiconductor device structure according to claim 2, wherein the first patterned dielectric film and the second patterned dielectric film are single-layer or multi-layer structures.
4. The semiconductor device structure according to claim 2, wherein the second dielectric layer is a single-layer or multi-layer structure.
5. The semiconductor device structure according to claim 2, wherein the first conductive layer is disposed under the semiconductor layer; the semiconductor layer, the first conductive layer, the second conductive layer and the first dielectric layer form a bottom-gate transistor; the semiconductor layer is an active layer of the bottom-gate transistor, and the first conductive layer is a gate electrode of the bottom-gate transistor.
6. The semiconductor device structure according to claim 2, wherein the first conductive layer is disposed on the semiconductor layer; the semiconductor layer, the first conductive layer, the second conductive layer and the first dielectric layer form a top-gate transistor; the semiconductor layer has functions of an active layer, and the first conductive layer has functions of a gate electrode.
7. The semiconductor device structure according to claim 2, wherein the semiconductor layer, the first conductive layer and the first dielectric layer form a capacitor.
8. The semiconductor device structure according to claim 7, wherein the capacitor is formed by the first conductive layer, the semiconductor layer and the first patterned dielectric film of the first dielectric layer.
9. The semiconductor device structure according to claim 1, wherein the first conductive layer and the second conductive layer are separated from each other via the second dielectric layer; the first conductive layer, the second conductive layer and the second dielectric layer form a capacitor.
10. The semiconductor device structure according to claim 1, wherein the first conductive layer is disposed on the substrate, the second dielectric layer or the first dielectric layer has an opening revealing the first conductive layer, and the first conductive layer is electrically connected to the second conductive layer.
11. The semiconductor device structure according to claim 2, wherein the Young’s modulus of the first patterned dielectric film is between 1 GPa and 450 GPa, and the Young’s modulus of the second dielectric layer is between 0.1 MPa and 80 GPa.
12. The semiconductor device structure according to claim 11, wherein a leakage current density of the first patterned dielectric film is smaller than 10\u22127 Acm2 when electric field strength is 1 MVcm.
13. A method for manufacturing a semiconductor device structure, comprising:
providing a substrate;
forming a first dielectric layer on the substrate;
forming a second dielectric layer on the first dielectric layer, wherein a Young’s modulus of the second dielectric layer is smaller than a Young’s modulus of the first dielectric layer;
forming a semiconductor layer on the first dielectric layer or the second dielectric layer;
forming a first conductive layer, wherein the first conductive layer is adjacent to the first dielectric layer or the second dielectric layer; and
forming a second conductive layer on the second dielectric layer or the first dielectric layer.
14. The method according to claim 13, wherein the first dielectric layer comprises a first patterned dielectric film and a second patterned dielectric film; the second dielectric film is disposed on the first patterned dielectric film; the semiconductor layer and the first conductive layer are separated from each other via the first patterned dielectric film; the second conductive layer is disposed on the second dielectric layer or the first dielectric layer, and is electrically connected to at least one of the semiconductor layer and the first conductive layer via a contact hole.
15. The method according to claim 14, wherein the first patterned dielectric film and the second patterned dielectric film are single-layer or multi-layer structures.
16. The method according to claim 13, wherein the second dielectric layer is a single-layer or multi-layer structure.
17. The method according to claim 14, wherein the first conductive layer is disposed under the semiconductor layer; the semiconductor layer, the first conductive layer, the second conductive layer and the first dielectric layer form a bottom-gate transistor; the semiconductor layer has functions of an active layer, and the first conductive layer has functions of a gate electrode.
18. The method according to claim 14, wherein the first conductive layer is disposed on the semiconductor layer; the semiconductor layer, the first conductive layer, the second conductive layer and the first dielectric layer form a top-gate transistor; the semiconductor layer has functions of an active layer, and the first conductive layer has functions of a gate electrode.
19. The method according to claim 14, wherein the semiconductor layer, the first conductive layer and the first dielectric layer form a capacitor.
20. The method according to claim 19, wherein the capacitor is formed by the first conductive layer, the semiconductor layer and the first patterned dielectric film of the first dielectric layer.
21. The method according to claim 13, wherein the first conductive layer and the second conductive layer are separated from each other via the second dielectric layer; the second conductive layer, the first conductive layer and the second dielectric layer form a capacitor.
22. The method according to claim 13, wherein the first conductive layer is disposed on the substrate, the second dielectric layer or the first dielectric layer has an opening revealing the first conductive layer, and the first conductive layer is electrically connected to the second conductive layer.
23. The method according to claim 14, wherein the Young’s modulus of the first patterned dielectric film is between 1 GPa and 450 GPa, and the Young’s modulus of the second dielectric layer is between 0.1 MPa and 80 GPa.
24. The method according to claim 14, wherein a leakage current density of the first patterned dielectric film is smaller than 10\u22127 Acm2 when electric field strength is 1 MVcm.
25. A semiconductor device structure, comprising:
a substrate;
a first dielectric layer, disposed on the substrate, comprising a first patterned dielectric film and a second patterned dielectric film;
a second dielectric layer, disposed on the first dielectric layer, wherein a Young’s modulus of the second dielectric layer is smaller than a Young’s modulus of the first dielectric layer;
a first semiconductor layer, disposed on the substrate;
a first conductive layer, disposed on the first patterned dielectric film;
a second semiconductor layer, disposed on the second patterned dielectric film, wherein the first semiconductor layer and the first conductive layer are disposed at two opposite sides of the first patterned dielectric film, and the first conductive layer and the second semiconductor layer are disposed at two opposite sides of the second patterned dielectric film; and
a second conductive layer, disposed on the second dielectric layer, being electrically connected to the first semiconductor layer, the second semiconductor layer or the first conductive layer via a contact hole.
26. The semiconductor device structure according to claim 25, wherein the first semiconductor layer, the first conductive layer and the second conductive layer form a top-gate transistor; the first conductive layer, the second semiconductor layer and the second conductive layer form a bottom-gate transistor; the first conductive layer has functions of a gate layer, and the first semiconductor layer and the second semiconductor layer have functions of an active layer.
27. The semiconductor device structure according to claim 25, wherein the first semiconductor layer, the first conductive layer and the first patterned dielectric film form a capacitor; the first conductive layer, the second semiconductor layer and the second patterned dielectric film form another capacitor.
28. The semiconductor device structure according to claim 27, wherein the first semiconductor layer and the second semiconductor layer have the same potential.
29. The semiconductor device structure according to claim 25, wherein the first dielectric layer is a multi-layer structure.
30. The semiconductor device structure according to claim 25, wherein the second dielectric layer is a single-layer or multi-layer structure.
31. A pixel structure, comprising:
at least two pixel electrodes; and
a driving transistor, wherein the pixel electrodes are connected to an end electrode of the driving transistor; the driving transistor comprising:
a substrate;
a first dielectric layer, disposed on the substrate, comprising a first patterned dielectric film and a second patterned dielectric film;
a second dielectric layer, disposed on the first dielectric layer, wherein a Young’s modulus of the second dielectric layer is smaller than a Young’s modulus of the first patterned dielectric film or the second patterned dielectric film;
a semiconductor layer, disposed adjacently to the first dielectric layer or the second dielectric layer;
a first conductive layer, disposed adjacently to the first dielectric layer or the second dielectric layer, wherein the semiconductor layer and the first conductive layer are disposed at two opposite sides of the first patterned dielectric film; and
a second conductive layer, disposed on the second dielectric layer, electrically connected to the semiconductor layer or the first conductive layer via a contact hole;

wherein, the driving transistor drives the pixel electrodes to generate a pixel.
32. The pixel structure according to claim 31, wherein the second dielectric layer is a single-layer or multi-layer structure.
33. A pixel structure, comprising:
at least two pixel electrodes; and
a driving transistor, wherein the pixel electrodes are connected to an end electrode of the driving transistor; the driving transistor comprising:
a substrate;
a semiconductor layer, disposed on the substrate;
a dielectric layer, disposed on the semiconductor layer;
a first conductive layer, wherein the first conductive layer and the semiconductor layer are disposed at two opposite sides of the dielectric layer; and
a second conductive layer, disposed on the dielectric layer, electrically connected to the semiconductor layer or the first conductive layer via a contact hole;

wherein, the driving transistor drives the pixel electrodes to generate a pixel.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A thermoplastic resin composition comprising 2.5 to 6.5 wt. % of a styrene-based elastomer and 93.5 to 97.5 wt. % of tungsten powder.
2. A thermoplastic resin molded article comprising 2.5 to 6.5 wt. % of a styrene-based elastomer and 93.5 to 97.5 wt. % of tungsten powder.
3. A thermoplastic resin molded article consisting essentially of 2.5 to 6.5 wt. % of a styrene-based elastomer, 93.5 to 97.5 wt. % of tungsten powder and, optionally, at least one member selected from the group consisting of steel, brass, copper, aluminum, nickel, silver, zinc, iron oxide, copper oxide, aluminum oxide, barium sulfate, zinc oxide and molybdenum sulfide.
4. A thermoplastic resin composition consisting of 2.5 to 15 wt. % of a styrene-based thermoplastic elastomer and 85 to 97.5 wt. % of tungsten powder.
5. A thermoplastic resin molded article consisting of 2.5 to 15 wt. % of a styrene-based thermoplastic elastomer and 85 to 97.5 wt. % of tungsten powder.
6. A thermoplastic resin molded article consisting of 2.5 to 15 wt. % of a styrene-based thermoplastic elastomer, 85 to 97.5 wt. % of tungsten powder and, optionally, at least one member selected from the group consisting of steel, brass, copper, aluminum, nickel, silver, zinc, iron oxide, copper oxide, aluminum oxide, barium sulfate, zinc oxide and molybdenum sulfide.

1. An emitter package, comprising:
a casing comprising a cavity extending into the interior of said casing from a top surface of said casing;
electrically conductive bond pads integral to said casing, wherein a first set of said bond pads comprises chip carrier parts, and a second set of said bond pads comprises connection parts;
a plurality of light emitting devices arranged on said first set of bond pads, with said light emitting devices and portions of said bond pads exposed through said cavity;
a plurality of electrodes disposed at least on the bottom surface of said casing; and
through-holes integral to each of said bond pads, said through-holes extending from said bond pads through said casing to provide electrical paths between said bond pads and said electrodes.
2. The emitter package of claim 1, wherein said electrodes comprise:
a plurality of electrically conductive cathode parts; and
a corresponding plurality of electrically conductive anode parts separate from said cathode parts;
wherein each of said cathode and anode parts are electrically connected to one of said light emitting devices.
3. The emitter package of claim 1, wherein said light emitting devices are adapted to be energized to produce, in combination, a substantially full range of colors.
4. The emitter package of claim 2, wherein each of said light emitting devices comprises at least two contacts, one of which is electrically coupled to at least one of said cathode parts, and the other of which is electrically coupled to at least one of said anode parts.
5. The emitter package of claim 1, wherein said bond pads and said electrodes are comprised of an electrically conductive metal or metal alloy.
6. The emitter package of claim 5, wherein said electrodes are comprised of Ag or an Ag alloy.
7. The emitter package of claim 1, wherein said light emitting devices comprise red, blue and green LEDs.
8. The emitter package of claim 1, wherein each of said light emitting devices is attached to one of said chip carrier parts via solder and one of said connection parts via a wire bond.
9. The emitter package of claim 1, wherein said casing is comprised of white ceramic, with the white ceramic aiding in the color mixing of said light emitting devices.
10. The emitter package of claim 1, wherein said bond pads comprise features that cooperate with said casing to provide a robust connection between said bond pads and said casing to improve the structural integrity of the overall package.
11. The emitter package of claim 10, wherein said features comprise one or more of: through-holes, cuts, gaps between adjacent portions of said bond pads, and indentations in portions of said bond pads.
12. The emitter package of claim 1, further comprising an encapsulant over said package.
13. The emitter package of claim 12, wherein said encapsulant is UV-resistant and comprises silicone.
14. The emitter package of claim 12, wherein the top of said encapsulant is substantially flat.
15. The emitter package of claim 1, wherein said cavity comprises a reflector.
16. The emitter package of claim 1, wherein the height of said package is less than or equal to 0.9 mm.
17. The emitter package of claim 1, further comprising one or more Zener diodes electrically connected to said exposed bond pad portions and said light emitting devices.
18. The emitter package of claim 1, wherein one or more of the side surfaces of said package comprise U-shaped indentations to reduce the amount of electrode material on said side surfaces.
19. The emitter package of claim 1, wherein said casing is plated by said electrodes on portions of its bottom surface and portions of one or more of its side surfaces.
20. The emitter package of claim 19, wherein said plated portions further comprise solder pads such that said solder pads are disposed on both the bottom and side surfaces of said package.
21. The emitter package of claim 20, wherein said solder pads at the bottom surface of said casing connect said package to a printed circuit board, and said solder pads at the side surfaces of said casing connect said package to one or more adjacent packages.
22. A ceramic emitter package, comprising:
a white casing comprising a cavity extending into the interior of said casing from a top surface of said casing;
electrically conductive bond pads integral to said casing, wherein a first set of said bond pads comprises chip carrier parts, and a second set of said bond pads comprises connection parts;
a plurality of light emitting devices arranged on said first set of bond pads, with said light emitting devices and portions of said bond pads exposed through said cavity;
a plurality of electrodes disposed at least on the bottom surface of said casing;
U-shaped indentations in one or more of the side surfaces of said casing; and
features integral to one or more of said bond to improve the connection between said bond pads and said casing.
23. The emitter package of claim 22, further comprising through-holes integral to each of said bond pads, said through-holes extending from said bond pads through said casing to provide electrical paths between said bond pads and said electrodes.
24. The emitter package of claim 22, wherein said electrodes comprise:
a plurality of electrically conductive cathode parts; and
a corresponding plurality of electrically conductive anode parts separate from said cathode parts, each of said cathode parts and anode parts electrically connected to one of said bond pads;
wherein each of said light emitting devices is attached to one of said chip carrier parts via solder and one of said connection parts via a wire bond, with through-holes in said bond pads providing electrical paths between said bond pads and said electrodes.
25. The emitter package of claim 22, wherein said light emitting devices comprise multiple color LEDs adapted to be energized to produce, in combination, a substantially full range of colors.
26. The emitter package of claim 22, wherein said electrodes are comprised of Ag or an Ag alloy.
27. The emitter package of claim 22, wherein said features comprise one or more of: through-holes, cuts, gaps between adjacent portions of said bond pads, and indentations in portions of said bond pads.
28. The emitter package of claim 22, further comprising a silicone encapsulant over said package, with the top of said encapsulant being substantially flat.
29. The emitter package of claim 22, wherein said cavity comprises a reflector.
30. The emitter package of claim 22, wherein the height of said package is less than or equal to 1.0 mm.
31. The emitter package of claim 22, wherein said casing is plated by said electrodes on portions of its bottom surface and portions of one or more of its side surfaces, with said plated portions further comprising solder pads such that said solder pads are disposed on both the bottom and side surfaces of said package, wherein said solder pads at the bottom surface of said casing connect said package to a printed circuit board, and said solder pads at the side surfaces of said casing connect said package to one or more adjacent packages.
32. A low profile emitter package, comprising:
a white ceramic casing comprising a cavity extending into the interior of said casing from a top surface of said casing;
electrically conductive bond pads integral to said casing, wherein a first set of said bond pads comprises chip carrier parts, and a second set of said bond pads comprises connection parts;
a plurality of LEDs arranged on said first set of bond pads, with said LEDs and portions of said bond pads exposed through said cavity;
a plurality of electrodes disposed at least on the bottom surface of said casing; and
through-holes integral to each of said bond pads, said through-holes extending from said bond pads through said casing to provide electrical paths between said bond pads and said electrodes;
wherein the height of said package is less than or equal to 1.0 mm.
33. The emitter package of claim 32, wherein one or more of the side surfaces of said casing comprise U-shaped indentations to reduce the amount of electrode material on said side surfaces.
34. The emitter package of claim 32, wherein said electrodes comprise:
a plurality of electrically conductive cathode parts; and
a corresponding plurality of electrically conductive anode parts separate from said cathode parts, each of said cathode parts and anode parts electrically connected to one of said LEDs;
wherein each of said LEDs is attached to one of said chip carrier parts via solder and one of said connection parts via a wire bond.
35. The emitter package of claim 32, wherein said LEDs comprise red, blue and green LEDs adapted to be energized to produce, in combination, a substantially full range of colors.
36. The emitter package of claim 32, further comprising features in said bond pads to improve the connection between said bond pads and said casing, wherein said features comprise one or more of: through-holes, cuts, gaps between adjacent portions of said bond pads, and indentations in portions of said bond pads.
37. The emitter package of claim 32, wherein said casing is plated by said electrodes on portions of its bottom surface and portions of one or more of its side surfaces, with said plated portions further comprising solder pads such that said solder pads are disposed on both the bottom and side surfaces of said package, wherein said solder pads at the bottom surface of said casing connect said package to a printed circuit board, and said solder pads at the side surfaces of said casing connect said package to one or more adjacent packages.
38. An LED display, comprising:
a substrate carrying an array of emitter packages, each of said emitter packages comprising:
a white ceramic casing comprising a cavity extending into the interior of said casing from a top surface of said casing;
electrically conductive bond pads integral to said casing, wherein a first set of said bond pads comprises chip carrier parts, and a second set of said bond pads comprises connection parts;
a plurality of LEDs arranged on said first set of bond pads, with said LEDs and portions of said bond pads exposed through said cavity;
a plurality of electrodes disposed at least on the bottom surface of said casing; and
through-holes integral to each of said bond pads, said through-holes extending from said bond pads through said casing to provide electrical paths between said bond pads and said electrodes; and

electrically connected drive circuitry to selectively energize said array for producing visual images on said display.
39. The display of claim 38, wherein each of said LEDs in said emitter packages is driven by a respective electrical signal, with each of said emitter packages defining one pixel of said display.
40. The display of claim 38, wherein said bond pads comprise features that cooperate with said casing to provide a robust connection between said bond pads and said casing to improve the structural integrity of each package, with said features comprising one or more of: through-holes, cuts, gaps between adjacent portions of said bond pads, and indentations in portions of said bond pads.
41. The display of claim 38, wherein the height of each said package is less than or equal to 1.0 mm.
42. The display of claim 38, wherein the casing of each said package is plated by said electrodes on portions of its bottom surface and portions of one or more of its side surfaces, with each plated portion further comprising solder pads such that said solder pads are disposed on both the bottom and side surfaces of each said package such that said solder pads at the bottom surface of said casing connect each said package to a printed circuit board, and said solder pads at the side surfaces of each said casing connect each package to one or more adjacent packages to form a densely-packed display.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A polymorphic form I of idazoxan wherein the X-Ray spectra comprises specific peaks at 4.0200, 6.6400, 6.9000, 7.0800, 8.0800, 9.0000, 9.9600, 10.8400, 11.7200, 12.1400, 12.3800, 12.9800, 13.3000, 13.5200, 14.9000, 15.0600. 15.2400 and 21.4000 degrees \u03b8 and the differential thermal analysis thermogram exhibiting a single maximum value at approximately 207.5\xb10.2.
2. A polymorphic form I of idazoxan wherein the X-Ray spectra comprises specific peaks at 4.0200, 6.6400, 6.9000, 7.0800, 8.0800, 9.0000, 9.9600, 10.8400, 11.7200, 12.1400, 12.3800, 12.9800, 13.3000, 13.5200, 14,9000, 15.0600, 15.2400 and 21.4000 degrees \u03b8 and lacking at least one peak at 4.0200, 6.6400, 6.9000, 7.0800, 8.0800, 9.0000, 9.9600, 9.9600, 10.8400, 11.7200, 12.1400, 12.3800, 12.9800, 13.3000, 13.5200, 14.9000, 15.0600, 15.2400 and 21.4000 degrees \u03b8 and the differential thermal analysis thermogram exhibiting a single maximum value at approximately 207.5\xb10.2.