All The Claims

1. A method for performing memory prefetching, said method comprising:
generating a stream length histogram (SLH) based on a stream of Read and Write requests accessing a system memory;
determining whether or not to issue a prefetch command after a Read request based on information within said generated SLH; and
in a determination that a prefetch command should be issued, issuing a prefetch command to said system memory along with other commands, wherein a prefetch command prefetching k consecutive lines after a Read request is issued when the following equality is met:
lht(i)<2\xd7lht(i+k)\u2212lht(fs+1)
where lht(i) is the number of Read requests that are part of said stream of length i or longer, where 1\u2266i\u2266fs, and fs is the longest stream to be tracked.
2. The method of claim 1, wherein method further includes constructing said SLH using length Fs likelihood tables LHTcurr and LHTnext that correspond to said lht( ) function.
3. A computer non-transitional storage medium having a computer program product for performing memory prefetching, said computer storage medium comprising:
computer program code for generating a stream length histogram (SLH) based on a stream of Read and Write requests accessing a system memory;
computer program code for determining whether or not to issue a prefetch command after a Read request based on information within said generated SLH; and
computer program code for, in a determination that a prefetch command should be issued, issuing a prefetch command to said system memory along with other commands, wherein a prefetch command prefetching k consecutive lines after a Read request is issued when the following equality is met:
lht(i)<2\xd7lht(i+k)\u2212lht(fs+1)
where lht(i) is the number of Read requests that are part of said stream of length i or longer, where 1\u2266i\u2266fs, and fs is the longest stream to be tracked.
4. The computer storage medium of claim 3, wherein computer storage medium further includes computer program code for constructing said SLH using length Fs likelihood tables LHTcurr and LHTnext that correspond to said lht( ) function.
5. A memory controller comprising:
a stream filter for generating a stream length histogram (SLH) based on a stream of Read and Write requests accessing a system memory; and
a prefetch generator for determining whether or not to issue a prefetch command after a Read request based on information within said generated SLH, and for issuing a prefetch command to be sent to said system memory along with other commands in a determination that a prefetch command should be issued, wherein a prefetch command prefetching k consecutive lines after a Read request is issued when the following equality is met:
lht(i)<2\xd7lht(i+k)\u2212lht(fs+1)
where lht(i) is the number of Read requests that are part of said stream of length i or longer, where 1\u2266i\u2266fs, and fs is the longest stream to be tracked.
6. The memory controller of claim 5, wherein memory controller further includes two length Fs likelihood tables LHTcurr and LHTnext that correspond to said lht( ) function for representing said SLH.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

Having thus described the invention, what we claim is:

1. A process for removing lower temperature binders from a monolith structure while activating the adsorbent in said monolith structure comprising heating said monolith structure to a temperature sufficient to remove substantially all of said lower temperature binder.
2. The process as claimed in claim 1 wherein said temperature is less than about 450 C.
3. The process according to claim 2 wherein the said temperature is less than 325 C.
4. The process as claimed in claim 1 wherein said lower temperature binder is selected from the group consisting of polyurethanes, polyethylene glycols, polyvinyl alcohols, and copolymers such as butadiene-acrylonitrile copolymers.
5. The process as claimed in claim 1 wherein said monolith adsorbent contains lower temperature and higher temperature binders.
6. The process as claimed in claim 5 wherein said lower temperature and said higher temperature binders are in a mixture.
7. The process as claimed in claim 6 wherein said mixture comprises from about 50 to about 95 weight % lower temperature binder.
8. The process as claimed in claim 5 wherein said higher temperature binder is selected from the group consisting of silica, clays, amorphous aluminosilicates, and copolymers of butadiene-acrylonitrile.
9. The process as claimed in claim 1 wherein said adsorbent materials are selected from the group consisting of zeolite type X, zeolite type A, zeolite type Y, ZSM-3, EMT, EMC-2, ZSM-18, ZK-5, ZSM-5, ZSM-11, , L, chabazite, offretite, erionite, mordenite, gmelinite, mazzite, and mixtures thereof, alumina, CMS, silica, silica gel, amorphous aluminosilicate and clays.
10. The process as claimed in claim 9 wherein said adsorbent material is selected from the group consisting of type X zeolite, type A zeolite and mordenite.
11. The process as claimed in claim 10 wherein said type X zeolite has a SiAl molar ratio of about 0.9 to about 1.25.
12. The process as claimed in claim 11 wherein said type X zeolite has a SiAl molar ratio of about 1.0 to 1.1.
13. The process as claimed in claim 12 wherein said type X zeolite has a SiAl ratio less than 1.08.
14. The process as claimed in claim 9 wherein substantially all of the charge-compensating cations in said zeolites are in sodium.
15. The process as claimed in claim 10 wherein substantially all of the charge-compensating cations in said X and type A zeolites with SiAl ratio of 1.0 are in sodium form.
16. The process as claimed in claim 9 wherein said adsorbent material is selected from the group consisting of activated alumina, silica gel and CMS.
17. The process as claimed in claim 10 wherein said adsorbent material is selected from the group consisting of type X zeolite; type A zeolite; and mordenite containing lithium, lithium and bivalent cations, lithium and trivalent cations, and lithium and bivalent cations and trivalent cations; and mixtures thereof.
18. The process as claimed in claim 17 wherein said type X zeolite has a SiAl molar ratio of about 0.9 to about 1.25.
19. The process as claimed in claim 18 wherein said type X zeolite has a SiAl molar ratio of about 1.0 to 1.1.
20. The process as claimed in claim 19 wherein said type X zeolite has a SiAl ratio of about 1.0.
21. The process as claimed in claim 17 where the lithium content of X zeolite is greater than 50% of the total charge-compensating cations.
22. The process as claimed in claim 21 wherein said lithium content of X zeolite is greater than 75% of the total charge-compensating cations.
23. A process for fabricating a monolith adsorbent structure comprising the steps of: forming a slurry comprising water, fiber, adsorbent, retention aid and lower and higher temperature binders; forming paper from said slurry; forming a monolith adsorbent structure from said paper; and heating said monolith adsorbent structure in the flow of a gas to a temperature sufficient to remove substantially all of said lower temperature binder.
24. The process as claimed in claim 23 wherein said temperature is less than about 450 C.
25. The process as claimed in claim 24 wherein said temperature is less than about 325 C.
26. The process as claimed in claim 23 wherein said lower temperature binder is selected from the group consisting of polyurethanes, polyethylene glycols, polyvinyl alcohols, and copolymers such as butadiene-acrylonitrile copolymers.
27. The process as claimed in claim 23 wherein said lower temperature and said higher temperature binders are in a mixture.
28. The process as claimed in claim 27 wherein said mixture comprises from about 50 to about 95 weight % lower temperature binder.
29. The process as claimed in claim 23 wherein said higher temperature binder is selected from the group consisting of silica, clays, amorphous aluminosilicates, and copolymers of butadiene-acrylonitrile.
30. The process as claimed in claim 23 wherein said adsorbent materials are selected from the group consisting of zeolite type X, zeolite type A, zeolite type Y, ZSM-3, EMT, EMC-2, ZSM-18, ZK-5, ZSM-5, ZSM-11, , L, chabazite, offretite, erionite, mordenite, gmelinite, mazzite, and mixtures thereof, alumina, CMS, silica, silica gel, amorphous aluminosilicate and clays.
31. The process as claimed in claim 30 wherein said adsorbent material is selected from the group consisting of type X zeolite, type A zeolite and mordenite.
32. The process as claimed in claim 31 wherein said type X zeolite has a SiAl molar ratio of about 0.9 to about 1.25.
33. The process as claimed in claim 32 wherein said type X zeolite has a SiAl molar ratio of about 1.0 to 1.1.
34. The process as claimed in claim 33 wherein said type X zeolite has a SiAl ratio less than 1.08.
35. The process as claimed in claim 30 wherein said zeolites are sodium containing zeolites.
36. The process as claimed in claim 30 wherein said adsorbent material is selected from the group consisting of activated alumina, silica gel and CMS.
37. The process as claimed in claim 31 wherein said adsorbent material is selected from the group consisting of type X zeolite; type A zeolite; and mordenite containing lithium, lithium and bivalent cations, lithium and trivalent cations, and lithium and bivalent cations and trivalent cations; and mixtures thereof.
38. The process as claimed in claim 37 wherein said type X zeolite has a SiAl molar ratio of about 0.9 to about 1.25.
39. The process as claimed in claim 38 wherein said type X zeolite has a SiAl molar ratio of about 1.0 to 1.1.
40. The process as claimed in claim 39 wherein said type X zeolite has a SiAl ratio of about 1.0.
41. The process as claimed in claim 37 where the lithium content of X zeolite is greater than 50% of the total charge-compensating cations.
42. The process as claimed in claim 41 wherein said lithium content of X zeolite is greater than 75% of the total charge-compensating cations.
43. A method of separating a first gaseous component from a gas mixture comprising a first gaseous component and a second gaseous component comprising:
(a) passing the gaseous mixture into an adsorption zone containing a monolith adsorbent, wherein said monolith adsorbent has been heated to a temperature sufficient to remove substantially all of the lower temperature binder contained therein, and wherein said monolith adsorbent is capable of separating said first gaseous component from said second gaseous component; and
(b) recovering the non-preferentially adsorbed gaseous component from said adsorption zone.
44. The method as claimed in claim 43 wherein said gaseous mixture is air and said first and said second gaseous components are oxygen and nitrogen.
45. The method as claimed in claim 43 wherein said temperature is less than about 450 C.
46. The method as claimed in claim 45 wherein said temperature is less than about 325 C.
47. The method as claimed in claim 43 wherein said lower temperature binder is selected from the group consisting of polyurethanes, polyethylene glycols, polyvinyl alcohols, and copolymers such as butadiene-acrylonitrile copolymers.
48. The method as claimed in claim 43 wherein said monolith adsorbent contains higher temperature binders.
49. The method as claimed in claim 48 wherein said lower temperature and said higher temperature binders are in a mixture.
50. The method as claimed in claim 49 wherein said mixture comprises from about 50 to about 95 weight % lower temperature binder.
51. The method as claimed in claim 48 wherein said higher temperature binder is selected from the group consisting of silica, clays, amorphous aluminosilicates, and copolymers of butadiene-acrylonitrile.
52. The method as claimed in claim 43 wherein said adsorbent materials are selected from the group consisting of zeolite type X, zeolite type A, zeolite type Y, ZSM-3, EMT, EMC-2, ZSM-18, ZK-5, ZSM-5, ZSM-11, , L, chabazite, offretite, erionite, mordenite, gmelinite, mazzite, and mixtures thereof, alumina, CMS, silica, silica gel, amorphous aluminosilicate and clays.
53. The method as claimed in claim 52 wherein said adsorbent material is selected from the group consisting of type X zeolite, type A zeolite and mordenite.
54. The method as claimed in claim 53 wherein said type X zeolite has a SiAl molar ratio of about 0.9 to about 1.25.
55. The method as claimed in claim 54 wherein said type X zeolite has a SiAl molar ratio of about 1.0 to 1.1.
56. The method as claimed in claim 55 wherein said type X zeolite has a SiAl ratio less than 1.08.
57. The method as claimed in claim 52 wherein said zeolites are sodium containing zeolites.
58. The method as claimed in claim 52 wherein said adsorbent material is selected from the group consisting of activated alumina, silica gel and CMS.
59. The method as claimed in claim 53 wherein said adsorbent material is selected from the group consisting of type X zeolite; type A zeolite; and mordenite containing lithium, lithium and bivalent cations, lithium and trivalent cations, and lithium and bivalent cations and trivalent cations; and mixtures thereof.
60. The method as claimed in claim 59 wherein said type X zeolite has a SiAl molar ratio of about 0.9 to about 1.25.
61. The method as claimed in claim 60 wherein said type X zeolite has a SiAl molar ratio of about 1.0 to 1.1.
62. The method as claimed in claim 61 wherein said type X zeolite has a SiAl ratio of about 1.0.
63. The method as claimed in claim 59 where the lithium content of X zeolite is greater than 50% of the total charge-compensating cations.
64. The method as claimed in claim 63 wherein said lithium content of X zeolite is greater than 75% of total charge-compensating cations.

1. An acoustic actuator comprising:
an actuator element configured to generate a corresponding sound in response to an applied electrical signal;
a supporting member supporting the actuator element so as to form a movement axis of the actuator element; and
an edge member connected with the actuator element,
wherein the actuator element comprises:
a piezoelectric unit having at least one piezoelectric member of which a length is larger than a width by at least \u221a{square root over (2)} times; and
a membrane unit including at least one membrane member configured to generate the corresponding sound in response to the applied electrical signal, by being fixedly surface-adhered to the piezoelectric unit so as to extend in a length direction of the at least one piezoelectric member and by forming wave movement in the adhered surface in the length direction in response to a current applied to the piezoelectric unit.
2. The acoustic actuator of claim 1, wherein the piezoelectric unit comprises a plurality of piezoelectric members disposed in parallel in their width direction on a same plane.
3. The acoustic actuator of claim 1, wherein the membrane unit further comprises a driven member configured to amplify the wave movement of the membrane member by being adhered to the membrane member such that the membrane unit extends in a length direction of the membrane member.
4. The acoustic actuator of claim 2, wherein the membrane unit further comprises a driven member configured to amplify the wave movement of the membrane member by being adhered to the membrane member such that the membrane unit extends in a length direction of the membrane member.
5. The acoustic actuator of claim 1, wherein the supporting member is formed at a location that asymmetrically divides the actuator element.
6. The acoustic actuator of claim 1, wherein:
the supporting member is coupled with the membrane unit; and
the piezoelectric unit is spaced apart from the supporting member along the length direction of the at least one piezoelectric member.
7. The acoustic actuator of claim 5, wherein:
the supporting member is coupled with the membrane unit; and
the piezoelectric unit is formed distal to the supporting member along a length direction of the piezoelectric unit.
8. The acoustic actuator of claim 2, wherein:
the membrane unit comprises a same number of membrane members as the plurality of piezoelectric members; and
the piezoelectric members are respectively adhered to the membrane members.
9. The acoustic actuator of claim 8, wherein the membrane unit further comprises a driven member configured to amplify the wave movement of the plurality of membrane members by interconnecting ends of the plurality of membrane members such that the membrane unit extends in a length direction of the plurality of membrane members.
10. The acoustic actuator of claim 1, wherein the piezoelectric unit is adhered to upper and lower sides of the membrane unit.
11. The acoustic actuator of claim 1, further comprising an elastic member interposed between the actuator element and the supporting member so as to allow surface vibration of the actuator element.
12. An acoustic actuator system comprising:
a first acoustic actuator according to claim 1;
a second acoustic actuator according to claim 1; and
a piezoelectric unit driver that drives the first and second acoustic actuators at the same time.
13. The acoustic actuator system of claim 12, wherein each of the first and second acoustic actuators is asymmetrical with respect to the respective supporting members.
14. The acoustic actuator system of claim 12, wherein:
the first acoustic actuator and the second acoustic actuator have different dimensions; and
each of the first and second acoustic actuators is symmetrical with respect to the respective supporting members.
15. The acoustic actuator system of claim 12, wherein:
the first acoustic actuator and the second acoustic actuator have different dimensions;
the first acoustic actuator is symmetrical with respect to its supporting member; and
the second acoustic actuator is asymmetrical with respect to its supporting member.
16. The acoustic actuator system of claim 12, wherein:
the first acoustic actuator is a single cantilever type; and
the second acoustic actuator is a double cantilever type.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor memory comprising:
a plurality of word lines;
a plurality of memory cells provided on a semiconductor substrate, each of the memory cells including a MISFET including a first doped layer, a second doped layer and a gate electrode;
wherein for first and second memory cells of the plurality of memory cells that are adjacent to each other:
a first dummy gate electrode connected to a first power supply is provided between a first doped layer of a first MISFET included in the first memory cell and a first doped layer of a second MISFET included in the second memory cell, and
the first doped layer of the first MISFET, the first doped layer of the second MISFET and the first dummy gate electrode together constitute a first dummy MISFET which is held OFF during operation.
2. The semiconductor memory of claim 1, wherein each of the plurality of memory cells is constituted by a MISFET, and
data is recorded in accordance with whether or not the first doped layer of the MISFET constituting the respective memory cell connected to the bit line.
3. The semiconductor memory of claim 1, wherein the MISFETs included in the plurality of memory cells and the first dummy MISFET are of an n-channel type, and
the first power supply is a ground line.
4. The semiconductor memory of claim 1, wherein the MISFETs included in the plurality of memory cells and the first dummy MISFET are of an n-channel type, and
the first power supply is a power supply for supplying a negative voltage.
5. The semiconductor memory of claim 1, wherein a threshold value of the first dummy MISFET has an absolute value larger than that of a threshold value of each of the MISFETs included in the plurality of memory cells.
6. The semiconductor memory of claim 1, wherein the first dummy gate electrode has a gate length larger than that of a gate electrode of each of the MISFETs included in the plurality of memory cells.
7. The semiconductor memory of claim 1, wherein first and second gate insulating films are provided between the gate electrodes of the MISFETs included in the plurality of memory cells and the semiconductor substrate and between the first dummy gate electrode and the semiconductor substrate, respectively, and
the second gate insulating film has a thickness larger than that of the first gate insulating film.
8. The semiconductor memory of claim 1, wherein among the MISFETs included in the plurality of memory cells, gate electrodes of those MISFETs arranged in one row in the direction in which the word lines extend are also part of a common gate line, and
the gate line has a branch extending toward a region interposed between first doped layers of those MISFETs adjacent to each other and arranged in the direction in which the word lines extend, among the MISFETs included in the plurality of memory cells.
9. The semiconductor memory of claim 1, wherein the semiconductor substrate is a partially depleted SOI substrate including: a buried insulating film; and a semiconductor layer provided on the buried insulating film and including first and second doped layers, and
a negative voltage is applied to the semiconductor layer.
10. The semiconductor memory of claim 1, further comprising a word line driver including first driver MISFETs of an n-channel type and second driver MISFETs of a p-channel type and used for setting potentials on the plurality of word lines, the first and second driver MISFETs being connected to the plurality of word lines,
wherein a second dummy MISFET including a second dummy gate electrode and held OFF during operation is further provided between two of the first driver MISFETs connected to those word lines adjacent to each other among the plurality of word lines.
11. The semiconductor memory of claim 10, wherein each of the first and second dummy MISFETs is plural in number, and those first and second dummy MISFETs arranged in one row in the direction in which the word lines extend respectively have first and second dummy gate electrodes which are also part of a common dummy gate line.
12. The semiconductor memory of claim 10, wherein the MISFETs included in the plurality of memory cells and the first dummy MISFET are of an n-channel type,
second doped layers of the MISFETs included in the plurality of memory cells and second doped layers of the first driver MISFETs are connected to the first power supply, and
the first power supply is a power supply for supplying a negative voltage.
13. A semiconductor integrated circuit comprising:
a semiconductor memory comprising a plurality of word lines, a plurality of bit lines crossing the plurality of word lines and a plurality of first memory cells, the first memory cells being provided on a first semiconductor substrate and each including a MISFET including a first doped layer, a second doped layer and a gate electrode;
a circuit block including a MISFET provided on a semiconductor substrate and a logic circuit; and
a power supply circuit for supplying a fixed potential to at least part of the first semiconductor substrate,
wherein for third and fourth memory cells of the plurality of first memory cells that are adjacent to each other and arranged in the direction in which the bit lines extend,
a dummy MISFET which includes a dummy gate electrode connected to a first power supply, a third doped layer and a fourth doped layer and is held OFF during operation is provided between a first doped layer of a first MISFET included in the third memory cell and a first doped layer of a second MISFET included in the fourth memory cell.
14. The semiconductor integrated circuit of claim 13, wherein the circuit block further includes at least one circuit selected from the group consisting of a DRAM, an SRAM and a nonvolatile memory.
15. The semiconductor integrated circuit of claim 13, wherein the MISFETs included in the plurality of memory cells and the dummy MISFET are of an n-channel type, and
the first power supply is a power supply for supplying a negative voltage.
16. The semiconductor integrated circuit of claim 15, wherein the power supply circuit supplies a negative voltage to part of the first semiconductor substrate and part of the semiconductor substrate in the circuit block.
17. The semiconductor integrated circuit of claim 16, wherein a switch for selecting either one of an output voltage from the power supply circuit or a ground voltage to be supplied to the logic circuit is further provided between the power supply circuit and the logic circuit.