What is claimed is:
1. A delay locked loop (DLL) in a semiconductor device, comprising:
an clock buffer receiving an external clock signal and an inverted clock signal and outputting first and second internal clock signals to be used in the DLL circuit; and
a variable clock divider receiving the second internal signal from the clock buffer and variably dividing the second internal clock signal to have a predetermined pulse width according to a control signal based on a column address strobe (CAS) latency, which is set according to a frequency of the external clock signal, wherein the control signal is initially set to have a first logic level and is enabled to a second logic level when the CAS latency corresponds to a predetermined frequency.
2. The DLL as recited in claim 1, further comprising:
a plurality of delay lines, each delay line having a plurality of unit delay;
a phase comparator comparing a phase between a reference clock signal generated from the variable clock divider and a feedback signal;
a shift controller for generating a shift right signal or a shift left signal according to a comparison signal outputted from the phase comparator;
a shift register for adjusting amount of delay of the delay lines in response to the shift right signal or the shift left signal; and
a delay model generating a feedback signal by compensating a time difference between the external clock signal and the internal clock difference.
3. The DLL as recited in claim 1, wherein the variable clock divider includes:
a first divider for generating a first divided signal having a first pulse width and a first period by receiving the second internal clock signal;
a second divider for generating a second divided signal having the first pulse width and a second period and a third divided signal having a second pulse width and the second period by receiving the first divided signal;
a selector for selectively outputting the second divided signal and the third divided signal in response to the control signal;
a third clock divider for generating a fourth divided clock signal having the first pulse width and a third period or a fifth divided clock signal having the second pulse width and the third period as a reference clock signal by receiving the second divided signal and the third divided signal; and
an output driver outputting an inverted reference clock signal into the delay lines.
4. The DLL as recited in claim 3, wherein the first divider includes:
a 1st NAND gate performing a NAND operation by receiving the second internal clock signal;
a 2nd NAND gate performing a NAND operation by receiving the second internal clock signal;
a 1st inverter inverting the second internal clock signal;
a 3rd NAND gate performing a NAND operation by receiving an output signal of the 2nd NAND gate;
a 4th NAND gate, which is cross-coupled with the 3rd NAND gate, outputting the first divided signal by performing a NAND operation for an output signal of the 1st NAND gate;
a 5th NAND gate performing a NAND operation by receiving output signals of the 3rd NAND gate and the 1st inverter;
a 6th NAND gate performing a NAND operation by receiving output signals of the 4th NAND gate and the 1st inverter;
a 7th NAND gate performing an NAND operation by receiving an output signal of the 6th NAND gate and outputting an output signal to the 2nd NAND gate; and
a 8th NAND gate, which is cross-coupled with the 7th NAND gate, performing a NAND operation by receiving an output signal of the 5th NAND gate and outputting an output signal to the 1st NAND gate.
5. The DLL as recited in claim 3, wherein the second divider includes:
a 9th NAND gate for performing a NAND operation by receiving the first divided signal;
a 10th NAND gate for performing a NAND operation by receiving the first divided signal;
a 2nd inverter inverting the first divided signal;
a 11th NAND gate performing a NAND operation by receiving an output signal of the 10th NAND gate;
a 12th NAND gate, which is cross-coupled with the 11th NAND gate, outputting the second divided signal by performing a NAND operation for an output signal of the 9th NAND gate;
a 13th NAND gate performing a NAND operation by receiving output signals of the 11th NAND gate and the 2nd inverter;
a 14th NAND gate performing a NAND operation by receiving output signals of the 12th NAND gate and the 2nd inverter;
a 15th NAND gate performing an NAND operation by receiving an output signal of the 14th NAND gate and outputting an output signal to the 10th NAND gate; and
a 16th NAND gate, which is cross-coupled with the 15th NAND gate, performing a NAND operation by receiving an output signal of the 13th NAND gate and outputting an output signal to the 9th NAND gate.
6. The DLL circuit as recited in claim 3, wherein the selector includes:
a first pass gate for passing the second divided signal to the second clock divider when the control signal is the first logic level, and for breaking the second divided signal when the control signal is the second logic level; and
a second pass gate for passing the third divided signal to the second clock divider when the control signal is the second logic level, and for breaking the second divided signal when the control signal is the first logic level.
7. The DLL circuit as recited in claim 3, wherein the third divider includes:
a 17th NAND gate for performing a NAND operation by receiving an output signal of the selector;
a 18th NAND gate for performing a NAND operation by receiving the output signal of the selector;
a 3rd inverter inverting the output signal of the selector;
a 19th NAND gate performing a NAND operation by receiving an output signal of the 18th NAND gate;
a 20th NAND gate, which is cross-coupled with the 19th NAND gate, performing a NAND operation for an output signal of the 17th NAND gate;
a 21st NAND gate performing a NAND operation by receiving output signals of the 19th NAND gate and the 3rd inverter;
a 22nd NAND gate performing a NAND operation by receiving output signals of the 20th NAND gate and the 3rd inverter and outputting a reference signal;
a 23rd NAND gate performing an NAND operation by receiving an output signal of the 22nd NAND gate and outputting an output signal to the 18th NAND gate; and
a 24th NAND gate, which is cross-coupled with the 23rd NAND gate, performing a NAND operation by receiving an output signal of the 21st NAND gate and outputting an output signal to the 17th NAND gate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A data structure for representing an image including depth information, the data structure comprising two or more layers, each layer comprising:
an object representing a reference camera;
a collection of color channel values; and
a collection of depth channel values, each depth channel value in the collection of depth channel values corresponding to a color channel value in the collection of color channel values.
2. The data structure of claim 1, wherein each layer further comprises a collection of alpha-channel values, each alpha channel value in the collection of alpha channel values corresponding to a color channel value in the collection of color channel values.
3. The data structure of claim 1, wherein each layer further comprises a collection of texture channel values, each texture channel value in the collection of texture channel values corresponding to a color channel value in the collection of color channel values.
4. The data structure of claim 1, wherein each layer further comprises a collection of illuminance channel values, each illuminance channel value in the collection of illuminance channel values corresponding to a color channel value in the collection of color channel values.
5. The data structure of claim 1, wherein each layer further comprises a collection of normal channel values, each normal channel value in the collection of normal channel values corresponding to a color channel value in the collection of color channel values.
6. The data structure of claim 1, wherein the collection of color channel values comprises a two-dimensional array of color channel values, each entry in the two dimensional array representing the color channel value of a pixel in an image.
7. The data structure of claim 1, wherein the object representing the reference camera comprises a world-to-image projection matrix that specifies a field of view of the reference camera.
8. A method of interactively editing an image containing depth information and reference camera information, the method comprising:
a) displaying the image from a viewpoint defined by an interactive camera;
b) receiving an edit to the image;
c) transforming the edit to a viewpoint defined by the reference camera; and
d) applying the transformed edit to the image.
9. The method of claim 8, wherein receiving an edit comprises receiving an edit to color information associated with the image.
10. The method of claim 8, wherein receiving an edit comprises receiving an edit to alpha information associated with the image.
11. The method of claim 8, wherein receiving the edit comprises receiving an edit to depth information associated with the image.
12. The method of claim 11, wherein receiving an edit to depth information comprises:
providing a user with an interactive drawing tool that specifies edits to depth information; and
receiving edits to depth information made by the user using the interactive drawing tool.
13. The method of claim 12, wherein the interactive drawing tool specifies a selected value for depth for a selected portion of the image.
14. The method of claim 12, wherein the interactive drawing tool incrementally adds to the depth for a selected portion of the image.
15. The method of claim 12, wherein the interactive drawing tool incrementally subtracts from the depth for a selected portion of the image.
16. A method of assigning depth to an object in an image, the method comprising:
a) interactively determining a ground reference for the image; and
b) assigning depth information to the object based on the ground reference.
17. The method of claim 16, wherein interactively determining a ground reference comprises specifying a horizon line in the image.
18. The method of claim 16, wherein interactively determining a ground reference comprises specifying a scale factor on depth.
19. The method of claim 16, wherein assigning depth information comprises using an interactive depth painting tool to specify the depth information.
20. The method of claim 16, wherein assigning depth information comprises using geometric primitives to specify the depth information.
21. The method of claim 16, wherein assigning depth information comprises using a three-dimensional model of an object to specify the depth information.
22. The method of claim 16, wherein the ground reference comprises a planar surface.
23. The method of claim 16, wherein the ground reference comprises a non-planar surface.
24. A method of painting in an image that includes depth information, the method comprising:
a) providing a source position and a destination position in the image;
b) identifying a destination region in the image relative to the destination position;
c) determining a source region in the image relative to the source position and corresponding to the destination region;
d) transforming the image information of the source region relative to the depth information of the source region to image information relative to the depth information of the destination region; and
e) copying the transformed image information to the destination region.
25. The method of claim 24, wherein the image comprises two or more layers.
26. The method of claim 25, wherein the source position is in a first layer, and destination position is in a second layer.
27. The method of claim 24, wherein transforming the image further comprises transforming the image relative to lighting information of the source and destination regions.
28. The method of claim 24, wherein transforming the image further comprises transforming the image relative to texture information of the source and destination regions.
29. The method of claim 24, wherein:
the destination region is defined relative to a destination reference camera;
the source region is defined relative to a source reference camera; and
transforming the image information further comprises transforming the image information from a viewpoint defined by the source reference camera to a viewpoint defined by the destination reference camera.
30. The method of claim 24, further comprises temporarily displaying the area locally around the destination region initialized with image information that approximates the area locally around the source region.
31. The method of claim 30, wherein the approximation comprises a geometric mapping.
32. The method of claim 31, wherein the geometric mapping comprises a planar mapping.
33. The method of claim 24, wherein transforming the image occurs substantially concurrently with a user identifying the destination region.
34. The method of claim 33, wherein transforming the image comprises computing a parameterization only for selected active pixels concurrently with the user identifying the destination region.
35. The method of claim 24, further comprising factoring the image information into a texture component and an illumination component, and wherein copying the transformed image comprises copying the texture component of the transformed image and applying the illumination component of the destination region.
36. A method for determining a texture component and an illumination component of an image, the method comprising:
determining sizes of a small-scale feature in the image and a large-scale feature in the image; and
using an edge-preserving filter to place small-scale features into the texture component and large-scale features into the illumination component.
37. The method of claim 36, wherein determining sizes comprises interactively selecting a feature size of a texture.
38. The method of claim 36, wherein determining sizes further comprises determining a size and shape of a filter kernel, and wherein the edge-preserving filter evaluates image information over an area defined by the filter kernel.
39. The method of claim 38, wherein the image comprises depth information, and wherein determining a size and shape of the filter kernel comprises using the depth information to determine the size and shape of the filter kernel.
40. The method 38 wherein the image comprises normal information, and wherein determining a size and shape of the filter kernel comprises using the normal information to determine the size and shape of the filter kernel.
41. A system for interactively editing a three-dimensional image, the system comprising:
a computer comprising a processor, memory, and a display, the memory containing instructions that, when executed by the processor, cause the computer to:
receive an input image;
interact with a user to segment the input image into a plurality of layers; and
interact with a user to apply depth information to the plurality of layers.
42. The system of claim 41, wherein the input image comprises a two-dimensional image.
43. The system of claim 41, wherein the input image comprises a three-dimensional image including depth information.
44. The system of claim 41, wherein the instructions, when executed by the processor, further cause the computer to interact with the user to edit the plurality of layers.
45. The system of claim 41, wherein the instructions, when executed by the processor, further cause the computer to interact with the user to relight the plurality of layers.
46. The system of claim 41, wherein the instructions, when executed by the processor, further cause the computer to interact with the user to copy a source portion of one of the plurality of layers to a destination portion of one of the plurality of layers, transforming the source portion in response to differences in the depth information of the source portion and the destination portion.