All The Claims

1. A filtering apparatus having a main filter, the filtering apparatus comprising:
a variation detection circuit including a reference filter having at least one first resistor and at least one first capacitor, the variation detection circuit detecting a variation of a CR-product, which is a product of a resistance value of the at least one first resistor times a capacitance value of the at least one first capacitor, in response to each of a plurality of reference signals having different frequencies from each other, and outputting a variation detection signal indicating a detected result; and
a variation correction circuit for receiving the variation detection signal from said variation detection circuit and for correcting frequency characteristics of the main filter based on the variation detection signal;
wherein the variation detection circuit includes:
a frequency divider for frequency-dividing the reference signal by a predetermined frequency division ratio, and outputting a frequency-divided signal to the reference filter;
a reference signal frequency selection controller for generating a frequency selection signal for switching over group delay characteristics of the reference filter based on the frequency of the reference signal, and outputting the frequency selection signal to the reference filter, wherein the group delay characteristic is based on the at least one first resistor and the at least one first capacitor of the reference filter;
a delay time detector for detecting and outputting a delay time of an output signal of the reference filter for the frequency-divided signal; and
a counter for counting a multiple of a signal time cycle of the reference signal for the delay time detected by the delay time detector, and outputting the variation detection signal including a counted result to the variation correction circuit.
2. The filtering apparatus as claimed in claim 1,
wherein the reference filter has one of a plurality of first resistors and a plurality of first capacitors, and
wherein the reference signal frequency selection controller switches over the group delay characteristics of the reference filter by generating the frequency selection signal for selecting one of at least one resistor, at least one capacitor of the plurality of first resistors and the plurality of first capacitors based on the frequency of the reference signal, and outputting the frequency signal to the reference filter.
3. The filtering apparatus as claimed in claim 1, further comprising a switch for connecting the reference filter to the frequency-divider and the delay time detector during a variation correction time interval, and for disconnecting the reference filter from the frequency-divider and the delay time detector so that the reference filter operates as the main filter during an operation time interval of the main filter.
4. The filtering apparatus as claimed in claim 1,
wherein the main filter includes a plurality of second resistors and a plurality of second capacitors, and
wherein the variation correction circuit includes a switch selection controller for switching over the frequency characteristics of the main filter by selecting one of at least one resistor, at least one capacitor of the plurality of second resistors and the plurality of second capacitors based on the variation detection signal inputted from the counter.
5. The filtering apparatus as claimed in claim 1, further comprising an oscillator for generating and outputting the reference signal.
6. A filtering apparatus having a main filter, the filtering apparatus comprising:
a variation detection circuit including a reference filter having at least one first resistor and at least one first capacitor, the variation detection circuit detecting a variation of a CR-product, which is a product of a resistance value of the at least one first resistor times a capacitance value of the at least one first capacitor, in response to each of a plurality of reference signals having different frequencies from each other, and outputting a variation detection signal indicating a detected result; and
a variation correction circuit for receiving the variation detection signal from said variation detection circuit and for correcting frequency characteristics of the main filter based on the variation detection signal;
wherein the variation detection circuit includes:
a frequency division ratio change circuit for frequency-dividing the reference signal by one of a plurality of first frequency division ratios in response to a frequency selection signal, and then outputting a first frequency-divided signal;
a frequency divider for frequency-dividing the first frequency-divided signal by a predetermined second frequency division ratio, and then outputting a second frequency-divided signal to the reference filter;
a reference signal frequency selection controller for generating the frequency selection signal for switching over the first frequency division ratio of the frequency division ratio change circuit among the plurality of first frequency division ratios based on the frequency of the reference signal, and outputting the frequency selection signal to the frequency selection signal to the frequency division ratio change circuit;
a delay time detector for detecting and outputting a delay time of an output signal of the reference filter for the second frequency-divided signal; and
a counter for counting a multiple of a signal time cycle of the first frequency-divided signal for the delay time detected by the delay time detector, and then outputting the variation detection signal including a counted result to the variation correction circuit.
7. The filtering apparatus as claimed in claim 6, further comprising a switch circuit for connecting the reference filter to the frequency-divider and the delay time detector during a variation correction time interval, and for disconnecting the reference filter from the frequency-divider and the delay time detector so that the reference filter operates as the main filter during an operation time interval of the main filter.
8. The filtering apparatus as claimed in claim 6,
wherein the main filter includes a plurality of second resistors and a plurality of second capacitors, and
wherein the variation correction circuit includes a switch selection controller for switching over the frequency characteristics of the main filter by selecting one of at least one resistor, at least one capacitor of the plurality of second resistors and the plurality of second capacitors based on the variation detection signal inputted from the counter.
9. The filtering apparatus as claimed in claim 6, further comprising an oscillator for generating and outputting the reference signal.
10. A filtering apparatus having a main filter, the filtering apparatus comprising:
a variation detection circuit including a reference filter having at least one first resistor and at least one first capacitor, the variation detection circuit detecting a variation of a CR-product, which is a product of a resistance value of the at least one first resistor times a capacitance value of the at least one first capacitor, in response to each of a plurality of reference signals having different frequencies from each other, and outputting a variation detection signal indicating a detected result; and
a variation correction circuit for receiving the variation detection signal from said variation detection circuit and for correcting frequency characteristics of the main filter based on the variation detection signal;
wherein the variation detection circuit includes:
a frequency divider for frequency-dividing the reference signal by a predetermined first frequency division ratio, and then outputting a first frequency-divided signal to the reference filter;
a delay time detector for detecting a delay time of an output signal of the reference filter for the first frequency-divided signal;
a counter for counting a multiple of a signal time cycle of the reference signal for a delay time detected by the delay time detector, multiplying a counted result by a correction coefficient included in a frequency selection signal, and then outputting the variation detection signal including a multiplied result to the variation correction circuit; and
a reference signal frequency selection controller for generating the frequency selection signal including the correction coefficient of the counter based on the frequency of the reference signal, and outputting the frequency selection signal to the counter.
11. The filtering apparatus as claimed in claim 10, further comprising a switch circuit for connecting the reference filter to the frequency-divider and the delay time detector during a variation correction time interval, and for disconnecting the reference filter from the frequency-divider and the delay time detector so that the reference filter operates as the main filter during an operation time interval of the main filter.
12. The filtering apparatus as claimed in claim 10,
wherein the main filter includes a plurality of second resistors and a plurality of second capacitors, and
wherein the variation correction circuit includes a switch selection controller for switching over the frequency characteristics of the main filter by selecting one of at least one resistor, at least one capacitor of the plurality of second resistors and the plurality of second capacitors based on the variation detection signal inputted from the counter.
13. The filtering apparatus as claimed in claim 10, further comprising an oscillator for generating and outputting the reference signal.
14. A semiconductor apparatus having a filtering apparatus having a main filter,
the filtering apparatus comprising:
a variation detection circuit including a reference filter having at least one first resistor and at least one first capacitor, the variation detection circuit detecting a variation of CR-product, which is a product of a resistance value of the at least one first resistor times a capacitance value of the at least one first capacitor, in response to each of a plurality of reference signals having different frequencies from each other, and outputting a variation detection signal indicating a detected result; and
a variation correction circuit for correcting frequency characteristics of the main filter based on the variation detection signal,
wherein the variation detection circuit includes:
a frequency divider for frequency-dividing the reference signal by a predetermined frequency division ratio, and outputting a frequency-divided signal to the reference filter;
a reference signal frequency selection controller for generating a frequency selection signal for switching over group delay characteristics of the reference filter based on the frequency of the reference signal, and outputting the frequency selection signal to the reference filter, wherein the group delay characteristic is based on the at least one first resistor and the at least one first capacitor of the reference filter;
a delay time detector for detecting and outputting a delay time of an output signal of the reference filter for the frequency-divided signal; and
a counter for counting a multiple of a signal time cycle of the reference signal for the delay time detected by the delay time detector, and outputting the variation detection signal including a counted result to the variation correction circuit.
15. A semiconductor apparatus having a filtering apparatus having a main filter,
the filtering apparatus comprising:
a variation detection circuit including a reference filter having at least one first resistor and at least one first capacitor, the variation detection circuit detecting a variation of CR-product, which is a product of a resistance value of the at least one first resistor times a capacitance value of the at least one first capacitor, in response to each of a plurality of reference signals having different frequencies from each other, and outputting a variation detection signal indicating a detected result; and
a variation correction circuit for correcting frequency characteristics of the main filter based on the variation detection signal,
wherein the variation detection circuit includes:
a frequency division ratio change circuit for frequency-dividing the reference signal by one of a plurality of first frequency division ratios in response to a frequency selection signal, and then outputting a first frequency-divided signal;
a frequency divider for frequency-dividing the first frequency-divided signal by a predetermined second frequency division ratio, and then outputting a second frequency-divided signal to the reference filter;
a reference signal frequency selection controller for generating the frequency selection signal for switching over the first frequency division ratio of the frequency division ratio change circuit among the plurality of first frequency division ratios based on the frequency of the reference signal, and outputting the frequency selection signal to the frequency selection signal to the frequency division ratio change circuit;
a delay time detector for detecting and outputting a delay time of an output signal of the reference filter for the second frequency-divided signal; and
a counter for counting a multiple of a signal time cycle of the first frequency-divided signal for the delay time detected by the delay time detector, and then outputting the variation detection signal including a counted result to the variation correction circuit.
16. A semiconductor apparatus having a filtering apparatus having a main filter,
the filtering apparatus comprising:
a variation detection circuit including a reference filter having at least one first resistor and at least one first capacitor, the variation detection circuit detecting a variation of CR-product, which is a product of a resistance value of the at least one first resistor times a capacitance value of the at least one first capacitor, in response to each of a plurality of reference signals having different frequencies from each other, and outputting a variation detection signal indicating a detected result; and
a variation correction circuit for correcting frequency characteristics of the main filter based on the variation detection signal,
wherein the variation detection circuit includes:
a frequency divider for frequency-dividing the reference signal by a predetermined first frequency division ratio, and then outputting a first frequency-divided signal to the reference filter;
a delay time detector for detecting a delay time of an output signal of the reference filter for the first frequency-divided signal;
a counter for counting a multiple of a signal time cycle of the reference signal for a delay time detected by the delay time detector, multiplying a counted result by a correction coefficient included in a frequency selection signal, and then outputting the variation detection signal including a multiplied result to the variation correction circuit; and
a reference signal frequency selection controller for generating the frequency selection signal including the correction coefficient of the counter based on the frequency of the reference signal, and outputting the frequency selection signal to the counter.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for supporting input of one or more execution parameters of predetermined software in an input field, comprising:
receiving input of a text character string including one or more execution parameters in the input field displayed on a display device;
determining a selection type in response to a user selection of a part of the text character string;
displaying on the display device one or more execution options of the execution parameters depending on the determined selection type; and
in response to the user selection of a desired execution option, transforming said text character string to include the desired execution option selected and displaying the transformed text character string on the display device.
2. The method according to claim 1, further comprising:
determining the selection type corresponding to the range of the selected part of said text character string,
wherein said display of said execution options include identifying a set of execution options of said predetermined software corresponding to said selection type.
3. The method according to claim 1, further comprising:
transmitting the one or more parameters and execution options included in said transformed text character string to a server that executes said predetermined software.
4. The method according to claim 1, wherein, in a case where said text character string includes a plurality of input parameters, the input parameters are separated by a delimiter.
5. The method according to claim 4, wherein said delimiter is a space (a blank character).
6. The method according to claim 2, wherein said selection type is determined by considering any delimiter that is included in or adjacent to said selected part of said text character string.
7. The method according to claim 5, further comprising:
calculating the number of parameters associated with said selected part of said text character string based on the delimiter included in said selected part of said text character string.
8. The method according to claim 3, further comprising:
determining said selection type based on whether said selected part of said text character string is adjacent to a delimiter or not.
9. The method according to claim 1, further comprising:
obtaining an item ID corresponding to said selection type from an option item table; and
presenting the execution option corresponding to the obtained item ID on an interface.
10. The method according to claim 1, further comprising:
obtaining an item ID of a sub item from a table in a case where the item selected on said interface includes the sub item; and
presenting an item corresponding to the obtained item ID of said sub item.
11. The method according to claim 1, wherein the execution options that can be selected are displayed on the display device in the form of a menu.
12. The method according to claim 1, wherein labels of said one or more execution options that can be selected are displayed on the display device.
13. The method according to claim 1, wherein said selection type is selected from a group including \u201ca plurality of parameters\u201d, \u201ca single parameter\u201d and \u201ca part of a parameter\u201d.
14. The method according to claim 1, wherein said predetermined software is a search engine, said text character string represents a search condition, and said execution options are search options for said search engine.
15. The method according to claim 14, wherein said search options include search field specification, wild card, fuzzy search, proximity search, range search, search term boosting, Boolean operator, grouping and field grouping.
16. A computer program product for supporting input of one or more execution parameters of predetermined software in an input field, the computer program product comprising a computer readable storage medium having stored thereon computer program code that when executed by at least one processor of a computer makes the computer:
receive input of a text character string including one or more execution parameters in the input field displayed on a display device;
determine a selection type in response to a user selection of a part of the text character string;
display on the display device one or more execution options of the execution parameters depending on the determined selection type; and
in response to the user selection of a desired execution option, transform said text character string to include the desired execution option selected and display the transformed text character string on the display device.
17. A system for supporting input of one or more execution parameters of predetermined software in an input field, comprising:
a computer with a display and a processor configured to perform:
receiving input in the computer of a text character string including one or more execution parameters in the input field;
determining a selection type in response to a user selection of a part of the text character string;
displaying in the display one or more execution options of the execution parameters depending on the determined selection type; and
in response to the user selection of a desired execution option, transforming said text character string to include the desired execution option selected and displaying the transformed text character string.

1. An information processing system that includes a plurality of sets of two or more multiple processors that perform processing in synchronization with each other, comprising:
a non-volatile memory that stores a firmware program activating the multiple processors to a state in which the multiple processors are synchronized with each other;
a volatile memory that is defined by one address map as a whole;
a firmware copying section that copies the firmware program stored in the non-volatile memory to the volatile memory, on system boot;
a volatile memory address register in which an address of the volatile memory and of a copy destination to which the firmware program is copied is stored;
a volatile memory address storing section that stores the address of the volatile memory and of the copy destination to which the firmware program is copied by the firmware copying section, in the volatile memory address register;
a loss-of-synchronism detection section that detects loss of synchronism of the multiple processors; and
an address replacing section that refers to the volatile memory address register in response to the loss of synchronism being detected by the loss-of-synchronism detection section, to replace an address for reading the firmware program stored in the non-volatile memory, with the address of the volatile memory and of the copy destination of the firmware program.
2. The information processing system according to claim 1, further comprising:
a copy flag register in which a copy flag indicating that the firmware program is copied to the volatile memory is stored; and
a copy flag storing section that stores the copy flag in the copy flag register, in response to the firmware program being copied to the volatile memory by the firmware copying section, wherein
the address replacing section refers to the copy flag register in response to the loss of synchronism being detected by the loss-of-synchronism detection section, and when the copy flag is stored in the copy flag register, replaces the address for reading the firmware program stored in the non-volatile memory, with the address of the volatile memory and of the copy destination of the firmware program.
3. The information processing system according to claim 1, further comprising:
a context saving section that saves a context for continuing operation after resynchronization into the volatile memory, prior to reading of the firmware program, in response to the loss of synchronism being detected by the loss-of-synchronism detection section; and
a context reading section that reads the context saved into the volatile memory, after the firmware program is read out.
4. The information processing system according to claim 2, further comprising:
a context saving section that saves a context for continuing operation after resynchronization into the volatile memory, prior to reading of the firmware program, in response to the loss of synchronism being detected by the loss-of-synchronism detection section; and
a context reading section that reads the context saved into the volatile memory, after the firmware program is read out.
5. An information processing system that includes a plurality of sets of two or more multiple processors, and a system management device managing the plurality of sets of multiple processors, comprising:
a non-volatile memory that stores a firmware program activating the multiple processors to a state in which the multiple processors are synchronized with each other;
a volatile memory that is defined by one address map as a whole;
a loss-of-synchronism detection section that detects loss of synchronism of the multiple processors, and reports the loss of synchronism to the system management device; and
a separation processing section that logically separates the multiple processors from the information processing system, upon receipt of a separation instruction from the system management device, wherein
the system management device includes a separation instructing section that instructs, in response to the system management device receiving a report on loss of synchronism in any of the plurality of sets of multiple processors, a processor continuing normal operation of first multiple processors in which the loss of synchronism has occurred, to logically separate the first multiple processors from the information processing system.
6. The information processing system according to claim 5, wherein the system management device includes an addition instructing section that provides an instruction of logically adding the first multiple processors to the information processing system, in response to completion of resynchronization in the first multiple processors after being logically separated.
7. The information processing system according to claim 5, wherein
the plurality of sets of multiple processors include second multiple processors logically separated from the information processing system, and
the system management device includes an entry instructing section that provides an instruction of making a logical entry of the second multiple processors into the information processing system, in response to the system management device receiving a report on loss of synchronism in any of the plurality sets of multiple processors, and
the separation instructing section makes logical separation from the information processing system after transferring processing performed in the first multiple processors to the second multiple processors newly entered the information processing system, in response to a separation instruction from the system management device.
8. The information processing system according to claim 7, wherein the separation processing section separating the first multiple processors informs the second multiple processors of an ID of the first multiple processors as an ID of the second multiple processors newly entered the information processing system, in response to the separation instruction from the system management device.
9. The information processing system according to claim 8, further comprising:
a context saving section that saves a context for continuing processing performed in the first multiple processors with the second multiple processors into the volatile memory, in response to the separation instruction from the system management device, when being in a position of the first multiple processors; and
a context reading section that reads the context from the volatile memory, when being in a position of the second multiple processors and newly entering the information processing system.
10. A resynchronization method in an information processing system including a plurality of sets of two or more multiple processors that perform processing in synchronization with each other, the information processing system including
a non-volatile memory that stores a firmware program activating the multiple processors to a state in which the multiple processors are synchronized with each other,
a volatile memory that is defined by one address map as a whole, and
a volatile memory address register in which an address of the volatile memory and of a copy destination to which a firmware program is copied is stored, and
the resynchronization method comprising:
copying the firmware program stored in the non-volatile memory to the volatile memory, on system boot;
storing the address of the volatile memory and of the copy destination of the firmware program, in the volatile memory address register;
detecting loss of synchronism of the multiple processors; and
replacing an address for reading the firmware program stored in the non-volatile memory, with the address of the volatile memory and of the copy destination of the firmware program, by referring to the volatile memory address register in response to the loss of synchronism being detected.
11. A resynchronization method in an information processing system including a plurality of sets of two or more multiple processors, and a system management device managing the plurality of sets of multiple processors, the information processing system including
a non-volatile memory that stores a firmware program activating the multiple processors to a state in which the multiple processors are synchronized with each other, and
a volatile memory that is defined by one address map as a whole, and
the resynchronization method comprising:
detecting loss of synchronism of the multiple processors, and reporting the loss of synchronism to the system management device; and
instructing, in response to the system management device receiving a report on loss of synchronism in any of the plurality of sets of multiple processors, a processor continuing normal operation of first multiple processors in which the loss of synchronism has occurred, to logically separate the first multiple processors from the information processing system, the separation being performed in the system management device; and
logically separating the first multiple processors from the information processing system, in response to a separation instruction from the system management device, the separation being executed in the processor continuing the normal operation of the first multiple processors.
12. A non-transitory storage medium that stores a firmware program executed in an information processing system including a plurality of sets of two or more multiple processors that perform processing in synchronization with each other,
the information processing system including
a non-volatile memory that stores a firmware program activating the multiple processors to a state in which the multiple processors are synchronized with each other,
a volatile memory that is defined by one address map as a whole, and
a volatile memory address register in which an address of the volatile memory and of a copy destination to which a firmware program is copied is stored, and
the firmware program causing the information processing system to operate as the information processing system comprising:
a firmware copying section that copies the firmware program stored in the non-volatile memory to the volatile memory, on system boot;
a volatile memory address storing section that stores the address of the volatile memory and of the copy destination to which the firmware program is copied by the firmware copying section, in the volatile memory address register;
a loss-of-synchronism detection section that detects loss of synchronism of the multiple processors; and
an address replacing section that refers to the volatile memory address register in response to the loss of synchronism being detected by the loss-of-synchronism detection section, to replace an address for reading the firmware program stored in the non-volatile memory, with the address of the volatile memory and of the copy destination of the firmware program.
13. A non-transitory storage medium that stores a firmware program executed in an information processing system including a plurality of sets of two or more multiple processors, and a system management device managing the plurality of sets of multiple processors, the information processing system including
a non-volatile memory that stores a firmware program activating the multiple processors to a state in which the multiple processors are synchronized with each other, and
a volatile memory that is defined by one address map as a whole, and
the firmware program causing the information processing system to operate as the information processing system comprising:
a loss-of-synchronism detection section that detects loss of synchronism of the multiple processors, and reports the loss of synchronism to the system management device; and
a separation processing section that logically separates the multiple processors from the information processing system, upon receipt of a separation instruction from the system management device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A side pumping type DPSS laser, comprising:
a first laser chip for generating a pumping light;
a second laser chip, although being parallel with the first laser chip, slightly slanted to a predetermined degree so as to avoid a contact with the pumping light;
a first and second focusing lens for focusing the pumping lights; and
a side pumping medium for forming the focused pumping lights in a beam mode so as to output as a lasing light.
2. The side pumping type DPSS laser of claim 1, wherein the side pumping medium comprises:
a laser material manufactured in a plate type;
a sapphire plate formed at both sides of the laser material and having an AR coating and HR coating alternatively provided on each side of the laser material;
a copper block provided at a top of the sapphire plate for fixing the sapphire plate and transmitting heat to outside;
HR coating formed on a rear surface of the side pumping medium for reflecting radiated lasing light; and
PR coating formed on a front surface of the side pumping medium for transmitting a part of the lasing light.
3. The side pumping type DPSS laser of claim 2, further comprises a stop coating formed between the PR coating and the laser material for filtering all the pumping light, and a middle portion thereof is removed for filtering all lights except a light in a pumping light lasing mode.
4. The side pumping type DPSS laser of claim 2, wherein a width of the laser material is in a beam waist size of the lased laser.
5. The side pumping type DPSS laser of claim 2, wherein a doping amount of the laser material is a value of the pumping light radiated to and absorbed by the laser material after being transmitted through the laser material.
6. The side pumping type DPSS laser of claim 1, wherein perpendicular component of the light radiated to the predetermined surface is focused and parallel component thereof is proceeded parallel.
7. The side pumping type DPSS laser, comprising:
a first pumping laser diode (LD) generating a plurality of pumping lights;
a second pumping laser diode (LD) provided to be slightly slanted such that the pumping lights are not in contact with each other although being parallel around the side pumping medium;
a first and second focusing lens array having a plurality of focusing lens for focusing a plurality of the pumping lights; and
a side pumping assembly forming the focused pumping lights in a beam mode so as to output as a lasing light.
8. The side pumping type DPSS laser of claim 8, further comprises a stop coating formed between the PR coating and the laser material for filtering all the pumping light, and a middle portion thereof is removed for filtering all lights except a light in a pumping light lasing mode.
9. The side pumping type DPSS laser of claim 8, wherein a doping amount of the laser material is a value of the pumping light radiated to and absorbed by the laser material after being transmitted through the laser material.
10. The side pumping type DPSS laser of claim 8, wherein a width of the laser material is in a beam waist size of the lased laser
11. The side pumping type DPSS laser of claim 8, wherein a doping amount of the laser material is a value of the pumping light radiated to and absorbed by the laser material after being transmitted through the laser material.
12. The side pumping type DPSS laser of claim 7, wherein the focusing lens array focus perpendicular component light radiated to a predetermined surface and proceeds parallel component light parallel.