All The Claims

1. A system-on-chip control system, comprising:
a processor for generating a root key for protecting data stored in a memory device connected to the control system;
a root key storage unit for storing the root key; and
a debug port configured to enable an external device to access the control system;
wherein the processor keeps the debug port locked to prevent the external device from accessing the control system if a root key is stored in the storage unit, and unlocks the debug port to enable the external device to access the control system after the root key is erased.
2. The control system as defined in claim 1, wherein the debug port is locked by default when the control system is powered on.
3. The control system as defined in claim 1, wherein the processor erases the root key upon receiving a command to erase the root key from a host device connected to the control system.
4. The control system as defined in claim 1, wherein the root key is generated by entropy collected by the processor.
5. The control system as defined in claim 1, wherein said root key storage unit comprises FLASH memory or a one-time-programmable (OTP) memory.
6. The control system as defined in claim 1, further comprising a debug port interface for enabling the external device to access the control system via the debug port.
7. A method for protecting data stored in a memory device connected to an on-chip control system having a debug port configured to enable an external device to access the control system, the method comprising:
generating a root key for accessing data stored in the memory device;
storing the root key in a root key storage unit; and
keeping the debug port locked to prevent the external device from accessing the data in the memory device through the control system if the root key is stored in the storage unit, and unlocking the debug port to enable the external device to access the control system after the root key is erased.
8. The method as defined in claim 7, wherein the debug port is locked by default when the control system is powered on.
9. The method as defined in claim 7, wherein the root key is erased upon receiving a command to erase the root key from a host device connected to the control system.
10. The method as defined in claim 7, wherein the root key is generated by entropy collected by a processor in the control system.
11. The method as defined in claim 1, wherein the root key storage unit comprises FLASH memory or a one-time-programmable (OTP) memory.
12. A system-on-chip control system of a storage device, comprising:
a host interface configured to be in communication with a host device;
a processor for generating a root key for protecting data stored in a memory device connected to the control system;
a root key storage unit for storing the root key;
a debug port configured to enable an external device to access the control system; and
wherein the processor keeps the debug port locked to prevent the external device from accessing the control system if a root key is stored in the storage unit, and unlocks the debug port to enable the external device to access the control system after the root key is erased.
13. The control system as defined in claim 12, wherein said storage device comprises a disk drive.
14. The storage apparatus as defined in claim 12, wherein said storage device comprises a solid state drive.
15. A storage apparatus, comprising:
at least one storage medium;
a system-on-chip controller including:
a host interface configured to be in communication with a host device;
a processor for generating a root key for protecting data stored in a memory device connected to the control system;
a root key storage unit for storing the root key;
a debug port configured to enable an external device to access the control system; and
wherein the processor keeps the debug port locked to prevent the external device from accessing the control system if a root key is stored in the storage unit, and unlocks the debug port to enable the external device to access the control system after the root key is erased;

a buffer for storing data used by the system-on-chip controller; and
a non-volatile memory for storing programs and tables used by the system-on-chip controller.
16. The storage apparatus as defined in claim 15, wherein said storage medium comprises a disk medium.
17. The storage apparatus as defined in claim 15, wherein said storage medium comprises a solid state storage device.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An apparatus, comprising:
a voltage source to provide a substantially temperature stable output voltage;
a first semiconductor device biased by the substantially temperature stable output voltage to provide a first output current; and
a second semiconductor device biased by the substantially temperature stable output voltage to provide a second output current, the second semiconductor device to couple to the first semiconductor device to provide a reference current approximately equal to a difference between the first and the second output currents.
2. The apparatus of claim 1, wherein the first and the second semiconductor devices are biased by the substantially temperature stable output voltage to operate in a saturation mode.
3. The apparatus of claim 1, wherein the first and the second semiconductor devices are fabricated on a single die.
4. The apparatus of claim 1, further including:
a differencing circuit to couple to the first and the second semiconductor devices.
5. The apparatus of claim 1, further including:
a pair of current mirrors to couple to the first and the second semiconductor devices.
6. The apparatus of claim 5, wherein the first and the second semiconductor devices and the pair of current mirrors are fabricated on a single die.
7. The apparatus of claim 1, wherein a reference magnitude of the reference current is approximately equal to a difference between the second output current and a product of the first output current and a scaling constant.
8. The apparatus of claim 7, further comprising:
a differencing circuit including a first current mirror selected to determine the scaling constant.
9. The integrated circuit of claim 1, wherein the voltage source comprises a band-gap voltage source.
10. An integrated circuit, comprising:
a voltage source to provide a substantially temperature stable output voltage;
a first semiconductor device biased by the substantially temperature stable output voltage to provide a first output current; and
a second semiconductor device biased by the substantially temperature stable output voltage to provide a second output current, the second semiconductor device to couple to the first semiconductor device to provide a reference current approximately equal to a difference between the first and the second output currents; and
an output node in electrical communication with the first and second semiconductor devices to carry the reference current.
11. The integrated circuit of claim 10, wherein the first and the second semiconductor devices are biased by the substantially temperature stable output voltage to operate in a saturation mode.
12. The integrated circuit of claim 10, further including:
a differencing circuit to couple to the first and the second semiconductor devices.
13. The integrated circuit of claim 12, wherein the reference current has a reference magnitude approximately equal to the difference between the second output current and a product of the first output current and a scaling constant determined by a current mirror included in the differencing circuit.
14. The integrated circuit of claim 10, wherein each one of the first and the second semiconductor devices comprise a field effect transistor.
15. The integrated circuit of claim 14, further including:
a pair of current mirrors to couple to the first and the second semiconductor devices, wherein each one of the pair of current mirrors includes a pair of field effect transistors, and wherein the first and the second semiconductor devices and the pair of current mirrors are fabricated on a single die.
16. The integrated circuit of claim 10, wherein the voltage source comprises a band-gap voltage source.
17. A system, comprising:
a cellular telephone including a voltage source to provide a substantially temperature stable output voltage, a first semiconductor device biased by the substantially temperature stable output voltage to provide a first output current, and a second semiconductor device biased by the substantially temperature stable output voltage to provide a second output current, the second semiconductor device to couple to the first semiconductor device to provide a reference current approximately equal to a difference between the first and the second output currents.
18. The system of claim 17, further comprising a differencing circuit to couple to the first and the second semiconductor devices.
19. The system of claim 18, wherein the differencing circuit includes a first current mirror selected to determine a scaling constant.
20. The system of claim 19, wherein the reference current has a reference magnitude approximately equal to the difference between the second output current and a product of the first output current and the scaling constant.

1. A process for preparing an acyloxybenzoic acid of the formula (I)
in which
R1 is a linear or branched, saturated alkyl group having 6 to 30 carbon atoms, a linear or branched, singly or multiply unsaturated alkenyl group having 6 to 30 carbon atoms, or an aryl group having 6 to 30 carbon atoms,
comprising the steps of
a) reacting a carboxylic halide of the formula R1COHal, in which R1 is defined above and Hal is a halide, with para-hydroxybenzoic acid in the presence of base, wherein the base is selected from alkali metal hydroxides, in a solvent mixture comprising water and at least one organic solvent, wherein the organic solvent is isopropanol, at a temperature \u226625\xb0 C. and a pH of 9 to 11.5,
b) adjusting the pH of the reaction mixture after step a), at a temperature \u226625\xb0 C., to a pH of 6 to 8 by addition of acid, and
c) subsequently heating the reaction mixture after step b) to a temperature of 35 to 80\xb0 C. and thereafter adjusting the pH of the reaction mixture to a pH of 1 to 4 by addition of acid.
2. The process as claimed in claim 1, wherein after step c) the reaction mixture is cooled to a temperature <35\xb0 C.
3. The process as claimed in claim 1 wherein the acyloxybenzoic acids of the formula (I) are present in the form of particles having d50 values of 10 to 150 \u03bcm.
4. The process as claimed in claim 3, wherein the particles have d10 values of 5 to 30 \u03bcm and d90 values of 30 to 200 \u03bcm.
5. The process as claimed in claim 1, the base in step a) is KOH or NaOH.
6. The process as claimed in claim 1, the acid in steps b) and c) has a pKa value of less than or equal to 4.0.
7. The process as claimed in claim 1, the acid in steps b) and c) is H2SO4 or HCl.
8. The process as claimed in claim 1, wherein the weight ratio of water to the at least one organic solvent in step a) is from 5:1 to 1:5.
9. The process as claimed in claim 1, wherein the weight ratio of water to para-hydroxybenzoic acid in step a) is from 2:1 to 10:1.
10. The process as claimed in claim 1, wherein R1 is a linear or branched, saturated alkyl group having 6 to 30 carbon atoms, or a linear or branched, singly or multiply unsaturated alkenyl group having 6 to 30 carbon atoms.
11. The process as claimed in claim 10, wherein the radical R1 is an alkyl group.
12. The process as claimed in claim 10, wherein a carboxylic acid, R1\u2014COOH from which the carboxylic halide R1\u2014COHal is derived is selected from the group consisting of octanoic acid, nonanoic acid, 3,3,5-isononanoic acid, decanoic acid and dodecanoic acid.
13. The process as claimed in claim 12, wherein the carboxylic acid from which the carboxylic halide R1\u2014COHal is derived is decanoic acid.
14. The process as claimed in claim 1, wherein the amount of dimers and trimers of para-hydroxybenzoic acid present in the acyloxybenzoic acid produced is less than 0.3% by weight.
15. The process as claimed in claim 14, wherein the amount of dimers and trimers of para-hydroxybenzoic acid present in the acyloxybenzoic acid produced is less than 0.1% by weight.
16. The process as claimed in claim 1, wherein the acyloxybenzoic acid produced is free from unreacted para-hydroxybenzoic acid.
17. The process as claimed in claim 1, wherein the acyloxybenzoic acid produced is free from acid of the formula R1COOH.
18. The process as claimed in claim 1, wherein the acyloxybenzoic acids of the formula (I) are present in the form of particles having d50 values of 10 to 150 \u03bcm, obtained directly from the process without subsequent treatment.
19. The process as claimed in claim 18, wherein the particles have d10 values of 5 to 30 \u03bcm and d90 values of 30 to 200 \u03bcm, obtained directly from the process without subsequent treatment.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. Apparatus for verifying a validity of an encrypted token associated to a product, comprising:
a decryptor for decrypting an encrypted token using a decryption key to acquire a decrypted token comprising information bits related to the product and structure bits;
an evaluator for evaluating whether the structure bits fulfill a predetermined condition, wherein the encrypted token is verified to be valid when the predetermined condition is fulfilled or is not verified to be valid when the predetermined condition is not fulfilled;
a product access processor for interpreting the information bits and for determining a level of product access in accordance with the information bits when the encrypted token is verified to be valid;
wherein the product access processor is configured to process a variable number of bits in the decrypted token and to determine a higher level of product access when a number of information bits is lower and to determine a lower level of product access when a number of information bits is higher; and
wherein a higher level of product access allows a user to use more, more expensive or more complicated functions of the product and a lower level of product access allows the user to use less, less expensive or less complicated functions of the product.
2. Apparatus according to claim 1, further comprising:
a data parser for parsing the decrypted token or a clear data portion attached to the encrypted token, wherein the data parser is configured for determining a variable number of structure bits depending on at least a portion of the decrypted token or the clear data portion; and
wherein the data parser is configured to identify the structure bits in the decrypted token for the evaluator.
3. Apparatus according to claim 1, wherein the decryptor is configured to decrypt an encrypted token so that the decrypted token comprises a larger number of bits than the encrypted token.
4. Apparatus according to claim 1 in which the encrypted token additionally comprises a clear bit section and an encrypted section, the clear bit section comprising information on the product not relating to a level of product access; and
in which the decryptor is configured for only decrypting the encrypted section.
5. Apparatus according to claim 1 in which the evaluator is configured to use, in the evaluation, a higher number of structure bits when the number of information bits is lower or to use a lower number of structure bits when the number of information bits is higher.
6. Apparatus according to claim 1 in which the evaluator is configured to compare the structure bits or a value derived from the structure bits and other bits comprised in the decrypted token or a value derived from the other bits comprised in the decrypted token.
7. Apparatus according to claim 6 in which the other bits are the information bits, and
in which the evaluator is configured to use at least a portion of the information bits for evaluating, or
in which the encrypted token comprises clear bits,
in which the decryptor is configured not to decrypt the clear bits, and
in which the evaluator is configured to use at least a portion of the clear bits for evaluating; or
in which the other bits comprise random bits; and
in which the evaluator is configured to use at least a portion of the random bits for evaluating.
8. Apparatus according to claim 1 in which the decrypted token comprises less than or equal to 200 bits, the number of information bits is less than or equal to 100 bits, the number of structure bits is less than or equal to 100 bits; and
in which the decryptor is configured for performing a decryption comprising a block length equal to or less than 200 bits and in which the evaluator is configured for performing an operation related to a predetermined condition using a number width of equal to or less than 100 bits.
9. Method for verifying a validity of an encrypted token associated to a product, tile method comprising:
decrypting an encrypted token using a decryption key to acquire a decrypted token comprising information bits related to the product and to structure bits; and
evaluating whether the structure bits fullfill a predetermined condition, wherein the encrypted token is verified to be valid when the predetermined condition is fulfilled or is not verified to be valid when the predetermined condition is not fulfilled;
determining a level of product access in accordance with the information bits when the encrypted token is verified to be valid;
wherein a higher level of product access is determined when a number of information bits is lower and a lower level of product access is determined when a number of information bits is higher; and
wherein a higher level of product access allows a user to use more, more expensive or more complicated functions of the product and a lower level of product access allows the user to use less, less expensive or less complicated functions of the product.
10. A non-transitory storage medium having stored thereon a computer program comprising a program code for performing a method for verifying a validity of an encrypted token associated to a product, the method comprising:
decrypting an encrypted token using a decryption key to acquire a decrypted token comprising information bits related to the product and to structure bits; and
evaluating whether the structure bits fulfill a predetermined condition, wherein the encrypted token is verified to be valid when the predetermined condition is fulfilled or is not verified to be valid when the predetermined condition is not fulfilled;
determining a level of product access in accordance with the information bits when the encrypted token is verified to be valid;
wherein a higher level of product access is determined when a number of information bits is lower and a lower level of product access is determined when a number of information bits is higher; and
wherein a higher level of product access allows a user to use more, more expensive or more complicated functions of the product and a lower level of product access allows the user to use less, less expensive or less complicated functions of the product, when the computer program runs on a computer.