All The Claims

1. A trolling device for controlling a clutch oil pressure by rotationally operating a trolling lever,
the trolling device having a pressure reducing valve for reducing the clutch oil pressure and a low speed valve for adjusting the spring force of a pilot spring of the pressure reducing valve in conjunction with the trolling lever,
the low speed valve comprising a spool connected on the trolling lever unrotatably relative to a lever shaft of the trolling lever and freely slidably along the lever shaft, the spool having one end being in contact with the pilot spring, and the other end receiving primary pressure oil of the pressure reducing valve, a notch groove for discharging the pressure oil into a drain depending on the angle of rotational operation of the trolling lever being formed on a land of the spool, the trolling device being so constituted that forward and reverse clutches are fully engaged by bringing the notch groove into a closed position and a trolling state is attained by bringing the notch groove into an open position,
the pressure reducing valve comprising a spool provided with a pilot oil pressure chamber and an orifice formed therein, the pilot oil pressure chamber using the secondary pressure oil of the pressure reducing valve as a pilot pressure and the orifice for draining oil from the pilot oil pressure chamber to a drain,
the low speed valve having a protrusion which extends inside a coil spring constituting the pilot spring to the side of the pressure reducing valve and comes into contact with the pressure reducing valve at least when the forward and reverse clutches are fully engaged,
the protrusion having a drain oil passage which comes into communication with the orifice when in contact with the pressure reducing valve during trolling to discharge drain oil from the orifice.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A device comprising:
an output terminal;
a driver circuit configured to drive the output terminal to one of first and second voltages supplied from first and second source lines, respectively;
a control circuit configured to generate a first control signal and operating on third and fourth voltages supplied from third and fourth source lines that are provided independently of the first and second source lines; and
a buffer circuit configured to receive the first control signal to generate a second control signal and operating on the first and second voltages supplied from the first and second source lines,
wherein the driver circuit is configured to control a slew rate thereof based on the second control signal.
2. The device as claimed in claim 1, wherein the control circuit is configured to generate the first control signal having one of the third and fourth voltages, and the buffer circuit is configured to generate the second control signal having one of the first and second voltages.
3. The device as claimed in claim 1, further comprising a decoupling capacitor having a first electrode connected to the first source line and a second electrode connected to the second source line.
4. The device as claimed in claim 1, further comprising:
a first external terminal connected to the first source line and configured to receive the first source voltage from outside;
a second external terminal connected to the second source line and configured to receive the second source voltage from outside;
a third external terminal connected to the third source line and configured to receive the third source voltage from outside; and
a fourth external terminal connected to the fourth source line and configured to receive the fourth source voltage from outside.
5. The device as claimed in claim 1, further comprising an internal voltage generator configured to receive a fifth source voltage from outside to generate the third source voltage.
6. The device as claimed in claim 1, wherein the first and third source voltages have substantially the same value as each other, and the second and fourth source voltages have substantially the same value as each other.
7. The device as claimed in claim 1, further comprising a fuse circuit storing the first control signal.
8. A device comprising:
an output terminal;
a first transistor coupled between the output terminal and a first source line;
a second transistor coupled between the output terminal and a second source line;
a first circuit configured to supply a first data signal to a control electrode of the first transistor, the first data signal taking one of first and second logic levels based on a third data signal;
a second circuit configured to supply a second data signal to a control electrode of the second transistor, the second data signal taking one of the first and second logic levels based on a fourth data signal;
a third circuit configured to control a changing speed of the first control signal from the first logic level to the second logic level based on a first slew rate control signal on a first signal line;
a fourth circuit configured to control a changing speed of the second control signal from the second logic level to the first logic level based on a second slew rate control signal on a second signal line;
a first buffer circuit configured to generate the first slew rate control signal such that the first signal line is connected to one of the first and second source lines; and
a second buffer circuit configured to generate the second slew rate control signal such that the second signal line is connected to one of the first and second source lines.
9. The device as claimed in claim 8, wherein
the first buffer circuit generates the first slew rate control signal based on a third slew rate control signal on a third signal line,
the second buffer circuit generates the second slew rate control signal based on a fourth slew rate control signal on a fourth signal line,
the third signal line is connected to one of third and fourth source lines,
the fourth signal line is connected to one of the third and fourth source lines, and
the third and fourth source lines are provided independently of the first and second source lines.
10. The device as claimed in claim 9, further comprising:
a first external terminal coupled to the first source line,
a second external terminal coupled to the second source line,
a third external terminal coupled to the third source line, and
a fourth external terminal coupled to the fourth source line.
11. The device as claimed in claim 10, wherein the first and third external terminals are supplied with a first voltage, and the second and fourth external terminals are supplied with a second voltage different from the first voltage.
12. The device as claimed in claim 9, further comprising a fuse circuit storing values of the third and fourth slew rate control signals.
13. A device comprising:
first and second terminals between which a first power voltage is supplied;
third and fourth terminals between which a second power supply voltage is supplied;
a fifth terminal;
a first circuit coupled between the first and second terminals and configured to operate on the first power voltage to produce a first set of slew rate control signals;
a second circuit coupled to between the third and fourth terminals and configured to operate on the second power voltage to produce a second set of slew rate control signals in response to the first set of slew rate control signals; and
a third circuit coupled between the third and fourth terminals and configured to operate on the second power voltage to drive the fifth terminal at a rate that is controllable in response to the second set of slew rate control signals.
14. The device as claimed in claim 13, further comprising:
first and second power lines elongated respectively from the first and second terminals to the first circuit; and
third and fourth power lines elongated respectively from the third and fourth terminals independently of the first and second power lines, the third and fourth power lines reaching each of the second and third circuits.
15. The device as claimed in claim 13, wherein the first power voltage is substantially equal to the second power voltage.
16. The device as claimed in claim 13, further comprising:
an internal voltage generator coupled between the first and second terminals and configured to operate on the first power voltage to generate an internal voltage that is different from the first power voltage; and
a fourth circuit operating on the internal voltage to produce a third set of slew rate control signals;
the first circuit responding to the third set of slew rate control signals to produce the first set of slew rate control signals.
17. The device as claimed in claim 16, wherein the internal voltage is lower than the first power voltage.
18. The device as claimed in claim 13, further comprising a capacitor connected between the third and fourth terminals.
19. The device as claimed in claim 13, wherein the second circuit comprises at least one inverter.
20. The device as claimed in claim 13, further comprising:
first and second power lines elongated respectively from the first and second terminals to the first circuit to convey the first power voltage to the first circuit; and
third and fourth power lines elongated respectively from the third and fourth terminals independently of the first and second power lines, the third and fourth power lines reaching each of the second and third circuits to convey the second power voltage to each of the second and third circuits;
the first power voltage being substantially equal to the second power voltage.

1. A device comprising:
a memory with a first memory pad to an ith memory pad and a jth memory pad to a kth (1<i<j<k) memory pad;
an integrated circuit device, wherein the memory is stacked on the integrated circuit device, the integrated circuit device comprising:
a first pad to an ith pad connected to the first memory pad to the ith memory pad;
a jth pad to a kth pad connected to the jth memory pad to the kth (1<i<j<k) memory pad; and
at least one pad arranged between the ith pad and the jth pad, wherein the at least one pad is not connected to a memory pad of the memory and serves as a pad for inputting or outputting a signal between an external device and the integrated circuit device, and

a power supply pad that is not connected to a substrate that supports the first pad to the ith pad, the jth pad to the kth pad and the at least one pad but is instead arranged on the memory between the ith memory pad and the jth memory pad, wherein the power supply pad is not connected to the first pad to the ith pad, the jth pad to the kth pad and the at least one pad.
2. The device according to claim 1, further comprising a control unit that performs read-control and write-control over data in the memory, wherein
the control unit performs read-control and write-control over data of the memory in a stack mode in which a chip of the memory is stacked on the integrated circuit device and performs read-control and write-control over data of an external memory in a non-stack mode in which the chip of the memory is not stacked on the integrated circuit device; and
the at least one pad arranged between the ith pad and the jth pad serves as a non-stack mode pad for outputting or inputting at least one of a data signal, an address signal and a control signal from or to the external memory in the non-stack mode.
3. The device according to claim 1, wherein no memory pad is arranged between the ith memory pad and the jth memory pad.
4. The device according to claim 3, wherein the relation: LDS\u22672LP, where LDS is a distance between the ith memory pad and the jth memory pad and LP is the arrangement pitch between memory pads, is satisfied.
5. The device according to claim 1, wherein the first memory pad to the ith memory pad and the jth memory pad to the kth memory pad are included in a first memory pad group arranged along a first chip side of the chip of the memory or included in a second memory pad group arranged along a third chip side on the opposite of the first chip side of the chip of the memory; and
the first pad to the ith pad and the jth pad to the kth pad are included in a first pad group arranged along a first side of the integrated circuit device or included in a second pad group arranged along a third side on the opposite side of the first side of the integrated circuit device.
6. The device according to claim 5, wherein
the memory is an image memory that stores image data; and
a control unit performs display control over an electro-optical apparatus on the basis of image data stored in the image memory.
7. The device according to claim 6, comprising:
the first pad group arranged along the first side of the integrated circuit device and connected to the first memory pad group arranged along the first chip side of the chip of the image memory;
the second pad group arranged along the third side of integrated circuit device and connected to the second memory pad group arranged along the third chip side of the chip of the image memory; and
a third pad group that receives the output of a data signal and a control signal for display control over the electro-optical apparatus and are arranged along a second side crossing the first side and the third side of the integrated circuit device.
8. The device according to claim 7, further comprising a fourth pad group for host interface, wherein
the fourth pad group is arranged along a fourth side on the opposite side of the second side of the integrated circuit device.
9. The device according to claim 7, further comprising a fifth pad group that receives the output of a signal for control over a power supply circuit in the electro-optical apparatus, wherein
the fifth pad group is arranged along the second side of the integrated circuit device.
10. The device according to claim 7, wherein
the control unit performs display control over the electro-optical apparatus on the basis of the image data from the image memory in the stack mode in which the chip of the image memory is stacked on the integrated circuit device and performs display control over the electro-optical apparatus on the basis of external image data from an external image memory in the non-stack mode in which the chip of the image memory is not stacked on the integrated circuit device.
11. The device according to claim 10, further comprising a stack identification pad that is set to a first power supply voltage in the stack mode with a bonding wire and is set to a second power supply voltage in the non-stack mode with the bonding wire.
12. The device according to claim 7, further comprising:
a host interface that performs interface processing tofrom a host; and
an information register that provides information to the host,
wherein
the information register stores instruction select information for selecting instruction code information describing instruction code, the instruction code configuring a command issued by the host;
the instruction code information selected on the basis of the instruction select information stored in the information register from a plurality of instruction code information pieces is loaded to an information memory when electronic equipment including the electro-optical apparatus is utilized; and
the control unit performs operational control over the integrated circuit device on the basis of the command issued by the host and the instruction code information read from the information memory when the electronic equipment operates.
13. The device according to claim 12, wherein
the information register stores stack identification information for identifying, as the instruction select information, the stack mode in which the chip of the image memory that stores image data is stacked on the integrated circuit device or the non-stack mode in which the chip of the image memory is not stacked on the integrated circuit device.
14. The device according to claim 13, wherein
in the stack mode, when the electronic equipment is utilized, instruction code information for the stack mode from the plurality of instruction code information pieces is loaded to the information memory, and, when the electronic equipment operates, operational control is performed over the integrated circuit device on the basis of the command issued by the host and the instruction code information for the stack mode; and
in the non-stack mode, when the electronic equipment is utilized, instruction code information for the non-stack mode from the plurality of instruction code information pieces is loaded to the information memory, and, when the electronic equipment operates, operational control is performed over the integrated circuit device on the basis of the command issued by the host and the instruction code information for the non-stack mode.
15. The device according to claim 13, further comprising a stack identification pad that is set to a first power supply voltage with a bonding wire in the stack mode and is set to a second power supply voltage with a bonding wire in the non-stack mode, wherein
the information register stores the stack identification information set on the basis of the voltage of the pad for stack identification.
16. Electronic equipment comprising the device according to claim 1.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A light quantity measuring device comprising:
a first light reception element that receives a predetermined incident light at a first light reception surface;
a second light reception element that receives the incident light at a second light reception surface, which is oriented in the same direction as the first light reception surface;
an identification circuit that identifies an incident angle of the incident light with respect to the first light reception surface; and
a selection circuit that, when the incident angle differs from a desired incident angle, selectively electrically connects an output portion of the second light reception element to an output portion of the first light reception element.
2. The light quantity measuring device according to claim 1, wherein a plurality of the second light reception elements are provided, and the respective light reception surfaces thereof have different areas.
3. The light quantity measuring device according to claim 2, wherein the selection circuit selectively electrically connects the output portions of the second light reception elements with the output portion of the first light reception element, so as to compensate for a reduction in a received light quantity due to the incident angle differing from the desired incident angle, via switching elements that, individually and in parallel, switch between connecting or not connecting at least one of the plurality of second light reception elements to the first light reception element.