All The Claims

1. A logic circuit comprising:
a dynamic logic portion for evaluating a Boolean function of a plurality of data input signals, wherein a logic signal on a dynamic node asserted in response to a first logic state of a clock signal comprises either a logic true or a logic false Boolean combination of the plurality of the data input signals and the dynamic node is pre-charged to a first logic state corresponding to the logic false Boolean combination when the clock signal has a second logic state;
a static portion having a pull-down input, a data input coupled to the dynamic node, a data output node generating a latched data output signal in response to the logic signal and the clock signal, and an inverted data output node generating a latched inverted data output signal as the logic inversion of the latched data output signal, wherein the inverted data output node is set to a logic zero when the pull-down input is a logic one and the inverted data output node is held at a logic zero when the data output signal is a logic one; and
a feedforward pulse circuit having a first input coupled to the dynamic node, a second input coupled to the inverted data output node, and a pulse node coupled to the pull-down input and generating a feedforward pulse, wherein the feedforward pulse is a logic one when the dynamic node is a logic zero and the inverted data output signal is a logic one.
2. The logic circuit of claim 1, wherein the dynamic logic portion comprises:
a first P channel field effect transistor (PFET) having a gate terminal coupled to the clock signal, a source terminal coupled to a positive power supply voltage and a drain terminal coupled to the dynamic node, wherein the dynamic node is coupled to the positive power supply voltage in response to the first logic state of the clock signal and isolated from the positive power supply voltage in response to a second logic state of the clock signal;
a logic tree having a plurality of logic inputs, a positive tree terminal coupled to the dynamic node, and a negative tree terminal, wherein the positive tree terminal is coupled to the negative tree terminal in response to first logic states of the plurality of logic inputs and isolated from the negative tree terminal in response to second logic states of the plurality of logic inputs; and
a first N channel FET (NFET) having a gate terminal coupled to the clock signal, a drain terminal coupled to the negative tree terminal and a source terminal coupled to a negative power supply voltage, wherein the negative tree terminal is coupled to the negative power supply voltage in response to the second logic state of the clock signal and isolated from the negative power supply voltage in response to a first logic state of the clock signal.
3. The logic of claim 1 wherein the static portion comprises:
a first PFET having a gate coupled to the dynamic node, a source coupled to the first power supply voltage and a drain;
a first NFET having a gate coupled to the gate of the first PFET, a drain coupled to the drain of the first PFET for a data output node generating the data output signal, and a source;
a second NFET having a gate coupled to the second clock signal, a source coupled to the second power supply voltage and a drain coupled to the source of the first NFET;
a third NFET having a drain coupled to the drain of the second NFET, a source coupled to the second power supply voltage and a gate;
an inverting circuit having an input coupled to the data output node and an output coupled to the inverted data output node;
a fourth NFET having a source coupled to the second power supply voltage, a drain coupled to the inverted data output node, and a gate coupled to the pull-down input; and
and a second PFET having a gate coupled to the output node of the inverting circuit, a drain coupled to the data output node and a source coupled to the first power supply voltage.
4. The logic circuit of claim 1, wherein the feedforward pulse circuit comprises:
a first NFET having a source coupled to the second power supply voltage, a drain and a gate coupled to the dynamic node;
a first PFET having a drain coupled to the drain of the first NFET forming the pulse node, a gate coupled to the dynamic node and a source;
a second PFET having a drain coupled to the source of the first PFET, a source coupled to the first power supply voltage and a gate; and
an inverter having an input coupled to the inverted data output node, and output coupled to the gate of the first PFET.
5. The logic circuit of claim 3, wherein the inverting circuit comprises:
a third PFET having a gate coupled to the data output node, a source coupled to the first power supply voltage and a drain; and
a fifth NFET having a gate coupled to the gate of the third PFET, a source coupled to the second power supply voltage and a drain coupled to the drain of the third PFET forming the inverted data output node.
6. The logic circuit of claim 5, wherein the fourth NFET is substantially larger than the fifth NFET.
7. The logic circuit of claim 6, wherein the fourth NFET is about ten times larger than the fifth NFET.
8. The logic circuit of claim 6, wherein all PFETs and all NFETs in a logic path driving the fifth NFET may be made smaller when the fourth NFET is made substantially larger than the fifth NFET.
9. A data processing system comprising:
a central processing unit (CPU); and
a memory operable for communicating instructions and operand data to the CPU which includes a logic system having a logic circuit with a dynamic logic portion for evaluating a Boolean function of a plurality of data input signals, wherein a logic signal on a dynamic node asserted in response to a first logic state of a clock signal comprises either a logic true or a logic false Boolean combination of the plurality of the data input signals and the dynamic node is pre-charged to a first logic state corresponding to the logic false Boolean combination when the clock signal has a second logic state, a static portion having a pull-down input, a data input coupled to the dynamic node, a data output node generating a latched data output signal in response to the logic signal and the clock signal, and an inverted data output node generating a latched inverted data output signal as the logic inversion of the latched data output signal, wherein the inverted data output node is set to a logic zero when the pull-down input is a logic one and the inverted data output node is held low when the data output signal is a logic one; and a feedforward pulse circuit having a first input coupled to the dynamic node, a second input coupled to the inverted data output node, and a pulse node coupled to the pull-down input and generating a feedforward pulse, wherein the feedforward pulse is a logic one when the dynamic node is a logic zero and the inverted data output signal is a logic one.
10. The data processing system of claim 9, wherein the dynamic logic portion comprises:
a first P channel field effect transistor (PFET) having a gate terminal coupled to the clock signal, a source terminal coupled to a positive power supply voltage and a drain terminal coupled to the dynamic node, wherein the dynamic node is coupled to the positive power supply voltage in response to the first logic state of the clock signal and isolated from the positive power supply voltage in response to a second logic state of the clock signal;
a logic tree having a plurality of logic inputs, a positive tree terminal coupled to the dynamic node, and a negative tree terminal, wherein the positive tree terminal is coupled to the negative tree terminal in response to first logic states of the plurality of logic inputs and isolated from the negative tree terminal in response to second logic states of the plurality of logic inputs; and
a first N channel FET (NFET) having a gate terminal coupled to the clock signal, a drain terminal coupled to the negative tree terminal and a source terminal coupled to a negative power supply voltage, wherein the negative tree terminal is coupled to the negative power supply voltage in response to the second logic state of the clock signal and isolated from the negative power supply voltage in response to a first logic state of the clock signal.
11. The data processing system of claim 9 wherein the static portion comprises:
a first PFET having a gate coupled to the dynamic node, a source coupled to the first power supply voltage and a drain;
a first NFET having a gate coupled to the gate of the first PFET, a drain coupled to the drain of the first PFET for a data output node generating the data output signal, and a source;
a second NFET having a gate coupled to the second clock signal, a source coupled to the second power supply voltage and a drain coupled to the source of the first NFET;
a third NFET having a drain coupled to the drain of the second NFET, a source coupled to the second power supply voltage and a gate;
an inverting circuit having an input coupled to the data output node and an output coupled to the inverted data output node;
a fourth NFET having a source coupled to the second power supply voltage, a drain coupled to the inverted data output node, and a gate coupled to the pull-down input; and
and a second PFET having a gate coupled to the output node of the inverting circuit, a drain coupled to the data output node and a source coupled to the first power supply voltage.
12. The data processing system of claim 9, wherein the feedforward pulse circuit comprises:
a first NFET having a source coupled to the second power supply voltage, a drain and a gate coupled to the dynamic node;
a first PFET having a drain coupled to the drain of the first NFET forming the pulse node, a gate coupled to the dynamic node and a source;
a second PFET having a drain coupled to the source of the first PFET, a source coupled to the first power supply voltage and a gate; and
an inverter having an input coupled to the inverted data output node, and output coupled to the gate of the first PFET.
13. The data processing system of claim 11, wherein the inverting circuit comprises:
a third PFET having a gate coupled to the data output node, a source coupled to the first power supply voltage and a drain; and
a fifth NFET having a gate coupled to the gate of the third PFET, a source coupled to the second power supply voltage and a drain coupled to the drain of the third PFET forming the inverted data output node.
14. The data processing system of claim 13, wherein the fourth NFET is substantially larger than the fifth NFET.
15. The data processing system of claim 14, wherein the fourth NFET is about ten times larger than the fifth NFET.
16. The logic circuit of claim 14, wherein all PFETs and all NFETs in a logic path driving the fifth NFET may be made smaller when the fourth NFET is made substantially larger than the fifth NFET.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An internal combustion engine assembly, comprising:
an engine blocking having a crankcase portion adjacent a cylinder case portion, the cylinder case portion defining at least one cylinder bore therein;
an air intake system in fluid communication with the at least one cylinder bore and configured to selectively deliver air-charges thereto;
a valve cover operatively attached to the engine block, and in fluid communication with the crankcase portion to receive blowby gases therefrom; and
A sound dissipating resonator having a resonator body defining a resonator volume therein, wherein the resonator body is in fluid communication with the valve cover and with the air intake system, whereby blowby gases are delivered from the valve cover to a blowby breather pipe disposed within the resonator body and configured to deliver blow by gases to the air intake system.
2. The internal combustion engine assembly of claim 1, further comprising:
an oil separation unit fluidly communicating the valve cover with the resonator, and configured to separate entrained oil particulates from blowby gases evacuated therethrough from the crankcase portion.
3. The internal combustion engine assembly of claim 2, wherein the oil separation unit is positively attached to the valve cover between the valve cover and the resonator.
4. The internal combustion engine assembly of claim 1, wherein the resonator body defines a fluid inlet port having a first diameter and a fluid outlet port having a second diameter.
5. The internal combustion engine assembly of claim 4, further comprising:
a first connection neck in fluid communication between the inlet port and the valve cover, and having a third diameter that is greater than the first diameter; and
a second connection neck in fluid communication between the outlet port and the air intake system, and having a fourth diameter that is greater than the second diameter.
6. The internal combustion engine assembly of claim 5, wherein a first and a second seal member respectively fluidly seal the connections between the first and second connection necks and the fluid inlet and outlet ports.
7. The internal combustion engine assembly of claim 5, wherein:
The blowby breather pipe and is in fluid communication with both the fluid inlet and outlet ports.
8. The internal combustion engine assembly of claim 7, further comprising:
a first blowby vent at least partially located inside the first connection neck and fluidly communicating the valve cover with the blowby breather pipe; and
a second blowby vent at least partially located inside the second connection neck and fluidly communicating the air intake system with the blowby breather pipe.
9. The internal combustion engine assembly of claim 7, wherein a third and a fourth seal member respectively fluidly seal the connections between the blowby breather pipe and the first and second blowby vents.
10. The internal combustion engine assembly of claim 1, further comprising:
a supercharging device in fluid communication with the air intake system and configured to provide compressed airflow thereto, the supercharging device having an air inlet hose in fluid communication with the resonator body to receive blowby gases therefrom.
11. The internal combustion engine assembly of claim 10, wherein the supercharging device includes a compressor blade rotatably disposed in a compressor housing and configured for compressing airflow, and a turbine blade rotatably disposed in a turbine housing, the turbine blade being attached to the compressor blade for unitary rotation therewith, the turbine housing being configured to redirect exhaust flow from the internal combustion engine to spin the turbine blade.
12. The internal combustion engine assembly of claim 1, wherein the resonator is positively attached to the engine block.
13. An internal combustion engine assembly, comprising:
an engine block having a crankcase portion configured to at least partially house a crankshaft, and a cylinder case portion proximate to the crankcase portion and defining a plurality of cylinder bores therein, each of the plurality of cylinder bores having a piston reciprocally movable therein;
an air intake system in fluid communication with each of the plurality of cylinder bores and configured to selectively deliver air-charges thereto;
a valve cover operatively attached to the engine block, and in fluid communication with the crankcase portion to receive blowby gases therefrom;
an oil separation unit positively attached to and in fluid communication with the valve cover, and configured to separate entrained oil particulates from blowby gases evacuated therethrough from the valve cover;
a sound dissipating resonator positively attached to the engine block and having a resonator body defining a resonator volume therein, the resonator body in fluid communication with the oil separation unit and with the air intake system, whereby blowby gases are evacuated from the oil separation unit and delivered to the air intake system through the resonator volume; and
a blowby breather pipe disposed within the resonator body and configured to deliver the blowby gases through the resonator volume.
14. The internal combustion engine assembly of claim 13, further comprising:
a supercharging device in fluid communication with the air intake system and configured to provide compressed airflow thereto, the supercharging device having an air inlet hose in fluid communication with the resonator body to receive blowby gases therefrom for reintroduction to the air intake system.
15. The internal combustion engine assembly of claim 14, wherein the resonator body defines a fluid inlet port having a first diameter and a fluid outlet port having a second diameter.
16. The internal combustion engine assembly of claim 15, further comprising:
a first connection neck operatively attached to and fluidly communicating the inlet port of the resonator with the oil separation unit, the first connection neck having a third diameter that is greater than the first diameter; and
a second connection neck operatively attached to and fluidly communicating the outlet port of the resonator with the air inlet hose of the supercharging device, the second connection neck having a fourth diameter that is greater than the second diameter.
17. The internal combustion engine assembly of claim 16, wherein the blowby breather pipe is in fluid communication with both the fluid inlet and outlet ports.
18. An internal combustion engine assembly, comprising:
an engine block having a crankcase portion at least partially housing a crankshaft therein, and a cylinder case portion having first and second cylinder banks each of which defines at least one cylinder bore therein, each of the at least one cylinder bores having a piston reciprocally movable therein and operatively connected to the crankshaft, wherein the first and second cylinder banks are oriented with respect to one another such that they form an angle of less than 180 degrees and define a generally V-shaped interbank valley therebetween;
an air intake system in fluid communication with each of the at least one cylinder bores and configured to selectively deliver air-charges thereto;
a cam cover operatively attached to the engine block and configured to at least partially house a camshaft therein, wherein the cam cover is in fluid communication with the crankcase portion to receive blowby gases therefrom;
an oil separation unit positively attached to and in fluid communication with the cam cover, and configured to separate entrained oil particulates from blowby gases evacuated therethrough from the cam cover;
a sound dissipating resonator positively attached to the engine block and having a resonator body defining a resonator volume therein, the resonator body in fluid communication with the oil separation unit and with the air intake system, whereby blowby gases are evacuated from the oil separation unit and delivered to the air intake system through the resonator volume;
a blowby breather pipe disposed within the resonator body and configured to deliver the blowby gases through the resonator volume;
a turbocharger device at least partially located within the V-shaped interbank valley, the turbocharger device being in fluid communication with the air intake system and configured to provide compressed airflow thereto, wherein the turbocharger device has an air inlet hose in fluid communication with the resonator body to receive blowby gases therefrom for reintroduction to the air intake system;
wherein the resonator body defines a fluid inlet port having a first diameter and a fluid outlet port having a second diameter, the blowby breather pipe being in fluid communication with the fluid inlet port and the fluid outlet port; and
a plurality of apertures defined by the fluid inlet port and the fluid outlet port and radially outwards of the blowby breather pipe, the plurality of apertures being configured to provide an alternate flow path into the resonator.
19. The internal combustion engine assembly of claim 4, further comprising:
a plurality of apertures defined by the fluid inlet port and the fluid outlet port and radially outwards of the blowby breather pipe, the plurality of apertures being configured to provide an alternate flow path into the resonator.

1. An individualized dental product ready for application, the product comprising:
at least one tooth veneer which is of a ceramic material, is plate-like and has a plate thickness of at least about 0.08 mm, wherein the thickness is less than about 0.2 mm.
2. A dental product according to claim 1, wherein each of the at least one tooth veneer is individually designed to match a part of a predetermined tooth that is to be covered by that veneer
3. A dental product according to claim 1, wherein each of the at least one veneer is individually designed to correspond to a part of a non-prepared tooth that is to be covered by that veneer.
4. A dental product according to claim 1, wherein the ceramic material is translucent.
5. A dental product according to claim 1, wherein the product comprises a plurality of tooth veneers.
6. A dental product according to claim 1, wherein the product is associated with a first and a second part for sandwiching one of the at least one tooth veneer thereinbetween, wherein the first part is provided with a shape for fittingly matching one side of one of the at least one plate-like tooth veneer and the second part is arranged for releasably bonding another side of the at least one plate-like tooth veneer against the second part and optionally comprises at least one grasp holder.
7. A dental product according to claim 6, wherein the first part and the second part are releasably securable to each other when the first part and second part are sandwiching the at least one tooth veneer.
8. A dental product according to claim 6, wherein the first part comprises a model of at least a part of a person’s set of teeth.
9. A dental product according to claim 1, wherein the ceramic material is glass ceramic material.
10. A dental product according to claim 6, wherein the second part comprises a foil.
11. A dental product according to claim 8, wherein the model is associated with a support for supporting the model, the support and the model being positionally fixed or fixable relative to each other, wherein the support is associated with a container and wherein the support has dimensions for holding the model stable in the container.
12. A dental product according to claim 1, wherein the at least one tooth veneer comprises a pre-treated bonding material.
13. A dental product according to claim 12, wherein the bonding material comprises at least one coloring material and the at least one tooth veneer is at least partially transparent or translucent.
14. A method of improving the aesthetics of a tooth, wherein the method comprises placing a dental product as defined in claim 1, onto a tooth surface.
15. A dental product according to claim 1, wherein the thickness is less than about 0.14 mm.
16. A dental product according to claim 1, wherein the thickness is less than about 0.1 mm.
17. A dental product according to claim 6, wherein the second part comprises at least one grasp holder.
18. A dental product according to claim 9, wherein the glass ceramic material includes a Li disilicate glass ceramic.
19. A dental product according to claim 1, wherein the ceramic material includes a microwave sintered aluminum oxide ceramic.
20. A dental product according to claim 11, wherein the support and model are integrally connected to each other.
21. A dental product according to claim 12, wherein the pre-treated bonding material includes an at least partially cured bonding material cured before application to a tooth.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for accessing a secure user area of a physical storage device, the method comprising:
performing by a physical storage device that has a physical storage medium including a clear user area and a secure user area, wherein the clear user area is in a first range of physical addresses in the storage medium, wherein the secure user area is in a second range of physical addresses in the storage medium, wherein the clear user area and the secure user area are physically separate areas in the storage medium, and wherein the physical storage device is operative to allow access to the clear user area without requiring a user password and to allow access to the secure user area only upon receiving the user password:
receiving the user password from a host device in communication with the physical storage device; and
performing at least one of (a) and (b):
(a) receiving data from the host device, performing on-the-fly encryption of the data, and storing the encrypted data in the secure user area; and
(b) reading encrypted data from the secure user area, performing on-the-fly decryption of the encrypted data, and sending the decrypted data to the host device.
2. The method of claim 1 further comprising determining that the user password is valid by comparing the user password with a stored password.
3. The method of claim 1 further comprising determining that the user password is valid by hashing the user password and comparing the hashed user password to a stored hashed password.
4. The method of claim 1, wherein the physical storage device stores a key used for at least one of on-the-fly encryption and on-the-fly decryption.
5. The method of claim 4, wherein the key is encrypted with the user password.
6. The method of claim 1, wherein the physical storage device is operative to access the secure user area by offsetting a logical address received from the host device by an offset parameter before transforming the logical address to a physical address.
7. The method of claim 6, wherein the offsetting is performed after the host device remounts the physical storage device.
8. The method of claim 1 further comprising configuring a size of the secure user area based on a request by a user.
9. The method of claim 8, wherein the configuring is performed by a program stored in the physical storage device and executed by the physical storage device.
10. The method of claim 8, wherein the configuring is performed only after determining that the user password is valid.
11. A physical storage device comprising:
an interface to a host device; and
a physical storage medium including a clear user area and a secure user area, wherein the clear user area is in a first range of physical addresses in the storage medium, wherein the secure user area is in a second range of physical addresses in the storage medium, and wherein the clear user area and the secure user area are physically separate areas in the storage medium;
wherein the physical storage device is operative to allow access to the clear user area without requiring a user password and to allow access to the secure user area only upon receiving the user password; and
wherein the physical storage device is further operative to:
receive the user password from the host device via the interface; and
perform at least one of (a) and (b):
(a) receive data from the host device, perform on-the-fly encryption of the data, and store the encrypted data in the secure user area; and
(b) read encrypted data from the secure user area, perform on-the-fly decryption of the encrypted data, and send the decrypted data to the host device.
12. The physical storage device of claim 11, wherein the physical storage device is operative to determine that the user password is valid by comparing the user password with a stored password.
13. The storage device of claim 11, wherein the physical storage device is operative to determine that the user password is valid by hashing the user password and comparing the hashed user password to a stored hashed password.
14. The storage device of claim 11, wherein the physical storage medium stores a key used for at least one of on-the-fly encryption and on-the-fly decryption.
15. The storage device of claim 14, wherein the key is encrypted with the user password.
16. The storage device of claim 11, wherein the physical storage device is operative to access the secure user area by offsetting a logical address received from the host device by an offset parameter before transforming the logical address to a physical address.
17. The storage device of claim 16, wherein the offsetting is performed after the host device remounts the physical storage device.
18. The storage device of claim 11, wherein the physical storage device is operative to configure a size of the secure user area based on a request by a user.
19. The storage device of claim 18, wherein the physical storage device is operative to configure the size of the secure user area by executing a program stored in the physical storage device.
20. The storage device of claim 18, wherein the physical storage device is operative to configure the size of the secure user only after determining that the user password is valid.