All The Claims

1. A multilayer capacitor comprising:
a capacitor body having a multilayer structure including a plurality of stacked dielectric layers, and having a substantially rectangular parallelepiped shape including a first principal surface and a second principal surface extending substantially parallel to surfaces of the dielectric layers and opposed to each other, a first side surface and a second side surface opposed to each other, and a first end surface and a second end surface opposed to each other, the first and second end surfaces having a length greater than a length of the first and second side surfaces; and
a first external terminal electrode and a second external terminal electrode provided on the first end surface and on the second end surface of the capacitor body, respectively; wherein
the capacitor body includes a first capacitor portion and a second capacitor portion arranged adjacently in a direction in which the dielectric layers are stacked;
the first capacitor portion includes a first internal electrode and a second internal electrode opposed to each other with a dielectric layer therebetween to provide electrostatic capacity;
the second capacitor portion includes a third internal electrode and a fourth internal electrode opposed to each other with a dielectric layer therebetween to provide electrostatic capacity;
the first internal electrode includes a first capacity portion and a first lead portion which is led out from the first capacity portion to extend to the first end surface and which is electrically connected to the first external electrode;
the second internal electrode includes a second capacity portion opposed to the first capacity portion via a dielectric layer, and a second lead portion which is led out from the second capacity portion to extend to the second end surface and which is electrically connected to the second external electrode;
the third internal electrode includes a third capacity portion and a third lead portion which is led out from the third capacity portion to extend to the first end surface and which is electrically connected to the first external electrode;
the fourth internal electrode includes a fourth capacity portion opposed to the third capacity portion via a dielectric layer, and a fourth lead portion which is led out from the fourth capacity portion to extend to the second end surface and which is electrically connected to the second external electrode; and
the third lead portion includes a region that is narrower than the first lead portion.
2. The multilayer capacitor according to claim 1, wherein the fourth lead portion includes a region that is narrower than the second lead portion.
3. The multilayer capacitor according to claim 1, wherein, in the second capacitor portion, a plurality of third internal electrodes are arranged continuously in a stacking direction of the dielectric layers.
4. The multilayer capacitor according to claim 1, wherein the second capacitor portion is sandwiched between two first capacitor portions in the capacitor body, and the capacitor body is arranged to be mounted on a mounting surface such that one of the first and second principal surfaces is arranged to face the mounting surface.
5. A multilayer capacitor comprising:
a capacitor body having a multilayer structure including a plurality of stacked dielectric layers, and having a substantially rectangular parallelepiped shape including a first principal surface and a second principal surface opposed to each other, a first side surface and a second side surface extending substantially parallel to surfaces of the dielectric layers and opposed to each other, and a first end surface and a second end surface opposed to each other; and
a first external terminal electrode and a second external terminal electrode provided on at least the second principal surface of the capacitor body and arranged to be isolated from each other; wherein
the capacitor body includes a first capacitor portion and a second capacitor portion arranged adjacently in a direction in which the dielectric layers are stacked;
the first capacitor portion includes a first internal electrode and a second internal electrode opposed to each other with a dielectric layer therebetween to provided electrostatic capacity;
the second capacitor portion includes a third internal electrode and a fourth internal electrode opposed to each other with a dielectric layer therebetween to provide electrostatic capacity;
the first internal electrode includes a first capacity portion and a first lead portion which is led out from the first capacity portion to extend to the second principal surface and which is electrically connected to the first external electrode;
the second internal electrode include a second capacity portion opposed to the first capacity portion via a dielectric layer, and a second lead portion which is led out from the second capacity portion to extend to the second principal surface and which is electrically connected to the second external electrode;
the third internal electrode includes a third capacity portion and a third lead portion which is led out from the third and is electrically connected to the first external electrode;
the fourth internal electrode includes a fourth capacity portion opposed to the third capacity portion via a dielectric layer, and a fourth lead portion which is led out from the fourth capacity portion and is electrically connected to the second external electrode;
the third lead portion includes a region that is narrower than the first lead portion when the third lead portion and the first lead portion are compared in the same direction; and
the multilayer capacitor arranged to be mounted on a mounting surface with the second principal surface arranged to face a mounting surface.
6. The multilayer capacitor according to claim 5, wherein the third lead portion and the fourth lead portion extend to the second principal surface.
7. The multilayer capacitor according to claim 5, wherein the first external terminal electrode is arranged to extend from the second principal surface to at least the first end surface, the third lead portion is arranged to extend to the first end surface for electrical connection with the first external terminal electrode, the second external terminal electrode is arranged to extend from the second principal surface to at least the second end surface, and the fourth lead portion is arranged to extend to the second end surface for electrical connection with the second external terminal electrode.
8. The multilayer capacitor according to claim 5, wherein the first external terminal electrode is arranged to extend from the second principal surface to the first principal surface through the first end surface and through the first and second side surfaces, and the second external terminal electrode is arranged to extend from the second principal surface to the first principal surface through the second end surface and through the first and second side surfaces.
9. The multilayer capacitor according to claim 5, wherein the fourth lead portion includes a region that is narrower than the second lead portion when the fourth lead portion and the second lead portion are compared in the same direction.
10. The multilayer capacitor according to claim 5, wherein, in the second capacitor portion, a plurality of third internal electrodes are arranged continuously in a stacking direction of the dielectric layers.
11. The multilayer capacitor according to claim 5, wherein the second capacitor portion is sandwiched between two first capacitor portions in the capacitor body.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. An antisense oligonucleotide or analog thereof comprising 10 or more contiguous bases or base analogs from the sequence of bases of sequence A, B, C, D, E, F, G, H, I, J, K, L, or M of FIG. 1.
2. An antisense oligonucleotide or analog thereof comprising a sequence having 90% of greater identity to sequence A, B, C, D, E, F, G, H, I, J, K, L, or M of FIG. 1.
3. An antisense oligonucleotide or analog thereof comprising nucleotide sequence A, B, C, D, E, F, G, H, I, J, K, L, or M of FIG. 1.
4. The antisense oligonucleotide of claim 3, wherein the nucleotide sequence comprises nucleotide sequence A, A, B, C, C, D, E, E, F, G, G, H, H, I, I, J, K, K, L, L, M, or M of FIGS. 2A and 2B.
5. The antisense oligonucleotide of claim 3, wherein the oligonucleotide is conjugated to a peptide.
6. The antisense oligonucleotide of claim 3, wherein the oligonucleotide is encapsulated in a liposome or nanoparticle.
7. The antisense oligonucleotide of claim 3, wherein the phosphate backbone comprises phosphorothioate bonds.
8. The antisense oligonucleotide of claim 3, wherein the backbone is bonded to one or more lipid substituents.
9. The antisense oligonucleotide of claim 3, wherein one or more of the oligonucleotide’s sugars contain an -OMe group at their 2 position.
10. The antisense oligonucleotide of claim 3, wherein the phosphate backbone consists essentially of phosphorothioate bonds.
11. The antisense oligonucleotide of claim 7, wherein the phosphorothioate is stereo regular.
12. The antisense oligonucleotide of claim 3, wherein the oligonucleotide is linked to an intercalating agent, a cross-linker, an endonuclease, a lipophilic carrier, an alkylating agent, a coordination complex, or a peptide conjugate, or a combination thereeof
13. The antisense oligonucleotide of claim 3, wherein the oligonucleotide is modified to reduce its ionic charge or increase its hydrophobicity.
14. The antisense oligonucleotide of claim 13, wherein the oligonucleotide comprises one or more short chain alkyl structures that replace some of the oligonucleotide’s phosphodiester bonds.
15. The antisense oligonucleotide of claim 13, wherein the oligonucleotide is linked to one or more cholesteryl moieties.
16. The antisense oligonucleotide of claim 3, wherein the oligonucleotide comprises one or more bases with a C-5 propynyl pyrimidine modification.
17. A method of treating cancer, comprising introducing into a tumor cell an effective amount of the antisense oligonucleotide of claim 16, thereby reducing the levels of bcl-2 protein produced and treating cancer.
18. The method of claim 17, wherein the cancer is epithelial cancer.
19. The method of claim 18, wherein the epithelial cancer is prostate cancer.
20. The method of claim 18, wherein the epithelial cancer is lung cancer.
21. The method of claim 18, wherein the epithelial cancer is bladder cancer.
22. The method of claim 17, wherein the introducing comprises using a lipid as a delivery agent.
23. The method of claim 17, wherein the introducing comprises using porphyrin or lipofectin as a delivery agent.
24. The method of claim 17, wherein the effective amount is between 0.1 M and 10 M.
25. The method of claim 17, wherein the effective amount is between 0.1 M and 4 M.
26. The method of claim 17, wherein the effective amount is between 0.4 M and 1 M.
27. A method of treating cancer, comprising introducing into a tumor cell an effective amount of the antisense oligonucleotide of claim 3, thereby reducing the levels of bcl-xL protein produced and treating cancer.
28. The method of claim 27, wherein the cancer is epithelial cancer.
29. The method of claim 28, wherein the epithelial cancer is prostate cancer.
30. The method of claim 28, wherein the epithelial cancer is lung cancer.
31. The method of claim 28, wherein the epithelial cancer is bladder cancer.
32. The method of claim 27, wherein the introducing comprises using a lipid as a delivery agent.
33. The method of claim 27, wherein the introducing comprises using porphyrin or lipofectin as a delivery agent.
34. The method of claim 27, wherein the effective amount is between 0.1 M and 10 M.
35. The method of claim 27, wherein the effective amount is between 0.1 M and 4 M.
36. The method of claim 27, wherein the effective amount is between 0.4 M and 1 M.
37. A method of promoting the regression of vascular lesions, comprising introducing into a vascular cell an amount of the antisense oligonucleotide of claim 3 effective to reduce the levels of bcl-xL protein produced, thereby promoting the regression of vascular lesions.
38. The method of claim 37, wherein the introducing comprises using a lipid as a delivery agent.
39. The method of claim 37, wherein the introducing comprises using porphyrin or lipofectin as a delivery agent.
40. The method of claim 37, wherein the effective amount is between 0.1 M and 4 M.
41. The method of claim 37, wherein the effective amount is between 0.4 M and 1 M.
42. A pharmaceutical composition comprising an effective amount of the antisense oligonucleotide or analog thereof of claim 3 and a pharmaceutically acceptable carrier.
43. The pharmaceutical composition of claim 42, wherein the effective amount is between 0.1 M and 10 M.
44. The pharmaceutical composition of claim 42, wherein the effective amount is between 0.1 M and 4 M.
45. The pharmaceutical composition of claim 42, wherein the effective amount is between 0.4 M and 1 M.
46. The pharmaceutical composition of claim 42, wherein the oligonucleotide is encapsulated in a liposome or nanoparticle.
47. The pharmaceutical composition of claim 42, wherein the pharmaceutical composition comprises tetra meso-(4-methylpyridyl)porphine or tetra meso-(anilinium)porphine or a combination thereof.

1. A method of packaging a semiconductor device, the method comprising:
mounting an electrical component to an inner portion die pad, the die pad being a portion of a substrate strip component of a first leadless three-dimensional stackable semiconductor package;
securing a plurality of bond wires from a plurality of bond pads on the electrical component to corresponding ones of a plurality of wirebond pads included on a leadless outer portion of the substrate strip component;
selecting a sidewall of each of the plurality of wirebond pads, the sidewall having a height to be greater than a combined height of the electrical component and the inner portion die pad; and
covering the electrical component, bond wires, and any exposed uppermost portions of the die pad with an encapsulating material to the uppermost portion of the sidewalls on the leadless outer portion, wherein an outer side surface of the sidewalls form a substantially continuous outermost edge of the semiconductor package.
2. The method of claim 1, further comprising plating any exposed areas of the uppermost portion of the sidewalls with an electrically conductive and non-oxidizing material.
3. The method of claim 2, wherein the electrically conductive and non-oxidizing material is selected to be tin.
4. The method of claim 2, wherein the electrically conductive and non-oxidizing material is selected to be a tin alloy.
5. The method of claim 2 wherein, the electrically conductive and non-oxidizing material is selected to be a nickel-gold alloy.
6. The method of claim 1, further comprising plating any exposed areas of a lowermost portion of the die pad with an electrically conductive and non-oxidizing material.
7. The method of claim 1, further comprising:
mounting one or more additional electrical components over the encapsulating material; and
securing a plurality of bond wires from the one or more additional electrical components to the uppermost portion of the sidewalls.
8. The method of claim 7, wherein the one or more additional electrical components are first mounted to a circuitry substrate prior to being mounted over the encapsulating material.
9. The method of claim 1, further comprising mounting an additional leadless three-dimensional package in electrical contact over the first leadless three-dimensional stackable semiconductor package.
10. The method of claim 1, wherein covering the electrical component, bond wires, and any exposed uppermost portions of the die pad with the encapsulating material includes forming the encapsulating material substantially over both the leadless outer portion and the inner portion die pad and leaving an uppermost portion of the sidewall, a lowermost portion of the sidewall, and an outer side surface of the sidewall exposed, wherein the sidewall is substantially perpendicular to the wirebond pads, and the wirebond pads are integrally formed with the sidewall, the outer side surface of the sidewall being disposed at and forming a substantially continuous outermost edge of the semiconductor package.
11. A method of fabricating a leadless package for a semiconductor device, the method comprising:
selecting a substrate with a given height;
choosing the height of the substrate to be greater than a die pad and an integrated circuit die combined;
patterning and etching the substrate to produce an area of the substrate to have a reduced thickness,
selecting a portion of the reduced thickness area to serve as the die pad;
patterning and etching the die pad to be electrically isolated from an outer portion of the substrate on at least two edge regions;
patterning and etching the at least two outer edge regions of the substrate to serve as a plurality of bonding pads and sidewalls;
electrically isolating each of the plurality of bonding pads and sidewalls from each other to form leadless three-dimensional connection areas; and
forming the sidewalls to be essentially perpendicular to the bonding pads while maintaining the sidewalls at substantially the selected height of the substrate and having an outer side surface of the sidewalls forming a substantially continuous outermost edge of the leadless package.
12. The method of claim 11, further comprising:
mounting the integrated circuit die to the die pad;
securing a plurality of bond wires from a plurality of bond pads on the electrical component to corresponding ones of the plurality of bonding pads; and
covering the integrated circuit die, bond wires, and any exposed portions of the die pad with an encapsulating material to an uppermost portion of the sidewalls on the leadless three-dimensional connection areas.
13. The method of claim 12, wherein covering the integrated circuit die, bond wires, and any exposed portions of the die pad with the encapsulating material includes forming the encapsulating material substantially over both the leadless three-dimensional connection areas and the die pad and leaving an uppermost portion of the sidewalls, a lowermost portion of the sidewalls, and an outer side surface of the sidewalls exposed, wherein the outer side surface is disposed at and forms a substantially continuous outermost edge of the leadless package.
14. The method of claim 11, wherein forming the sidewalls includes forming the sidewalls including an outer side surface disposed at and forming a substantially continuous outermost edge of the leadless package.
15. The method of claim 11, wherein patterning and etching the die pad includes forming the die pad to include a thickness that is less than a height of the sidewalls, the die pad configured to serve as an attachment area for an integrated circuit die, wherein the thickness of the die pad is sized to accommodate an attached integrated circuit die, such that a top surface of the attached integrated circuit die is disposed below a top of the sidewalls.
16. A method comprising:
mounting an electrical component to an inner portion of a substrate strip component of a leadless three-dimensional stackable semiconductor package;
securing a plurality of bond wires from a plurality of bond pads on the electrical component to corresponding wire bonding areas included on a leadless outer portion of the substrate strip component; and
selecting a height of a sidewall of each wire bonding area to be greater than a combined height of the electrical component and the inner portion, wherein each sidewall is integrally formed with and substantially perpendicular to the corresponding flat wire bonding area, an outer side surface of the sidewalls being disposed at and forming a substantially continuous outermost edge of the semiconductor package, the inner portion being located within and electrically isolated from the outer portion, the inner portion having a thickness that is less than a height of the sidewalls of the outer portion and being configured to serve as an attachment area for the electrical component, the thickness of the inner portion configured such that a top surface of an attached electrical component is disposed below a top of the sidewalls.
17. The method of claim 16, comprising covering the electrical component, bond wires, and exposed uppermost portions of the die pad with an encapsulating material to the uppermost portion of the sidewalls on the leadless outer portion.
18. The method of claim 17, wherein covering the electrical component, bond wires, and exposed portions of the die pad with the encapsulating material includes forming the encapsulating material substantially over both the inner portion and the outer portion and leaving an uppermost uppermost portions of the sidewalls, a lowermost portion of the sidewalls, and the outer side surface of the sidewalls exposed.
19. The method of claim 16, comprising plating exposed areas of the uppermost portion of the sidewalls with an electrically conductive and non-oxidizing material.
20. The method of claim 16, comprising plating exposed areas of a lowermost portion of the inner portion with an electrically conductive and non-oxidizing material.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A power management device comprising:
a workload rate detector configured to adjust a length of a duration period;
a power management unit configured to calculate a period workload rate in the duration period; and

a voltage-clock provider configured to adjust a power level, based on the period workload rate andor based on an external command.
2. The power management device of claim 1, wherein the power level is adjusted to a reference power level.
3. The power management device of claim 1, wherein the voltage-clock provider is configured to adjust the power level of a processor.
4. The power management device of claim 1, wherein the workload rate detector is configured to nonlinearly adjust the length of the duration period.
5. The power management device of claim 1, wherein the workload rate detector is configured to detect a plurality of unit workload rates in the duration period, and is configured to adjust the length of the duration period based on a variation of the plurality of unit workload rates.
6. The power management device of claim 5, wherein the length of the duration period is exponentially decreased when a variation of the plurality of unit workload rates is greater than a reference value,
the length of the duration period is exponentially increased when the variation of the plurality of unit workload rates is less than the reference value, and
the length of the duration period is maintained when the variation of the plurality of unit workload rates is equal to the reference value.
7. The power management device of claim 5, wherein the power management unit is configured to calculate the period workload rate of the duration period, based on the plurality of unit workload rates and the length of the duration period.
8. The power management device of claim 7, wherein the duration period includes a plurality of unit periods, and
each of the plurality of unit workload rates is calculated during a corresponding unit period among the plurality of unit periods.
9. The power management device of claim 8, wherein the power management unit is configured to calculate the period workload rate in the duration period by calculating an active period and an idle period during each of the plurality of unit periods, and
the active period is a period during which a main clock signal is applied to a processor, and the idle period is a period during which the main clock signal is not applied to the processor.
10. The power management device of claim 1, wherein the length of the duration period is exponentially adjusted.
11. A power management device comprising:
a workload rate detector configured to nonlinearly adjust a length of a duration period;
a power management unit configured to calculate a period workload rate in the duration period; and
a voltage-clock provider configured to adjust a power level of a processor based on the period workload rate in the duration period.
12. The power management device of claim 11, wherein the workload rate detector is configured to detect a plurality of unit workload rates in the duration period, and is configured to adjust the length of the duration period based on a variation of the plurality of unit workload rates.
13. The power management device of claim 12, wherein the power management unit includes a calculation unit configured to receive the plurality of unit workload rates and to accumulate the plurality of unit workload rates to calculate the period workload rate.
14. The power management device of claim 11, wherein the power management unit includes a comparison unit configured to compare the period workload rate with a reference value.
15. The power management device of claim 11, wherein the power management unit includes a comparison unit configured to compare the period workload rate with a first reference value and to compare the period workload rate with a second reference value,
the voltage-clock provider is configured to increase the power level of the processor when the period workload rate is greater than the first reference value,
the voltage-clock provider is configured to decrease the power level of the processor when the period workload rate is less than the second reference value, and
the voltage-clock provider is configured to maintain the power level of the processor when the period workload rate is between the first reference value and the second reference value.
16. A power management device comprising:
a workload rate detector configured to detect a plurality of unit workload rates in a duration period, and to adjust a length of the duration period based on a variation of the plurality of unit workload rates;
a power management unit configured to calculate a period workload rate of the duration period based on the plurality of unit workload rates and the length of the duration period; and
a voltage-clock provider configured to adjust a power level based on the period workload rate.
17. The power management device of claim 16, wherein the workload rate detector is configured to nonlinearly adjust the length of the duration period.
18. The power management device of claim 16, wherein the power management unit includes:
a comparison unit configured to compare the period workload rate with a reference value and to generate a comparison signal; and
a state machine configured to receive the comparison signal and to provide a level control signal to the voltage-clock provider based on the comparison signal.
19. The power management device of claim 16, wherein the length of the duration period is adjusted between a reference maximum value and a reference minimum value.
20. The power management device of claim 16, wherein the length of the duration period is exponentially adjusted.