All The Claims

1. A polyalkene amine formulation, comprising:
at least one polyalkene amine in a solvent,
wherein the formulation has at least one of the following low temperature properties:
a) a cloud point less than or equal to \u221228\xb0 C. determined according to DIN ISO 3015 or DIN EN 23015;
b) a pour point less than or equal to \u221227\xb0 C. determined according to DIN ISO 3016; andor
c) no crystalline precipitates after storage at a temperature in the region of about \u221235\xb0 C.;
wherein the solvent is selected from mixtures of:
S1) at least one n- or iso-C10-C14 paraffin,
S2) at least one C10-C14 naphthene; and
wherein S1 and S2 are present in mixing ratio of from 10:90 to 90:10.
2. The formulation according to claim 1, wherein the pour point ranges from about \u221227 to \u221255\xb0 C. andor the cloud point ranges from about \u221228 to \u221251\xb0 C.
3. The formulation according to claim 1, wherein the solvent has
a density at 15\xb0 C. according to ASTM D 4052 and EN ISO 12185-1996 in the range from about 650 to 900 kgm3, andor
a viscosity at 20\xb0 C. according to ASTM D 445 in the range from about 1.0 to 5.0 mm2s.
4. The formulation according to claim 1, wherein the polyalkene moiety of the polyalkene amine is a polymerization product of identical or different, straight-chain or branched C2-C6 olefin monomers.
5. The formulation according to claim 4, wherein the polyalkene moiety of the polyalene amine has a number-average molecular weight Mn of from about 200 to 10 000.
6. The formulation according to claim 5, wherein the polyalkene moiety of the polyalene amine is derived from iso-butene or an isobutenic monomer mixture.
7. The formulation according to claim 6, wherein the polyalkene moiety of the polyalene amine is a polyisobutene.
8. The formulation according to claim 1, wherein the polyalkene amine is a polyisobutene amine which is derived from a polyisobutene having at least one of the following properties:
a) a fraction of vinylidene double bonds of at least 70 mol %, based on polyisobutene;
b) a polyisobutene polymer structure comprises at least 85% by weight of isobutene units; and
c) a polydispersity in the range from 1.05 to 7.
9. The formulation according to claim 1, wherein the polyalkene amine is a reaction product of a polyalkene with an amine of the following general formula I:
HNR1R2\u2003\u2003(I)

wherein
R1 and R2 are each independently H, a C1-C18-alkyl, C2-C18-alkenyl, C4-C18-cycloalkyl, C1-C18-alkylaryl, hydroxy-C1-C18-alkyl, poly(oxyalkyl), polyalkylene polyamine or a polyalkylene amine radical; or, together with the nitrogen atom to which they are bonded, are a heterocyclic ring.
10. The formulation according to claim 1, wherein the polyalkene amine is a polyisobutene amine is the reaction product of a hydroformylation and subsequent reductive amination of reactive polyisobutene.
11. The formulation according to claim 1, wherein the solvent is the process solvent of hydroformylation and subsequent reductive amination of reactive polyisobutene.
12. A polyisobutene formulation, comprising:
polyisobutene amine in a mixture comprising
a solvent,
wherein polyisobutene amine is present in a fraction of at least about 63% by weight, based on a total weight of the mixture;

wherein the solvent has
a density at 15\xb0 C. according to ASTM D 4052 and EN ISO 12185-1996 in the range from about 650 to 900 kgm3, andor
a viscosity at 20\xb0 C. according to ASTM D 445 in the range from about 1.0 to 5.0 mm2s;
wherein the solvent is selected from mixtures of:
S1) at least one n- or iso-C10-C14 paraffin,
S2) at least one C10-C14 naphthene; and
wherein S1 and S2 are present in a mixing ratio of from 10:90 to 90:10.
13. A fuel or lubricant composition, comprising:
in a majority of a fuel or lubricant, an amount, effective as an additive, of a formulation according to claim 1.
14. An printing ink, comprising:
as an additive the formulation according to claim 1.
15. A method for improving the intake system-cleaning action of a gasoline fuel, comprising:
adding the formulation according to claim 1 to a gasoline fuel, to obtain a mixture; and
contacting the mixture with said intake system.
16. An additive package, comprising:
a formulation according to claim 1, optionally in combination with at least one further coadditive.
17. A method for improving the low temperature performance of polyisobutene amine, comprising:
adding a mixture of solvent S1 and S2 to polyisobutene amine;
wherein
S1) is at least one n- or iso-C10 -C14 paraffin,
S2) is at least one C10C14 naphthene;
wherein S1 and S2 are present in a mixing ratio of from 10:90 to 90:10.
18. A process for preparing a polyalkene amine formulation according to claim 1, wherein
a) dissolving a polyalkene in a solvent mixture, to obtain a solution;
wherein said polyalkene is a polymerization product of identical or different, straight-chain or branched C2-C6 olefin monomers;
wherein said solvent mixture comprises
S1) at least one n- or iso-C10-C14 paraffin,
S2) at least one C10-C14 naphthene; and
wherein S1 and S2 are present in a mixing ratio of from 10:90 to 90:10;
b) hydroformylating the solution in the presence of CO and H2, to obtain an oxo product; and
c) aminating said oxo product under hydrogenating conditions in the presence of an amine of the following formula I
HNR1R2\u2003\u2003(I)

wherein
R1 and R2 are each independently H, a C1-C18-alkyl, C2-C18-alkenyl, C4-C18-cycloalkyl, C1-C18-alkylaryl, hydroxy-C1-C18-alkyl, poly(oxyalkyl), polyalkylene polyamine or a polyalkylene imine radical; or, together with the nitrogen atom to which they are bonded, are a heterocyclic ring.
19. The process according to claim 18, wherein the solution in stage a) has solvent fraction of at most 40% by weight based on a total weight of the solution.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of removing a low-k dielectric layer from a wafer, the low-k dielectric layer having a k value of less than about 3 and comprising silicon, oxygen and carbon, the method comprising:
(a) fine grinding the low-k dielectric layer with a grinding surface comprising bonded particles of abrasive material having a size of from about 1 to about 6 micrometers; and
(b) polishing the wafer.
2. A method according to claim 1 wherein (a) comprises fine grinding the low-k dielectric layer with a grinding surface comprising bonded particles of abrasive material comprising diamond.
3. A method according to claim 1 wherein (a) comprises fine grinding the low-k dielectric layer with a grinding surface comprising bonded particles of abrasive material comprising cubic boron nitride.
4. A method according to claim 1 wherein (a) comprises fine grinding the low-k dielectric layer to remove a thickness of from about 0.5 to about 4 micrometers.
5. A method according to claim 1 wherein (b) comprises polishing the wafer by chemical mechanical polishing.
6. A method according to claim 5 comprising polishing the wafer by rotating the surface of the wafer against a polishing pad having a hardness of at least about 40 while applying a polishing slurry between the wafer and polishing pad.
7. A method according to claim 5 comprising polishing the wafer with a polishing slurry comprising silica particles in de-ionized water.
8. A method according to claim 5 wherein the wafer comprises silicon material below the low-k dielectric layer, and wherein (b) comprises polishing away a thickness of less than about 8 microns of the silicon material.
9. A method according to claim 1 further comprising immersing a surface of the low-k dielectric layer in an etching solution.
10. A method according to claim 9 wherein the etching solution comprises at least one of:
(i) HF and H2SO4;
(ii) HF and NH4F; and
(iii) H2SO4 and H2O2.
11. A method according to claim 1 further comprising exposing the surface of the low-k dielectric layer to an oxygen-containing gas to oxidize the surface.
12. A method according to claim 1 further comprising:
(c) providing a removable layer on the wafer;
(d) forming the low-k dielectric layer over the removable layer; and
(e) etching the removable layer from the wafer.
13. A method according to claim 1 further comprising the initial steps of (1) processing a wafer comprising a test wafer to form the low-k dielectric layer on the wafer, and (2) determining at least one of a thickness, particle count, or composition of the low-k dielectric layer.
14. A method according to claim 1 wherein the wafer comprises a production wafer having a processed low-k dielectric layer.
15. A method according to claim 1 wherein the low-k dielectric layer further comprises hydrogen.
16. A method according to claim 1 further comprising re-forming the low-k dielectric layer on the wafer.
17. A method of removing a low-k dielectric layer from a wafer, the low-k dielectric layer having a k value of less than about 3 and comprising silicon, oxygen and carbon, the method comprising:
(a) fine grinding the low-k dielectric layer with a grinding surface comprising bonded particles of abrasive material (i) comprising diamond or cubic boron nitride, and (ii) having a size of from about 1 micrometer to about 6 micrometers; and
(b) polishing the wafer by chemical mechanical polishing.
18. A method according to claim 17 wherein (a) comprises fine grinding the low-k dielectric layer to remove a thickness of from about 0.5 micrometers to about 4 micrometers.
19. A method according to claim 17 comprising polishing the wafer by rotating the surface of the wafer against a polishing pad having a hardness of at least about 40 while applying a polishing slurry between the wafer and polishing pad.
20. A method according to claim 19 comprising polishing the wafer using a polishing slurry comprising silica particles in de-ionized water.
21. A method according to claim 17 wherein the wafer comprises silicon material below the low-k dielectric layer, and wherein (b) comprises polishing away a thickness of less than about 8 microns of the silicon material.
22. A method of removing a low-k dielectric layer from a wafer, the low- k dielectric layer having a k value of less than about 3 and comprising silicon, oxygen and carbon, and the method comprising:
(a) fine grinding the low-k dielectric layer with a grinding surface comprising bonded particles of abrasive material (i) comprising diamond or cubic boron nitride, and (ii) having a size of from about 1 micrometer to about 6 micrometers; and
(b) polishing the wafer by rotating the surface of the wafer against a polishing pad having a hardness of at least about 40 while applying a polishing slurry between the wafer and polishing pad.
23. A method according to claim 22 comprising polishing the wafer using a polishing slurry comprising silica particles in de-ionized water.

1. An integrated circuit, comprising:
a first processor;
a plurality of messaging signal registers, wherein the first processor is configured to write a transmit set of messaging signals into the messaging signal registers;
a plurality of GPIO pins;
a GPIO interface configured to receive a first set of signals from the first processor and to transmit a portion of the first set of signals as GPIO signals to a remote processor over the plurality of GPIO pins;
a dedicated transmit pin; and
a finite state machine (FSM) configured to receive a remaining portion of the first set of signals from the GPIO interface and to serially transmit the remaining portion as a transmit set of virtual GPIO signals to the remote processor over the dedicated transmit pin, and wherein the FSM is further configured to retrieve a transmit set of messaging signals from messaging signal register and to serially transmit the transmit set of messaging signals to the remote processor over the dedicated transmit pin.
2. The integrated circuit of claim 1, further comprising:
a dedicated receive pin, wherein the FSM is further configured to serially receive a receive set of virtual GPIO signals from the remote processor over the dedicated receive pin and to provide the receive set of virtual GPIO signals to the GPIO interface.
3. The integrated circuit of claim 2, wherein the GPIO interface is further configured to receive a receive set of GPIO signals from the GPIO pins and to transmit the receive set of GPIO signals to the first processor.
4. The integrated circuit of claim 1, wherein the first processor comprises an application processor.
5. The integrated circuit of claim 1, wherein the first processor comprises a modem processor.
6. The integrated circuit of claim 2, wherein the FSM comprises a parallel-in-serial-out (PISO) shift register and a serial-in-parallel-out (SIPO) shift register.
7. The integrated circuit of claim 2, wherein the FSM is further configured to serially transmit the transmit set of virtual GPIO signals and the transmit set of messaging signals in frames, each frame being demarcated by a start bit and an end bit.
8. The integrated circuit of claim 7, wherein the FSM is further configured to detect a failure of the remote processor by a detection of a failure to receive the end bit for one of the frames.
9. The integrated circuit of claim 3, wherein the FSM if further configured to serially transmit the transmit set of virtual GPIO signals and the transmit set of messaging signals responsive to cycles of an external clock.
10. The integrated circuit of claim 9, wherein the FSM is further configured to serially transmit the transmit sets of signals responsive to first clock edges of the external clock and to serially receive the receive sets responsive to second clock edges of the external clock.
11. The integrated circuit of claim 3, wherein the FSM is further configured to serially transmit the transmit sets of signals as pulse-width-modulated signals.
12. The integrated circuit of claim 11, wherein the FSM includes an oscillator and at least one counter to count oscillations from an oscillator, and wherein the FSM is further configured to determine a pulse width for each pulse-width-modulated signal responsive to a count from the at least one counter.
13. The integrated circuit of claim 12, wherein the oscillator is a ring oscillator.
14. The integrated circuit of claim 11, wherein the FSM is further configured to generate each pulse-width-modulated signal to either have a first pulse width or a second pulse width, wherein the second pulse width is greater than the first pulse width.
15. A method, comprising:
receiving a set of GPIO signals at an GPIO interface from a first processor;
transmitting a portion of the set of GPIO signals through dedicated GPIO pins to a remote processor;

510:
serially transmitting over a dedicated transmit pin a remaining portion of the set of GPIO signals to the remote processor as virtual GPIO signals; and
retrieving messaging signals from messaging signal registers written to by the first processor and serially transmitting the retrieved messaging signals over the dedicated transmit pin to the remote processor.
16. The method of claim 15, further comprising:
serially receiving a receive set of virtual GPIO signals from the remote processor over a dedicated receive pin;
serially receiving a receive set of GPIO signals from the remote processor over the dedicated GPIO pins; and
providing the receive set of virtual GPIO signals and the receive set of GPIO signals to the first processor through the GPIO interface.
17. The method of claim 16, further comprising:
serially receiving a receive set of messaging signals from the remote processor over the dedicated receive pin;
writing the receive set of messaging signals into the messaging signal registers according to addresses for the receive set of messaging signals; and
from the first processor, retrieving the receive set of messaging signals from the messaging signal registers.
18. The method of claim 17, wherein serially transmitting the virtual GPIO signals and the retrieved messaging signals is responsive to cycles of an external clock.
19. The method of claim 17, wherein serially transmitting the virtual GPIO signals and the retrieved messaging signals comprises pulse-width-modulating a transmitted signal over the dedicated transmit pin.
20. An integrated circuit, comprising:
a first processor;
a plurality of messaging signal registers, wherein the first processor is configured to write a transmit set of messaging signals into the messaging signal registers;
a plurality of GPIO pins;
a GPIO interface configured to receive a first set of signals from the processor and to transmit a portion of the first set of signals as GPIO signals to a remote processor over the plurality of GPIO pins;
a dedicated transmit pin; and
a means for receiving a remaining portion of the first set of signals from the GPIO interface and for serially transmitting the remaining portion as a transmit set of virtual GPIO signals to the remote processor over the dedicated transmit pin, and for retrieving a transmit set of messaging signals from messaging signal registers and for serially transmitting the transmit set of messaging signals to the remote processor over the dedicated transmit pin.
21. The integrated circuit of claim 20, wherein the means is configured to serially transmit the transmit sets responsive to cycles of an external clock.
22. The integrated circuit of claim 20, further comprising an oscillator; and wherein the means is configured to serially transmit the transmit sets as pulse-width-modulated signals responsive to counts of oscillations from the oscillator.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A thermally insulating apparatus operatively configured to thermally insulate therein for a period of time, comprising:
an outer shell; and
an internal thermal assembly, positionable within the outer shell, the internal thermal assembly comprising:
a frame sub-assembly cooperating with the outer shell to define a plurality of outer cavities and at least one internal cavity; and
a plurality of insulating members, at least one of the plurality of insulating members being positionable within each of the plurality of outer cavities.