1. A laser device comprising:
a seed laser;
a polarizer optically coupled to receive an output of the seed laser and generate a polarization filtered output;
a pseudorandom bit sequence (PRBS) pattern generator configured to generate a PRBS pattern; and
a phase modulator configured to apply a PRBS modulation scheme to the polarization filtered output based on the PRBS pattern,
wherein the PRBS pattern is generated to have a length above a first threshold for avoiding an occurrence of backward propagation being in phase with forward propagation in an active fiber receiving an output of the phase modulator when the pattern repeats and below a second threshold for phase mismatch in the active fiber.
2. The laser device of claim 1, wherein the polarizer comprises a linear fiber polarizer.
3. The laser device of claim 1, wherein the first threshold is five bits and wherein the second threshold is ten bits.
4. The laser device of claim 1, wherein the PRBS pattern is a PRBS including seven bits.
5. The laser device of claim 1, further comprising a power amplifier configured to amplify an output of the PRBS pattern generator prior to provision of the PRBS pattern to the phase modulator.
6. The laser device of claim 1, further comprising a fiber amplifier configured to amplify an output of the phase modulator to generate a power level of at least about 1 kW.
7. The laser device of claim 6, wherein the second threshold is determined relative to causing phase mismatch in the active fiber of the fiber amplifier.
8. The laser device of claim 1, wherein the seed laser comprises a seed diode having a linewidth of about 30 MHz.
9. The laser device of claim 1, further comprising a laser controller configured to control operation of the laser device.
10. The laser device of claim 8, wherein the laser controller includes processing circuitry configured to control a modulation scheme employed by the laser device.
11. The laser device of claim 8, wherein the laser controller includes processing circuitry configured to control a single frequency seed source employed by the seed laser.
12. A phase modulator for a laser device, the phase modulator comprising:
an input device in operable communication with a polarizer to receive a polarization filtered output of the polarizer responsive to the polarizer polarizing an output of a seed laser; and
a modulator configured to modulate the polarization filtered output of the polarizer based on a pseudorandom bit sequence (PRBS) pattern provided by a PRBS generator in communication with the phase modulator,
wherein the PRBS pattern is generated to have a length above a first threshold for avoiding an occurrence of backward propagation being in phase with forward propagation in an active fiber receiving an output of the phase modulator when the pattern repeats and below a second threshold for phase mismatch in the active fiber.
13. The phase modulator of claim 12, wherein the first threshold is five bits and wherein the second threshold is ten bits.
14. The phase modulator of claim 12, wherein the PRBS pattern is a PRBS including seven bits.
15. The phase modulator of claim 12, wherein the PRBS pattern is provided from the PRBS generator via a power amplifier configured to amplify an output of the PRBS pattern generator prior to provision of the PRBS pattern to the phase modulator.
16. The phase modulator of claim 12, wherein an output of the phase modulator is provided to a fiber amplifier configured to amplify an output of the phase modulator to generate a power level of at least about 1 kW.
17. The phase modulator of claim 12, wherein the phase modulator operates at least partially under control of a laser controller.
18. The phase modulator of claim 17, wherein the laser controller includes processing circuitry configured to control a modulation scheme employed by the laser device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of manufacturing a nonvolatile memory device, comprising:
providing a semiconductor substrate including a cell region;
forming first gate lines and second gate lines over the cell region of the semiconductor substrate, wherein the first gate lines are spaced from each other at a first width, the second gate lines are spaced from each other at a second width, and the first gate lines and the second gate lines are spaced from each other at a third width;
forming first junction regions in the semiconductor substrate between the first gate lines, between the first gate line and an adjacent second gate line, and between the second gate lines by performing a first ion implantation process; and
forming second junction regions in first junction region of the semiconductor substrate between the first gate lines and between a second gate line and an adjacent first gate line by performing a second ion implantation process,
wherein the third width is wider than the second width, and wherein the third width is larger than a height of the first gate lines and the second gate lines.
2. The method of claim 1, wherein the second ion implantation process is a tilt ion implantation process.
3. The method of claim 2, wherein the second ion implantation process is not performed in the first junction regions formed between the second gate lines.
4. The method of claim 1, wherein the first ion implantation process is performed by implanting impurities in a direction vertical to the semiconductor substrate.
5. The method of claim 1, wherein an impurity concentration of the second ion implantation process is lower than an impurity concentration of the first ion implantation process.
6. The method of claim 1, wherein the second ion implantation process comprises:
forming a mask pattern exposing the first junction regions formed between the first gate lines and between the second gate line and the first gate line; and
performing the second ion implantation process to form the second junction regions in the exposed first junction regions using the mask pattern as an ion implantation mask.
7. The method of claim 1, wherein the second ion implantation process comprises:
forming spacers on sidewalls of the first gate lines and on a sidewall of the second gate line formed adjacent to the first gate lines with covering the first junction regions formed between the second gate lines; and
performing the second implantation process to form the second junction regions between the first gate lines and between the second gate line and the first gate line using the spacers as an ion implantation mask.
8. The method of claim 1, wherein the first gate lines comprise select lines and the second gate lines comprise word lines.
9. The method of claim 1, wherein the first width is wider than that of the second width.
10. The method of claim 7, wherein the spacer comprises an oxide layer or nitride layer.
11. A method of manufacturing a nonvolatile memory device, comprising;
providing a semiconductor substrate including a cell region and a peripheral region;
forming select transistors and a plurality of memory cells over the semiconductor substrate of the cell region, and forming low-voltage NMOS transistors or high-voltage NMOS transistors over the semiconductor substrate of the peripheral region, wherein a memory cell and an adjacent select transistor are spaced from each other at a first width, and the low-voltage NMOS transistors or high-voltage NMOS transistors are spaced from each other at a second width, and wherein the first width is smaller than a height of the select transistors and the memory cells;
forming first junction regions in the semiconductor substrate between the select transistors, between the memory cell and the adjacent select transistor, between the plurality of the memory cells, and between the low-voltage NMOS transistors or the high-voltage NMOS transistors;
forming spacers on sidewalls of the select transistors, the memory cells, and the low-voltage NMOS transistors or the high-voltage NMOS transistors, wherein the spacers formed on the sidewalls of the memory cells cover the first junction regions formed between the memory cells; and,
forming second junction regions in the first junction regions of the semiconductor substrate between the low-voltage NMOS transistors or the high-voltage NMOS transistors by performing a tilt ion implantation process using the spacers as an ion implantation mask.
12. The method of claim 11, wherein the first width is narrower than the second width.
13. The method of claim 11, wherein the spacer comprises oxide layer or nitride layer.