All The Claims

1. A frame rail for a vehicle, comprising:
a pair of elongated structural members, each one of said pair of elongated structural members having flanges protruding from lateral edges thereof, said flanges of one of said pair of elongated structural members extending in a direction toward the flanges of the other one of said pair of elongated structural members; and,
first and second web panels interconnecting the pair of elongated structural members so as to form a box beam structure, at least a major portion of each one of the first and second metallic web panels having a material thickness that is substantially less than a material thickness of at least a major portion of each one of the pair of elongated structural members.
2. The frame rail for a vehicle according to claim 1, wherein each one of the first and second web panels is substantially planar.
3. The frame rail for a vehicle according to claim 1, wherein the first web panel is attached to the flanges of the pair of elongated structural members on a first side of the box beam structure via peripheral regions of the first web panel, and wherein the second web panel is attached to the flanges of the pair of elongated structural members on a second side of the box beam structure via peripheral regions of the second web panel, such that the first web panel is spaced apart from and substantially parallel to the second web panel.
4. The frame rail for a vehicle according to claim 1, wherein the first and second web panels are welded to the flanges of the pair of elongated structural members.
5. The frame rail for a vehicle according to claim 1, wherein the first and second web panels are mechanically fastened to the flanges of the pair of elongated structural members.
6. The frame rail for a vehicle according to claim 1, wherein the first and second web panels are secured to the flanges of the pair of elongated structural members using an adhesive.
7. The frame rail for a vehicle according to claim 1, wherein one elongated structural member of said pair of elongated structural members comprises two structural member portions, each structural member portion having one of said flanges protruding from an outer lateral edge thereof and having an inner lateral edge, wherein the inner lateral edges of the two elongated structural member portions are disposed in a side-by-side arrangement and wherein said two structural member portions are butt-welded together along said inner lateral edges thereof.
8. The frame rail for a vehicle according to claim 1, wherein the first web panel is butt-welded along opposite edges thereof to the flanges of the pair of elongated structural members on a first side of the box beam structure, and wherein the second web panel is butt-welded along opposite edges thereof to the flanges of the pair of elongated structural members on a second side of the box beam structure, such that the first web panel is spaced apart from and substantially parallel to the second web panel.
9. The frame rail for a vehicle according to claim 1, wherein the box beam structure is formed along substantially the entire length of the frame rail.
10. The frame rail for a vehicle according to claim 1, wherein the height of the box beam structure is at least double the width of the box beam structure.
11. The frame rail for a vehicle according to claim 1, wherein said elongated structural members are made from one of steel and aluminum.
12. The frame rail for a vehicle according to claim 1, wherein said first and second web panels are made from one of steel and aluminum.
13. A frame rail for a vehicle, comprising:
a first elongated structural member having a first width defined between opposite edges thereof, and having first lateral surfaces along each of said opposite edges, said first lateral surfaces extending along at least a portion of a length of the first elongated structural member;
a second elongated structural member having a second width defined between opposite edges thereof, and having second lateral surfaces along each of said opposite edges, said second lateral surfaces extending along at least a portion of a length of the second elongated structural member; and,
first and second metallic web panels interconnecting the first and second elongated structural members so as to form a box beam structure, each one of the first and second metallic web panels being substantially planar,
wherein a material thickness of at least a major portion of each one of the first and second metallic web panels is substantially less than a material thickness of at least a major portion of each one of the first and second elongated structural members.
14. (canceled)
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21. (canceled)
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28. (canceled)
29. A method of making a frame rail for a vehicle, comprising:
providing a blank, the blank comprising a plurality of joined together sections, some of the plurality of joined together sections having a material thickness extending over at least a major portion thereof that is less than a material thickness extending over at least a major portion of others of the plurality of joined together sections, a first section being disposed along a first lateral edge of the blank and having a same material thickness as a second section that is disposed along a second lateral edge of the blank;
shaping the blank such that an edge of the first section is aligned with and adjacent to an edge of the second section, the edge of the first section and the edge of the second section extending along a length direction; and,
fixedly joining the edge of the first section to the edge of the second section so as to form a frame rail with a closed profile in a cross section taken in a plane that is transverse to the length direction.
30. The method according to claim 29, wherein adjacent sections of the plurality of joined together sections are joined together via a butt weld.
31. The method according to claim 29, wherein fixedly joining comprises butt-welding the edge of the first section to the edge of the second section, and wherein the first section and the second section cooperate, when butt-welded together, to form a first elongated structural member extending along the length direction.
32. The method according to claim 31, wherein shaping comprises bending the blank such that a central section of the plurality of joined together sections forms a second elongated structural member disposed opposite the first elongated structural member, a first intermediate section disposed between the first section and the central section forms a first sidewall, and a second intermediate section disposed between the second section and the central section forms a second sidewall.
33. The method according to claim 32, wherein a material thickness of at least a major portion of each one of the first and second intermediate sections is substantially less than a material thickness of at least a major portion of the first, second and central sections.
34. A blank for use in making a frame rail for a vehicle, the blank comprising:
a first elongated metallic section having a width and a length, the first elongated metallic section having a first material thickness extending over at least a major portion thereof;
a second and a third elongated metallic section each having a length substantially the same as the first elongated metallic section, the second and the third elongated metallic sections each having a material thickness extending over at least a major portion thereof that is substantially the same as the first material thickness; and,
a fourth and a fifth elongated metallic section each having a length substantially the same as the first elongated metallic section, the fourth elongated metallic section being butt-welded along a first edge thereof to the first elongated metallic section and being butt-welded along a second edge thereof that is opposite the first edge to the second elongated metallic section, the fifth elongated metallic section being butt-welded along a first edge thereof to the first elongated metallic section and being butt-welded along a second edge thereof that is opposite the first edge to the third elongated metallic section, a material thickness of at least a major portion of each one of the fourth and fifth elongated metallic sections being substantially less than the first material thickness.
35. The blank according to claim 34, wherein the second elongated metallic section and the third elongated metallic section each has a width and wherein the total width of the second elongated metallic section and third elongated metallic section is substantially the same as the width of the first elongated metallic section.
36. The blank according to claim 34, wherein the fourth elongated metallic section and the fifth elongated metallic section each has a width, and wherein the width of each one of the fourth elongated metallic section and the fifth elongated metallic section is at least two times the width of the first elongated metallic section.
37. (canceled)
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43. The frame rail for a vehicle according to claim 1, wherein said first and second web panels are made from a composite material.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A network apparatus comprising:
storage units, mounted on the board, storing configuration information about the network apparatus;
an input network interfaces mounted on the board, to couple to at least one network physical line;
at least one processor, mounted on the board, receiving network data from said input network interface, processing said data, storing information about said network data in said storage units, storing said data as formatted data units in said storage units;
a first bus interfaces to two bus connections;
a first hardware component reading said configuration information and said information about data stored in said storing units and steering said formatted data units stored in said storage units to at least one of the two bus connections of said first bus interface;
a second bus interface to two bus connections;
an output network interface to at least one network physical line; and
a second hardware component reading formatted data units arriving on at least one of the two bus connections of said second bus interface and storing said formatted date units in said storage units, said at least one processor reading said formatted data units from said storage units, processing them and sending them as network data to at least one network physical line through said output network interface.
2. The network apparatus of claim 1 further comprising:
a bus connecting one of the two bus connections of said first bus interface to one of the two bus connections of said second bus interface, the first hardware component of said network apparatus sending formatted data units to said bus and the second hardware component receiving from said bus said formatted data units.
3. The network apparatus of claim 2,
wherein the second hardware component further comprises an additional storage unit and additional logic for reading said configuration information and said information about data stored in said storing units and steering said read formatted data units either to said storage units or to said additional storage unit; and
wherein, the first hardware component further comprises a bus accessing said additional storage unit, said first hardware component steering said formatted data units stored in said additional storage unit to at least one of the two bus connections of said first bus interface.
4. A switching system comprising:
a network apparatus according to claim 3;
a second network apparatus according to claim 2;
a second bus connecting the second one of the two bus connections of said second bus interface of said first network apparatus to the second one of the two bus connections of said first bus interface of said second network apparatus, said second bus conveying data received at the network interface of said first network processor said data being intended to be sent to the network interface of said second network processor;
a third bus connecting the second one of the two bus connections of said first bus interface of said second network apparatus to the second one of the two bus connections of said second bus interface of said first network apparatus, said third bus conveying data having been sent through said second bus but being intended to be sent through said bus to said additional memory, to the network interface of said first network processor.
5. A blade comprising:
a circuit board;
a network apparatus according to claim 3 mounted on the board;
a second network apparatus according to claim 2 mounted on the board;
a second bus, mounted on the board, connecting the second one of the two bus connections of said second bus interface of said first network apparatus to the second one of the two bus connections of said first bus interface of said second network apparatus, said second bus conveying data received at the network interface of said first network processor said data being intended to be sent to the network interface of said second network processor;
a third bus, mounted on the board, connecting the second one of the two bus connections of said first bus interface of said second network apparatus to the second one of the two bus connections of said second bus interface of said first network apparatus, said third bus conveying data having been sent through said second bus but being intended to be sent through said bus to said additional memory, to the network interface of said first network processor.
6. A switching system comprising:
a switching fabric receiving formatted data units from at least one input bus connection and switching said formatted data units to at least one output bus connection;
a second switching fabric receiving formatted data units from at least one input bus connection and switching said formatted data units to at least one output bus connection;
a first network apparatus according to claim 3;
a second network apparatus according to claim 3;
a first bus connecting one of the two bus connections of said first bus interface of said first network apparatus to one of the at least one input bus connection of said switching fabric, said first bus conveying formatted data units sent by said first network apparatus to said first switching fabric;
a second bus connecting one of the two bus connections of said second bus interface of said first network apparatus to one of the at least one output bus of said switching fabric, said second bus conveying formatted data units sent by said first switching fabric to said first network apparatus;
a third bus connecting one of the two bus connections of said first bus interface of said second network apparatus to one of the at least one input bus connection of said second switching fabric, said third bus conveying formatted data units sent by said second network apparatus to said second switching fabric;
a fourth bus connecting one of the two bus connections of said second bus interface of said first network apparatus to one of the at least one output bus of said switching fabric, said second bus conveying formatted data units sent by said switching fabric to said first network apparatus;
a fifth bus connecting the second one of the two bus connections of said first interface of said first network apparatus to the second one of the two bus connections of the second interface of said second network apparatus; and
a sixth bus connecting the second one of the two bus connections of said first interface of said second network apparatus to the second one of the two bus connections of the second interface of said first network apparatus.
7. The network apparatus of claim 2 wherein the recited elements are formed on a common semiconductor substrate.
8. A switching system comprising:
a switching fabric receiving formatted data units from at least one input bus connection and switching said formatted data units to at least one output bus connection;
a first network apparatus according to claim 7;
a second network apparatus according to claim 1;
a second bus connecting one of the two bus connections of said first bus interface of said first network apparatus to one of the at least one input bus connection of said switching fabric, said second bus conveying formatted data units sent by said network apparatus to said switching fabric;
a third bus connecting one of the two bus connections of said second bus interface of said network apparatus to one of the at least one output bus of said switching fabric, said third bus conveying formatted data units sent by said switching fabric to said network apparatus;
a fourth bus connecting the second one of the two bus connections of said second bus interface of said first network apparatus to the second one of the two bus connections of said first bus interface of said second network apparatus, said fourth bus conveying data received at the network interface of said first network processor said data being intended to be sent to the network interface of said second network processor; and
a fifth bus connecting the second one of the two bus connections of said first bus interface of said second network apparatus to the second one of the two bus connections of said second bus interface of said first network apparatus, said fifth bus conveying data having been sent through said second bus but being intended to be sent through said bus to said additional memory, to the network interface of said first network processor.
9. A switching system comprising:
a switching fabric receiving formatted data units from at least one input bus connection and switching said formatted data units to at least one output bus connection,
at least one network apparatus according to claim 2, each network apparatus further comprising:
a second bus connecting the second one of the two bus connections of said first bus interface of said network apparatus to one of the at least one input bus connection of said switching fabric, said first bus conveying formatted data units sent by said network apparatus to said switching fabric;
a third bus connecting the second one of the two bus connections of said second bus interface of said network apparatus to one of the at least one output bus of said switching fabric, said second bus conveying formatted data units sent by said switching fabric to said network apparatus.
10. The network apparatus of claim 1,
wherein the second hardware component further comprises an additional storage unit and additional logic for reading said configuration information and said information about data stored in said storing units and steering said read formatted data units either to said storage units or to said additional storage unit; and
wherein the first hardware component further comprises a bus accessing said additional storage unit, said first hardware component steering said formatted data units stored in said additional storage unit to at least one of the two bus connections of said first bus interface.
11. The network apparatus of claim 10 wherein the recited elements are formed on a common semiconductor substrate.
12. The network apparatus of claim 1 wherein the recited elements are formed on a common semiconductor substrate.
13. A switching system comprising:
a switching fabric receiving formatted data units from at least one input bus connection and switching said formatted data units to at least one output bus connection;
at least one network apparatus according to claim 1;
said switching system further comprising;
a first bus connecting one of the two bus connections of said first bus interface of said network apparatus to one of the at least one input bus connection of said switching fabric, said first bus conveying formatted data units sent by said network apparatus to said switching fabric;
a second bus connecting one of the two bus connections of said second bus interface of said network apparatus to one of the at least one output bus of said switching fabric, said second bus conveying formatted data units sent by said switching fabric to said network apparatus.
14. The switching system of claim 13 further comprising:
a second switching fabric receiving formatted data units from at least one input bus connection and switching said formatted data units to at least one output bus connection;
said switching system further comprising:
a third bus connecting the second of the two bus connections of said first bus interface of said network apparatus to one of the at least one input bus connection of said second switching fabric, said third bus conveying formatted data units sent by said network apparatus to said second switching fabric;
a fourth bus connecting the second one of the two bus connections of said second bus interface of said network apparatus to one of the at least one output bus of said second switching fabric, said fourth bus conveying formatted data units sent by said second switching fabric to said network apparatus.
15. A blade comprising:
a circuit board;
storage units mounted on the board, storing configuration information about the network apparatus;
an input network interface mounted on the board, to connect to at least one network physical line;
at least one processor mounted on the board, receiving network data from said input network interface, processing said data, storing information about said network data in said storage units, storing said data as formatted data units in said storage units;
a first bus interface mounted on the board, to connect to two bus connections;
a first hardware component mounted on the board, to read said configuration information and said information about data stored in said storing units and steering said formatted data units stored in said storage units to at least one of the two bus connections of said first bus interface;
a second bus interface mounted on the board, to connect to two bus connections;
an output network interface mounted on the board, to connect to at least one network physical line;
a second hardware component mounted on the board, reading formatted data units arriving on at least one of the two bus connections of said second bus interface and storing said formatted data units in said storage units, said at least one processor reading said formatted data units from said storage units, processing them and sending them as network data to at least one network physical line through said output network interface.
16. A blade comprising:
a circuit board;
storage units mounted on the board, storing configuration information about a network apparatus;
an input network interface mounted on the board, to connect to at least one network physical line;
at least one processor mounted on the board, receiving network data from said input network interface, processing said data, storing information about said network data in said storage units, storing said data as formatted data units in said storage units;
a first bus interface mounted on the board, to connect to two bus connections;
a first hardware component mounted on the board, said first hardware component reading said configuration information and said information about data stored in said storing units and steering said formatted data units stored in said storage units to at least one of the two bus connections of said first bus interface;
a second bus interface mounted on the board, to connect to two bus connections, wherein the second hardware component further comprises an additional storage unit, mounted on the board, and an additional logic, mounted on the board, for reading said configuration information and said information about data stored in said storing units and steering said read formatted data units either to said storage units or to said additional storage unit, wherein, the first hardware component further comprises a bus, mounted on the board, accessing said additional storage unit, said first hardware component steering said formatted data units stored in said additional storage unit to at least one of the two bus connections of said first bus interface.
17. A blade comprising:
a circuit board;
storage units, mounted on the board, storing configuration about the network apparatus;
an input network interface, mounted on the board, to couple to at least one network physical line;
at least one processor, mounted on the board, receiving network data from said input network interface, processing said data units in said storage units; storage units, storing said data as formatted data units in said storage units;
a first bus interface, mounted on the board, to couple to two bus connections,
a first hardware component, mounted on the board reading said configuration information and said information about data stored in said storing units and steering said formatted data units stored in said storage units to at least one of the two bus connections of said first bus interface;
a second bus interface, mounted on the board, to couple to two bus connections;
a bus, mounted on the board, connecting one of the two bus connections of said first bus interface to one of the two bus connections of said second bus interface, the first hardware component of said network apparatus sending formatted data units to said bus and the second hardware component receiving from said bus said formatted data units.
18. A blade comprising:
a circuit board;
storage units, mounted on the board, storing configuration about a network apparatus;
an input network interface, mounted on the board, to couple to at least one network physical line;
at least one processor, mounted on the board, receiving network date from said input network interface, processing said data, storing information about said network data in said storage units, storing said data as formatted data units in said storage units;
a first bus interface, mounted on the board, to couple to two bus connections;
a first hardware component, mounted on the board;
reading said configuration information and said information about data stored in said storing units and steering said formatted data units stored in said storage units to at least one of the two bus connections of said first bus interface;
a second bus interface mounted on the board, to connect to two bus connections;
a bus, mounted on the board, connecting one of the two bus connections of said first bus interface to one of the two bus connections of said second bus interface, the first hardware component of said network apparatus sending formatted data units to said bus and the second hardware component receiving from said bus said formatted date units, wherein the second hardware component further comprises an additional storage unit, mounted on the board, and an additional logic, mounted on the board, for reading said configuration information and said information about data stored in said storing units and steering said read formatted data units either to said storage units or to said additional storage unit, wherein, the first hardware component further comprises a bus, mounted on the board, accessing said additional storage unit, said first hardware component steering said formatted data units stored in said additional storage unit to at least one of the two bus connections of said first bus interface.

1. An on-die termination (ODT) circuit, comprising:
a first termination circuit including a first switch and configured to switchably connect a first termination impedance between an inputoutput data node and a first power supply voltage;
a second termination circuit including a second switch and configured to switchably connect a second termination impedance between the inputoutput data node and the first power supply voltage; and
a switch-control circuit configured to perform a logic operation on an output enable signal (DOEN) and an asynchronous control signal (ACS) to output a first switch-control signal and a second switch-control signal to selectively activate the first termination circuit and the second termination circuit, respectively, to selectively connect the first termination impedance, the second termination impedance, or both the first termination impedance and the second termination impedance between the inputoutput data node and the first power supply voltage;
wherein the first switch-control signal is not configured to control a switch to switchably connect a termination impedance between the inputoutput data node and a second power supply voltage during a memory READ mode nor during a memory WRITE mode;
wherein the second switch-control signal is not configured to control a switch to switchably connect a termination impedance between the inputoutput data node and the second power supply voltage during the memory READ mode nor during the memory WRITE mode.
2. An on-die termination (ODT) circuit, comprising:
a first termination circuit including a second switch and configured to switchably connect a first termination impedance between an inputoutput data node and a first power supply voltage;
a second termination circuit including a second switch and configured to switchably connect a second termination impedance between the inputoutput data node and the first power supply voltage; and
a switch-control circuit configured to perform a logic operation on an output enable signal (DOEN) and an asynchronous control signal (ACS) to output a first switch-control signal and a second switch-control signal to selectively activate the first termination circuit and the second termination circuit, respectively, to selectively connect the first termination impedance, the second termination impedance, or both the first termination impedance and the second termination impedance between the inputoutput data node and the first power supply voltage,
wherein the inputoutput data node receives data read out or written into a memory device, wherein
a first total impedance value is connected between the inputoutput data node and the first power supply voltage during a memory READ mode and based on a first set of predetermined logic levels of DOEN and ACS;
a second total impedance value, different from the first total impedance value, is connected between the inputoutput data node and the first power supply voltage during a memory WRITE mode and based on a second set of predetermined logic levels of DOEN and ACS;
a third total impedance value, different from the first and second total impedance values is connected between the inputoutput data node and the first power supply voltage during a memory normal mode and based on a third set of predetermined logic levels of DOEN and ACS.
3. The ODT circuit of claim 2, wherein: neither of the first termination circuit and the second termination circuit is activated during the memory READ mode;
and the first termination circuit is activated during the memory WRITE mode; and wherein both the first termination circuit and the second termination circuit are activated during the normal mode.
4. The ODT circuit of claim 2, wherein the second total impedance value is about 120 ohms for the memory WRITE mode, the third total impedance value is about 60 ohms during the NORMAL mode, and the first total impedance value is about zero during the memory READ mode.
5. The ODT circuit of claim 2, wherein the ACS signal is received at an external pin of the memory device and the inputoutput data node is connected to another external pin of the memory device.
6. The ODT circuit of claim 2, wherein the ACS signal is asynchronous with respect to a clock signal of the memory device.
7. The ODT circuit of claim 2, wherein the ACS signal is generated based on a memory WRITE command.
8. The ODT circuit of claim 7, further including a pulse generator configured to generate the ACS signal with a pulse width larger than the write data window.
9. The ODT circuit of claim 7, further including a command decoder configured to receive memory READ and WRITE commands from an external memory controller.
10. The ODT circuit of claim 2, wherein the DOEN signal is used to enable an output buffer of the memory device.
11. The ODT circuit of claim 2, wherein the first termination circuit comprises the first switch that responds to the first switch-control signal and at least one resistor.
12. The ODT circuit of claim 2, wherein the switch-control circuit comprises one of logic gates or at least one multiplexer.
13. The ODT circuit of claim 2, further comprising:
a third termination circuit configured to switchably connect a third termination impedance between the inputoutput data node the first power supply voltage; and
a third switch-control signal generated by the switch-control circuit to selectively activate the third termination circuit.
14. The ODT circuit of claim 13, wherein the second total impedance value is about 120 ohms, and wherein the third total impedance value is about 60 ohms, and wherein the first total impedance value is about 40 ohms.
15. A method of providing termination impedance at an inputoutput data line of a memory device, comprising:
performing a logic operation on an output enable (DOEN) signal and an asynchronous control signal (ACS) to output a first switch-control signal configured to selectively activate a first termination circuit having a first termination impedance and to output a second switch-control signal configured to selectively activate a second termination circuit having a second termination impedance,
wherein the first termination circuit is configured to switchably connect the first termination impedance between the inputoutput data line and a first power supply voltage,
wherein the second termination circuit is configured to switchably connect the second termination impedance between the inputoutput data line and the first power supply voltage,
wherein the ACS is asynchronous with respect to a clock signal of the memory device and is generated based on the presence of a memory WRITE command,
wherein the first switch-control signal activates the first termination circuit only if the memory WRITE command is present, and
wherein the DOEN signal is generated based on the presence of a memory READ command.
16. The method of claim 15, wherein a first total impedance value and a second total impedance value corresponding to a memory READ mode and a memory WRITE mode respectively, are alternately connected between the inputoutput data line and the first power supply voltage based on predetermined logic levels of DOEN and ACS.
17. The method of claim 16, wherein the DOEN signal is generated using an internal clock signal generated from an external clock signal, and the internal clock signal is turned off during memory WRITE and NORMAL modes.
18. The method of claim 15, wherein a first total impedance value is about 120 ohms for a memory WRITE operation, and wherein both the first termination circuit and the second termination circuit are activated during a NORMAL operation so that third total impedance values is about 60 ohms for the NORMAL operation, and wherein no termination circuit is activated for a memory READ operation.
19. The method of claim 15, wherein the ACS is generated by a memory controller and received at an external pin of the memory device and the inputoutput data line is connected to another external pin of the memory device.
20. The method of claim 15, further comprising decoding at the memory device commands issued from an external memory controller and generating the ACS based on a decode of the memory WRITE command.
21. The method of claim 19, wherein generating the ACS includes generating a pulse width larger than the write data window.
22. The method of claim 15, further comprising generating a third switch-control signal configured to selectively activate a third termination circuit to switchably connect a third impedance between the inputoutput data line and the first power supply voltage based on predetermined logic levels of DOEN and ACS.
23. The method of claim 22, wherein a total impedance value of about 120 ohms is connected between the inputoutput data line and the first power supply voltage for a memory WRITE; and a total impedance value of about 60 ohms is connected between the inputoutput data line and the first power supply voltage for a NORMAL operation; and a total impedance value of about 40 ohms of driver impedance is connected between the inputoutput data line and the first power supply voltage for a memory READ.
24. The ODT circuit of claim 3, wherein a logic level H at the DOEN indicates the memory READ mode and wherein a logic level L at the DOEN and a logic level H at the ACS indicates the memory WRITE mode, and wherein the presence of a logic level L at the DOEN and a logic level L at the ACS indicates the NORMAL mode.
25. The ODT circuit of claim 1, wherein the on-die termination (ODT) circuit does not include a switch configured to switchably connect a termination impedance between the inputoutput data node and the second power supply voltage in response to the first switch-control signal.
26. The ODT circuit of claim 25, wherein the on-die termination (ODT) circuit does not include a switch configured to switchably connect a termination impedance between the inputoutput data node and the second power supply voltage.
27. The ODT circuit of claim 25, further comprising: a third termination circuit including a third switch and configured to switchably connect a third termination impedance between the inputoutput data node and the first power supply voltage.
28. The ODT circuit of claim 27, further comprising: a fourth termination circuit including a fourth switch and configured to switchably connect a fourth termination impedance between the inputoutput data node and the second power supply voltage while neither of the first second termination impedance nor the second termination impedance is connected between the inputoutput data node and the first power supply voltage.
29. The method of claim 15, wherein the second switch-control signal activates the second termination circuit only if the memory READ command is NOT present.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A controller device for performing communication control of a mobile terminal belonging to an ad hoc network, comprising:
a communication environment information obtaining unit configured to obtain communication environment information, which shows a communication environment in the mobile terminal belonging to the ad hoc network, from the mobile terminal; and
a proxy control information transmitter unit configured to transmit proxy control information for performing the communication control instead of the controller device, to a predetermined mobile terminal belonging to the ad hoc network, when the obtained communication environment information satisfies a predetermined condition.
2. The controller device according to claim 1, comprising a communication control result receiver unit configured to receive a result of the communication control performed by the predetermined mobile terminal instead of the controller device, when a connection between the mobile terminal belonging to the ad hoc network and the controller device is recovered.
3. The controller device according to claim 1, wherein the communication environment information in the mobile terminal is a state of a radio wave in the mobile terminal.
4. The controller device according to claim 1, wherein the communication control of the mobile terminal is routing control performed through the ad hoc network.
5. A mobile terminal belonging to an ad hoc network, comprising:
a communication environment information transmitter unit configured to transmit to a predetermined controller device communication environment information which shows a communication environment in the mobile terminal;
a proxy control information receiver unit configured to receive proxy control information transmitted by the predetermined controller device, when the communication environment information satisfies predetermined conditions; and
a proxy controller unit configured to perform communication control of a mobile terminal belonging to the ad hoc network instead of the predetermined controller device based on the received proxy control information, when a connection between the mobile terminal and the predetermined controller device is cut at the latest.
6. The mobile terminal according to claim 5, comprising a communication control result transmitter unit configured to transmit to the predetermined controller device a result of the communication control performed instead of the predetermined controller device, when the connection between the mobile terminal and the controller device is recovered.
7. A mobile communication method for performing communication control of a mobile terminal belonging to an ad hoc network, comprising:
obtaining, at a controller device, communication environment information which shows a communication environment in the mobile terminal belonging to the ad hoc network from the mobile terminal;
transmitting, at the controller device, proxy control information for performing the communication control instead of the controller device to a predetermined mobile terminal belonging to the ad hoc network, when the obtained communication environment information satisfies predetermined conditions; and
performing, at the predetermined mobile terminal, the communication control of the mobile terminal belonging to the ad hoc network instead of the predetermined controller device based on the received proxy control information, when a connection between the mobile terminal belonging to the ad hoc network and the predetermined controller device is cut at the latest.