All The Claims

1. A thin, film-form seating detection switch capable of detecting whether or not a passenger is seated in a seat, comprising:
a film-form substrate made of insulating material;
a first conductor fixed to one of the surfaces of the substrate, including a first terminal at one end and a first electrode at the other end;
a second conductor fixed to said one of the surfaces of the substrate, including a second terminal at one end and a second electrode at the other end, said second conductor being insulated from the first conductor;
a film form member made of insulating material, disposed on said one of the surfaces of the substrate, and slightly removed from the substrate via a spacer and substantially parallel to the substrate; and
a third conductor fixed to the surface of the member facing the substrate, including a fourth electrode at one end and a third electrode at the other end;
wherein when a passenger sits down in a seat on which the seating detection switch is provided, at least one of a part of the substrate and a part of the member bends due to the weight of the passenger, and the first and fourth electrodes as well as the second and third electrodes enter a condition of mutual conductivity.
2. The seating detection switch according to claim 1, wherein the first terminal and the second terminal are disposed in mutual proximity and the film-form substrate is formed in continuity between said terminals.
3. The seating detection switch according to claim 1 or claim 2, wherein a part of seating detection switch that curves substantially when a passenger sits down in the seat is reinforced.
4. The seating detection switch according to claim 3, wherein the part that curves substantially is reinforced by removing the spacer and the film-form member from the part that curves substantially and providing an insulating, thin resistance layer on the surface of the film-form substrate on which the first and second conductors are disposed so as to cover the first conductor and the second conductor.
5. The seating detection switch according to claim 4, wherein the resistance layer enters in slightly between the spacer and the film-form substrate.
6. The seating detection switch according to claim 4 or claim 5, wherein the surface of the resistance layer is covered with a flexible, thin, film-form protective tape.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An arrayed processor comprising:
a plurality of processing elements arranged in a matrix, each of said processing elements having: an instruction memory configured to store instruction codes, an instruction decoder, an mb (m-bit) arithmetic logic unit and an nb (n-bit) arithmetic logic unit, where \u201cm\u201d represents a natural number equal to or greater than 2 and \u201cn\u201d represents a natural number smaller than \u201cm\u201d;
a plurality of switch elements interconnecting said plurality of processing elements;
a state transition controller configured to generate instruction pointers for said processing elements in response to object codes supplied to the state transition controller from an external circuit and to supply the generated instruction pointers to said respective processing elements, said generated instruction pointers designating instruction codes stored in each said instruction memory of said plurality of processing elements; and
a data distributor configured to divide a series of processing data received from an external circuit into mb data and nb data, said mb data and nb data being input selectively to certain ones of said plurality of processing elements through mb and nb buses having connections controlled by said plurality of switch elements;
wherein said instruction decoder of each said plurality of processing elements is configured to decode instruction codes designated by said instruction pointers in order to control the processing operation of said mb and nb arithmetic logic; and
wherein said mb arithmetic logic unit processes in parallel mb data from said series of processing data, and said nb arithmetic logic unit processes nb data from said series of processing data according to said object codes.
2. The arrayed processor according to claim 1, wherein said processing elements are arranged in a matrix and have a bus connector, an input control circuit, and an output control circuit,
wherein said bus connector are configured to control connections between said mb buses connected thereto and connections between said nb buses connected thereto, and
said input control circuit are configured to control at least connections of input data from said mb buses to said mb arithmetic logic units and connections of input data from said nb buses to said nb arithmetic logic units, and
said output control circuits is configured to control at least connections of output data from said mb arithmetic logic units to said mb buses and connections of output data from said nb arithmetic logic unit to said nb buses.
3. The arrayed processor according to claim 1, wherein each of said processing elements has an mb register file unit for temporarily holding said mb data input thereto and outputting said mb data, and an nb register file unit for temporarily holding said nb data input thereto and outputting said nb data.
4. The arrayed processor according to claim 1, wherein each of said processing elements has a single register file unit for temporarily holding said mb data input thereto, outputting the mb data as at least one of said mb data and said nb data, temporarily holding said nb data input thereto, and outputting the nb data as at least one of said mb data and said nb data.
5. The arrayed processor according to claim 1, wherein each of said processing elements has internal interconnection resources for each of said processing elements to control connections between said mb arithmetic logic unit, said nb arithmetic logic unit, and a register file unit.
6. The arrayed processor according to claim 1, wherein each of said processing elements includes a data manipulation unit for manipulating at least said mb data and said nb data.
7. The arrayed processor according to claim 6, wherein said nb arithmetic logic unit of each of said processing elements comprises a part of said data manipulation unit.
8. The arrayed processor according to claim 6, wherein said data manipulation unit includes a shifting circuit for shifting at least said mb data.
9. The arrayed processor according to claim 6, wherein said data manipulation unit includes a numerical value holding circuit for temporarily holding numerical data for use in processing said mb data.
10. The arrayed processor according to claim 6, wherein said data manipulation unit includes a masking circuit for masking at least said mb data.
11. The arrayed processor according to claim 9, wherein said data manipulation unit includes a masking circuit for masking at least said mb data using the numerical data temporarily held by said numerical value holding circuit.
12. The arrayed processor according to claim 6, wherein said data manipulation unit includes an OR gate for performing OR operations on at least said mb data.
13. The arrayed processor according to claim 1, wherein \u201cnb\u201d represents 1 bit.
14. The arrayed processor according to claim 13, wherein \u201cmb\u201d represents 8 bits.
15. A data processing system comprising:
an arrayed processor according to claim 1;
a data processing apparatus for generating said object codes from source codes;
code supply means for supplying said source codes to said data processing apparatus; and
code transfer means for inputting said object codes output from said data processing apparatus to said arrayed processor.
16. A data processing system according to claim 15 further comprising code storage means for registering a plurality of types of said object codes.

1. A method of manufacturing a liquid crystal display, comprising the steps of:
forming a first conductive layer on a substrate;
patterning the first conductive layer to form a gate line with a gate line, a gate electrode and a gate pad;
forming a gate insulating layer, a semiconductor layer, a doped semiconductor layer and a second conductive layer on the gate line;
forming a photoresist pattern with various thicknesses on the second conductive layer;
providing stepwise etch said second conductive layer, said doped semiconductor layer, said semiconductor layer and said gate insulating layer so as to form a data line with source electrode and a drain electrode;
forming an organic protection layer;
patterning said organic protection layer to form a plurality of through holes; and
forming a third conductive layer in said through holes electrically connected to said second conductive layer.
2. The method of manufacturing a liquid crystal display of claim 1, wherein the photoresist pattern with various thicknesses is formed by a half tone mask.
3. The method of manufacturing a liquid crystal display of claim 1, wherein the photoresist pattern with various thicknesses is formed by a mask with a slit pattern.
4. The method of manufacturing a liquid crystal display of claim 1, wherein the organic protection layer is made from benzocyclobutene (BCB), perfluorocyclobutane (PFCB), fluorinated para-xylene, acrylic resin, or color resin.
5. The method of manufacturing a liquid crystal display of claim 1, wherein the photoresist layer is unexposed in a certain thickness over the gate pad and gate electrode.
6. The method of manufacturing a liquid crystal display of claim 1, wherein all areas are etched to the substrate to stop except the areas of the gate line and data line.
7. The method of manufacturing a liquid crystal display of claim 1, further comprising a step of forming an inorganic protection layer on the semiconductor layer over the gate electrode.
8. The method of manufacturing a liquid crystal display of claim 7, wherein the inorganic protection layer is formed by treating the semiconductor layer with a mixture of plasma and nitrogen, hot oxygen or hot nitrogen.
9. The method of manufacturing a liquid crystal display of claim 1, further comprising a step of removing the gate insulating layer and semiconductor layer disposed on the gate pads so as to expose the gate pads.
10. A method of manufacturing a liquid crystal display, comprising the steps of:
forming a first conductive layer on a substrate;
patterning the first conductive layer to form a gate line with a gate line, a gate electrode and a gate pad;
forming a gate insulating layer and a semiconductor layer on the gate line;
forming an etching stop layer on the semiconductor layer and over the gate electrode; forming a doped semiconductor layer and a second conductive layer on the etching stop layer and semiconductor layer;
patterning the second conductive layer, doped semiconductor layer, semiconductor layer and gate insulating layer to form a data line with a source electrode and a drain electrode;
forming an organic protection layer;
patterning the organic protection layer so as to form a plurality of through holes;
forming a third conductive layer in the through holes electrically connected to the second conductive layer.
11. The method of manufacturing a liquid crystal display of claim 10, wherein the thickness of the etching stop layer is greater than the total thickness of the semiconductor layer and gate insulating layer.
12. The method of manufacturing a liquid crystal display of claim 10, further comprising a step of removing the gate insulating layer over the gate pad by a mask after the second conductive layer is patterned.
13. The method of manufacturing a liquid crystal display of claim 10, wherein the organic protection layer is made from benzocyclobutene (BCB), perfluorocyclobutane (PFCB), fluorinated para-xylene, acrylic resin, or color resin.
14. The method of manufacturing a liquid crystal display of claim 10, wherein all areas are etched to the substrate to stop except the areas of the gate line and data line.
15. A method of manufacturing a liquid crystal display, comprising the steps of:
forming a first conductive layer on a substrate; patterning the first conductive layer to form a gate line with a gate line, a gate electrode and a gate pad;
forming a gate insulating layer on the gate line and patterning the gate insulating layer for the gate pad to be exposed;
forming a semiconductor layer, an etching stop layer, a doped semiconductor layer and a second conductive layer on the gate insulating layer and gate line;
patterning the second conductive layer, doped semiconductor layer and semiconductor layer to form a data line, a source electrode and a drain electrode;
forming an organic protection layer;
patterning the organic protection layer to form a plurality of through holes; and
forming a third conductive layer in the through holes electrically connected to the second conductive layer.
16. The method of manufacturing a liquid crystal display of claim 15, further comprising a step of removing the gate insulating layer except that over the gate line and data line after the gate insulating layer is formed.
17. The method of manufacturing a liquid crystal display of claim 15, wherein the gate line and gate electrode is covered with the gate insulating layer after the gate insulating layer is patterned.
18. The method of manufacturing a liquid crystal display of claim 15, wherein the organic protection layer is made from benzocyclobutene (BCB), perfluorocyclobutane (PFCB), fluorinated para-xylene, acrylic resin, or color resin.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A bubble cap adapted for co-current transport of a mixture of a liquid fluid and a gaseous fluid, comprising:
(a) a riser having a top; (b) a cap having a bottom and at least one side slot, the side slot having an upper end, wherein the cap is coupled to the riser to thereby form a space between the riser and the cap; and (c) a divider coupled to at least one of the riser and the cap and disposed in the space, wherein the divider extends to a length of at least 70% of a distance measured between the top of the riser and the bottom of the cap;
wherein the divider extends across the upper end of the slot such that an upper end of the divider is located above the upper end of the slot and such that a lower end of the divider is located below the upper end of the slot;
wherein the slot is configured to have a length such that the upper end of the slot is above a liquid fluid disposed on a distribution plate;
wherein the bubble cap is coupled to the distribution plate to thereby form a passage for downward flow of a mixture of the liquid fluid and a gaseous fluid through the distribution plate; and
wherein the distribution plate is disposed within a reactor that is configured such that the liquid fluid and the gaseous fluid move in a downward motion within the reactor.
2. The bubble cap of claim 1 wherein the length of the divider is at least 80% of the distance between the top of the riser and the bottom of the cap.
3. The bubble cap of claim 1 wherein the length of the divider is at least 90% of the distance between the top of the riser and the bottom of the cap.
4. The bubble cap of claim 1 wherein the length of the divider is 100% of the distance between the top of the riser and the bottom of the cap.
5. The bubble cap of claim 1 wherein the divider is attached to the riser.
6. The bubble cap of claim 1 wherein the divider is attached to the cap.
7. The bubble cap of claim 1 wherein the divider is attached to both the riser and the cap.
8. The bubble cap of claim 1 wherein the bubble cap has at least two dividers.
9. The bubble cap of claim 1 wherein the bubble cap has at least three dividers.
10. The bubble cap of claim 1 wherein the bubble cap has at least six dividers.
11. The bubble cap of claim 1, further comprising a swirl director attached to the riser.
12. A mixing device having a plurality of bubble caps according to claim 1.
13. A mixing device having a bubble cap of claim 1 wherein the bubble cap, having at least one slot, is positioned with respect to a distribution plate and the bottom of the cap is positioned at least 1.5 inches from the distribution plate.
14. A bubble cap, comprising:
a cap with at least one slot that has an upper end, and a riser configured to provide the cap with a skirt height of no less than 1.5 inches, wherein the bubble cap is configured to be coupled to a distribution plate in a vessel such that a liquid fluid and a gaseous fluid flow co-currently upwardly in a space between the riser and the cap;
a divider disposed in a space between the cap and the riser and extending to a length at least 70% of a distance measured between the tap of the riser and the bottom of the cap;
wherein the divider extends across the upper end of the slot such that an upper end of the divider is located above the upper end of the slot and such that a lower end of the divider is located below the upper end of the slot; and
wherein the slot is configured to have a length such that the upper end of the slot is above a liquid fluid surrounding the bubble cap.
15. The bubble cap of claim 14, wherein the skirt height is no less than 2.5 inches.
16. The bubble cap of claim 14, wherein the skirt height is no less than 4 inches.
17. The bubble cap of claim 14, wherein the cap has a side that includes at least three slots.
18. The bubble cap of claim 14, wherein the slot has a length of at least 2.5 inches.
19. The bubble cap of claim 14, wherein the slot has a length of at least 3.5 inches.
20. The bubble cap of claim 14, wherein the slot has a length of at least 5 inches.