All The Claims

What is claimed is:

1. A predistortion circuit comprising:
a divider for branching an input signal into plural branched signals;
a delay circuit for delaying one of the branched signals by a predetermined delay time;
a distortion generating circuit for receiving the other branched signal and for generating a distortion signal;
a vector adjustment circuit for varying an amplitude and a phase of the distortion signal; and
a combining circuit for combining an output signal of the delay circuit and an output signal of the vector adjustment circuit and for outputting a combined signal to circuit means as a subject of linearization to be provided downstream of and connected directly or indirectly to the combining circuit,
wherein the delay time of the delay circuit is set based on a phase difference of a distortion that would be generated by the circuit means if the vector adjustment circuit did not produce the output signal.
2. A predistortion circuit comprising:
a divider for branching an input signal into plural branched signals;
a delay circuit for delaying one of the branched signals by a predetermined delay time;
a distortion generating circuit for receiving the other branched signal and for generating a distortion signal;
an amplitude frequency characteristic adjustment circuit for varying an amplitude frequency characteristic of the distortion signal;
a vector adjustment circuit for varying an amplitude and a phase of the distortion signal that is output from the amplitude frequency characteristic adjustment circuit; and
a combining circuit for combining an output signal of the delay circuit and an output signal of the vector adjustment circuit.
3. The predistortion circuit according to claim 2, wherein the delay time of the delay circuit is set based on a phase difference of a distortion that would be generated by circuit means as a subject of linearization to receive an output signal of the combining circuit if the vector adjustment circuit did not produce the output signal.
4. The predistortion circuit according to claim 1 or 3, wherein the delay time of the delay circuit is set based on the phase difference in such a manner that a first delay time is so set that a difference between the first delay time and a second delay time substantially equivalent to or corresponding to the phase difference, where the first delay time is the delay time itself and the second delay time is a delay time of a signal that is input to the combining circuit via the distortion generation circuit and the vector adjustment circuit.
5. The predistortion circuit according to claim 1 or 3, wherein the delay time of the delay circuit is variable.
6. The predistortion circuit according to claim 1 or 3, wherein the delay time of the delay circuit is fixed at a predetermined value.
7. A predistortion circuit comprising:
a divider for branching an input signal into plural branched signals;
a delay circuit for receiving one of the branched signals;
a distortion generating circuit for receiving the other branched signal and for generating a distortion signal;
at least two filter circuits for separating the distortion signal into distortion signals having different frequencies;
at least two vector adjustment circuits connected to outputs of the respective filter circuits directly or indirectly, for varying amplitudes and phases of the distortion signals that are output from the respective filter circuits; and
a combining circuit for combining an output signal of the delay circuit and combined output signals of the respective vector adjustment circuits.
8. The predistortion circuit according to claim 7, further comprising at least two amplitude frequency characteristic adjustment circuits for varying amplitude frequency characteristics of distortion signals that are output from the respective filter circuits, wherein the vector adjustment circuits are connected to outputs of the respective amplitude frequency characteristic adjustment circuits.
9. The predistortion circuit according to any one of claims 1, 2, 3, 7, and 8, wherein the distortion generation circuit comprises a limiter amplifier.
10. The predistortion circuit according to any one of claims 1, 2, 3, 7, and 8, wherein the distortion generation circuit comprises a diode.
11. The predistortion circuit according to any one of claims 1, 2, 3, 7, and 8, wherein the distortion generation circuit comprises a zero-bias diode.
12. The predistortion circuit according to any one of claims 1, 2, 3, 7, and 8, wherein the distortion generation circuit comprises:
a divider for branching an input signal into plural signals;
a delay circuit connected to one output side of the divider;
a circuit connected to the other output side of the divider and comprising a nonlinear device;
a vector adjustment circuit connected to an output side of the circuit comprising the nonlinear device; and
a combining circuit for combining an output signal of the delay circuit and an output signal of the vector adjustment circuit.
13. A low-distortion power amplifier comprising:
a combining circuit for combining an input signal with another signal;
a power amplifier for receiving an output signal of the combining circuit;
a divider for branching an output signal of the power amplifier into plural branched signals;
a distortion extraction circuit for extracting a distortion signal from one of the branched signals;
an amplitude frequency characteristic adjustment circuit for varying an amplitude frequency characteristic of the distortion signal; and
a vector adjustment circuit for varying an amplitude and a phase of the distortion signal that is output from the amplitude frequency characteristic adjustment circuit,
wherein an output signal of the vector adjustment circuit is input to the combining circuit as said another signal and the other branched signal is output from the low-distortion power amplifier.
14. A low-distortion power amplifier comprising:
a combining circuit for combining an input signal with another signal;
a power amplifier for receiving an output signal of the combining circuit;
a divider for branching an output signal of the power amplifier into plural branched signals;
a distortion extraction circuit for extracting a distortion signal from one of the branched signals;
at least two filter circuits for separating the distortion signal into distortion signals having different frequencies; and
at least two vector adjustment circuits for varying amplitudes and phases of the distortion signals that are output from the respective filter circuits,
wherein a signal obtained by combining together output signals of the vector adjustment circuits is input to the combining circuit as said another signal and the other branched signal is output from the low-distortion power amplifier.
15. A low-distortion power amplifier comprising:
a combining circuit for combining an input signal with another signal;
a power amplifier for receiving an output signal of the combining circuit;
a divider for branching an output signal of the power amplifier into plural branched signals;
a distortion extraction circuit for extracting a distortion signal from one of the branched signals;
at least two filter circuits for separating the distortion signal into distortion signals having different frequencies;
at least two amplitude frequency characteristic adjustment circuits for adjusting amplitude frequency characteristics of the distortion signals that are output from the respective filter circuits; and
at least two vector adjustment circuits for varying amplitudes and phases of distortion signals that are output from the respective filter circuits,
wherein a signal obtained by combining together output signals of the vector adjustment circuits is input to the combining circuit as said another signal and the other branched signal is output from the low-distortion power amplifier.
16. A control method for the predistortion circuit according to any one of claims 1, 2, 3, 7, and 8, comprising the steps of:
connecting a power amplifier to an output side of the predistortion circuit;
detecting a magnitude of a distortion signal generated by the power amplifier; and
controlling at least one of the amplitude frequency characteristic adjustment circuit or circuits, the vector adjustment circuit or circuits, and the delay time of the delay circuit so as to minimize the detected magnitude of the distortion signal.
17. The control method for the low-distortion power amplifier according to any one of claims 13 to 15, comprising the steps of:
detecting a magnitude of the distortion signal that is output from the distortion extraction circuit; and
controlling at least one of the amplitude frequency characteristic adjustment circuit or circuits and the vector adjustment circuit or circuits so as to minimize the detected magnitude of the distortion signal.
18. A linearized power amplifier comprising:
the predistortion circuit according to any one of claims 1, 2, 3, 7, and 8;
a power amplifier for receiving an output signal of the predistortion circuit;
a divider for branching an output signal of the power amplifier into plural branched signal;
detecting means of receiving one of the branched signals and detecting an amplitude and a phase of a distortion signal that is output from the power amplifier; and
control means of controlling at least one of the amplitude frequency characteristic adjustment circuit or circuits, the vector adjustment circuit or circuits, and the delay circuit of the predistortion circuit so as to minimize a distortion generated by the power amplifier based on an output signal of the distortion amplitude and phase detecting means,
wherein the other branched signal becomes at least one output signal of the linearized power amplifier.
19. A feedforward amplifier having a predistortion circuit, comprising:
a divider for branching an input signal into plural branched signals;
a first vector adjustment circuit for varying an amplitude and a phase of one of the branched signals;
the predistortion circuit according to any one of claims 2, 3, 7, and 8 for receiving an output signal of the first vector adjustment circuit;
a first power amplifier for receiving an output signal of the predistortion circuit;
first distortion level detecting means of detecting a magnitude of a distortion component included in an output signal of the first power amplifier;
a first delay circuit for receiving the other branched signal;
a first combining circuit for combining an output signal of the first delay circuit and the output signal of the first power amplifier;
a second delay circuit for delaying the output signal of the first power amplifier;
signal level detecting means of detecting a magnitude of an output signal of the first combining circuit;
a second vector adjustment circuit for varying an amplitude and a phase of the output signal of the first combining circuit;
a second power amplifier for receiving an output signal of the second vector adjustment circuit;
a second combining circuit for combining an output signal of the second power amplifier and an output signal of the second delay circuit;
second distortion level detecting means of detecting a magnitude of a distortion component included in an output signal of the second combining circuit; and
control means of controlling the predistortion circuit, the first vector adjustment circuit, and the second vector adjustment circuit based on output signals of the first distortion level detecting means, the signal level detecting means, and the second distortion level detecting means, respectively,
wherein the control means repeatedly performs, in arbitrary order, a first control of controlling at least the predistortion circuit so as to minimize a distortion level detected by the first distortion level detecting means, a second control of controlling at least the first vector adjustment circuit so as to minimize a signal level detected by the signal level detecting means, and a third control of controlling at least the second vector adjustment circuit so as to minimize a distortion level detected by the second distortion level detecting means.
20. The feedforward amplifier having a predistortion circuit according to claim 19, wherein:
the first delay circuit is a variable delay circuit whose delay time is variable;
a variation amount of a delay time when each of the first vector adjustment circuit and the predistortion circuit was controlled is stored in the control means; and
the control means controls the predistortion circuit and the variable delay circuit as the first control, controls the first vector adjustment circuit and the variable delay circuit as the second control, and controls only the second vector adjustment circuit as the third control.
21. A predistortion circuit comprising:
a divider for branching an input signal into plural branched signals;
a delay circuit for delaying one of the branched signals by a predetermined delay time;
a distortion generating circuit for receiving the other branched signal and for generating a distortion signal;
a vector adjustment circuit for varying an amplitude and a phase of the distortion signal; and
an amplitude frequency characteristic adjustment circuit for varying an amplitude frequency characteristic of the distortion signal that is output from the vector adjustment circuit;
a combining circuit for combining an output signal of the delay circuit and an output signal of the vector adjustment circuit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An truck body for transporting hard rock mined ore, the truck body comprising;
a body floor having a rear edge at which the hard rock mined ore loaded into the body is released when the body is moved into a dumping position, the body floor including a first material forming a floor structure and a liner structure of a second material covering at least a portion of the floor surface, the second material having a hardness that is higher than a hardness of the first material;
a body front wall for confining a load of the hard rock mined ore; and
two opposing body sidewalls for confining the load at opposing sides of the truck body, the sidewalls tapering outwardly from front to rear of the truck body such that a width between the body sidewalls at the rear of the truck body is at least 10% greater than a width between the body sidewalls at the front of the truck body, the outward tapering of the body sidewalls promoting movement of the load away from the body sidewalls as the load is released from the truck body.
2. The truck body recited in claim 1, wherein the liner structure is formed by a plurality of discrete pieces arranged in a pattern over the floor surface.
3. The truck body recited in claim 2, wherein the discrete pieces are spaced apart, such that a gap is formed between adjacent pieces of the liner structure, the floor surface of the first material being exposed in the gap between the respective pieces of liner structure.
4. The truck body recited in claim 2, wherein the discrete pieces include a plurality of elongate strips, each extending in a direction that is at an angle between 45\xb0 and 90\xb0 from a longitudinal axis of the truck body.
5. The truck body recited in claim 1, wherein the liner structure includes a chromium carbide overlay.
6. The truck body recited in claim 1, wherein the liner structure includes a material having a Mohs scale hardness of at least 7 and a Vickers hardness of at least 1280 HV.
7. The truck body recited in claim 1, wherein a majority of the body sidewalls are free of the liner structure.
8. The truck body recited in claim 1, wherein an entirety of the body sidewalls are free of the liner structure.
9. The truck body recited in claim 1, wherein a gusset plate is disposed at an intersection between each body sidewall and the body floor, and wherein the liner structure includes transitions pieces that extend between the body floor and the gusset plate.
10. The truck body recited in claim 1, wherein the width between the truck body sidewalls at the rear of the truck body is 10% to 15% greater than the width between the truck body sidewalls at the front of the truck body.
11. The truck body recited in claim 1, wherein the width between the body sidewalls at the rear of the truck body is at least 36 inches greater than the width between the body sidewalls at the front of the truck body.
12. The truck body recited in claim 1, further comprising non-stick surfaces bridging intersections of the body floor, body front wall and one of the body sidewalls.
13. The truck body recited in claim 12, wherein the non-stick surfaces include a hydrophobic or oleophobic material.
14. A method of transporting hard rock mined ore using a truck, the method comprising:
depositing a load of hard rock mined ore having a hardness into a truck body of the truck, the truck body including:
a floor having an edge at which the load of hard rock mined ore in the body is released when the body is moved into a dumping position and including a first material forming a floor surface that has a hardness below the hard rock mined ore hardness and a liner structure of a second material that has a hardness greater than the hard rock mined ore hardness and covering at least a portion of the floor surface,
a body front wall for confining a load of the hard rock mined ore, and
two opposing body sidewalls for confining the load at opposing sides of the truck body, the body sidewalls tapering outwardly from front to rear of the truck body such that a width between the body sidewalls at a rear of the truck body is at least 10% greater than a width between the body sidewalls at the front of the truck body;

pivoting the front of the truck body upward to dump the load of hard rock mined ore from the truck body;
releasing lateral confinement of the load as it falls out of the truck body such that the load recedes from the outward tapering body sidewalls as the load falls, thereby preventing abrasion of the body sidewalls by the hard rock mined ore, and protecting the floor surface of the truck body floor from abrasion using the liner structure.
15. The method recited in claim 14, wherein the second material has a Mohs scale hardness of at least 7 and a Vickers hardness of at least 1280 HV.
16. The method recited in claim 14, wherein the liner structure is formed by a plurality of discrete pieces arranged in a pattern over the floor surface and spaced apart from one another in a longitudinal direction of the truck body, such that a gap is formed between adjacent pieces of the overlay where the floor surface is exposed.
17. The method recited in claim 14, wherein the liner structure includes chromium carbide overlay.
18. The method recited in claim 14, wherein a majority of the body sidewalls are free of the liner structure.
19. A truck body for hauling hard rock mined ore that is harder than a structural material of the truck body, the truck body comprising:
a body floor having an edge at which hard rock mined ore loaded into the body is released when the body is moved into a dumping position, the body floor including a floor surface formed by the structural material;
a body front wall for confining a load of the hard rock mined ore; and
two opposing body sidewalls for confining the load at opposing sides of the truck body;
a means for covering at least a portion of the floor surface of the body floor so as to protect the floor surface from abrasion by the hard rock mined ore during dumping of the load;
and a means for removing lateral confinement of the load during dumping so as to protect the body sidewalls from abrasion by the hard rock mined ore during dumping.
20. The truck body recited in claim 19, wherein a majority of the body sidewalls are free of the means for covering at least a portion of the floor surface.

What is claimed is:

1. A method of manufacturing a plate for a battery electrode comprising the steps of: passing a thin metal sheet between a pair of embossing rotation rollers having concave portions and convex portions formed on a peripheral surface thereof to form concave portions and convex portions on an entire surface of said metal sheet, and form pores each on an apex of each of said concave portions and convex portions and generate burrs each projecting outward from a peripheral edge of each of said pores by a pressing force during formation of said concave portions and convex portions.
2. A method of manufacturing a plate for a battery electrode comprising the steps of: passing a thin metal sheet between a pair of rotation rollers comprising an embossing roller having concave portions and convex portions formed on a peripheral surface thereof and a rubber roller having smooth outer surface to form pores on said metal sheet and generate burrs each projecting toward one side from a peripheral edge of each of said pores by pressing said rubber roller against said convex portions of said embossing roller.
3. A method of manufacturing a plate for a battery electrode comprising the steps of: passing a thin metal sheet sequentially between first and second sets of rotation rollers each consisting of an embossing roller having concave portions and convex portions formed on a peripheral surface thereof and a rubber roller having smooth outer surface to form pores on said metal sheet and generate burrs each projecting toward one side from a peripheral edge of each of said pores by pressing said rubber roller against said convex portions of said embossing roller when said metal sheet is passing between the embossing roller and-the rubber roller of said first set; and passing said metal sheet between the embossing roller and the rubber roller of said second set to form pores on said metal sheet at different positions thereof and generate burrs each projecting toward the other side from said peripheral edge of each of said pores.
4. The method of manufacturing a plate for a battery electrode according to any one of claims 1 through 3, wherein metal sheets of the same kind or different kinds, according to claims 1, 2, and 3, having said pores and said burrs each projecting from the peripheral edge of each of said pores are layered one upon another; and said burrs of an upper layer metal sheet and said burrs of a lower layer metal sheet adjacent to said upper layer metal sheet are interlocked with each other to integrate said upper layer metal sheet and said lower layer metal sheet with each other; and spaces between said upper layer metal sheet and said lower layer metal sheet are communicated with each other through said pores.
5. A plate for a battery electrode manufactured by the method according to any one of claims 1 through 4.
6. A plate for a battery electrode which is manufactured by the method according to claim 4 and comprises a first metal sheet, having pores each on an apex of each of concave portions and convex portions and burrs each projecting outward from a peripheral edge of each of said pores and second metal sheets, having burrs projecting toward one side and are layered on a surface at both sides of said first metal sheet and sandwiching said first metal sheet therebetween, whose said burrs are projected toward an inner surface side of said metal sheets.
7. A plate for a battery electrode which is manufactured by the method according to claim 4 and comprises a third metal sheet, having burrs each projecting toward both directions from a peripheral edge of each of said pores and second metal sheets, having burrs projecting toward one side and are layered on a surface at both sides of said third metal sheet and sandwiching said third metal sheet therebetween, whose said burrs are projected toward an inner surface side of said metal sheets.
8. The plate for a battery electrode according to any one of claims 5 through 7, wherein said metal sheet consists of a metal foil orand metal sheet formed by rolling metal powder.
9. The plate for a battery electrode according to claim 8, wherein said metal sheet consists of Ni, Al, Cu, Fe, Ag, Zn, Sn, Pb, Sb, Ti, In, V, Cr, Co, C, Ca, Mo, Au, P, W, Rh, Mn, B, Si, Ge, Se, La, Ga, Ir or an alloy of said elements.
10. The plate for a battery electrode according to any one of claims 5, 6, 8, and 9, wherein in an electrode plate for a battery which is manufactured by the method according to claim 1, a pitch between concave portions and that between convex portions are set to 0.5 mm -2.0 mm; and the height of each of said concave portions and that of said convex portions are set to 0.1 mm -2 mm.
11. An electrode for a battery in which an active substance is charged into spaces of said plate, according to any one of claims 5 through 10.
12. An electrode for a battery according to claim 11, wherein said active substance contains an electrically conductive material.
13. A battery comprising said electrode for a battery according to claim 11 or 12.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method, comprising the steps of:
providing an interface assembly comprising at least one test electronics module to make electrical connections with a test apparatus;
configuring a first side of a probe card assembly to make electrical connections with said test electronics modules;
configuring a plurality of probes on a second side of said probe card assembly to make electrical connections with at least one semiconductor device; and
configuring test electronics to receive as input signals received from any of said test apparatus and said semiconductor device, process said received signals there within, and output said processed received signals, at least a portion of said test electronics being disposed on said test electronics modules.
2. The method of claim 1, wherein said test electronics comprise any of passive components, active components, and combinations thereof.
3. The method of claim 1, wherein said test electronics comprise any of a power control module, a decoupling capacitor, a switching control circuit, a regulator, a controller, a pattern generator, a signal measurement circuit, a response detection circuit, a fail detection circuit, means for storing any of passfail information, a relay, a switch, means for determining any of a short circuit and an open circuit, means for testing any of a power pin and an IO pin of said semiconductor device, and means for functional testing of said semiconductor device.
4. The method of claim 1, wherein at least a portion of said test electronics module is disposed substantially coplanar to said probe card assembly.
5. The method of claim 1, wherein said interface assembly further comprises a system board configured between said at least one test electronics module and said substrate.
6. The method of claim 5, wherein said interface assembly further comprises an interposer configured any of or both of between said system board and said substrate and between said test electronics module and said system board.
7. The method of claim 1, wherein said interface assembly comprises a plurality of said test electronics modules.
8. The method of claim 7, wherein each of said plurality of test electronics modules are disposed parallel to each other.
9. The method of claim 1, wherein said test electronics process at least a portion of said signals for testing of said semiconductor device.
10. The method of claim 1, wherein at least a portion of said signals comprise response signals generated by said semiconductor device, and
wherein said test electronics process at least a portion of said generated response signals.
11. The method of claim 1, wherein at least a portion of said signals are test signals generated by said test apparatus, and
wherein said test electronics process at least a portion of said generated test signals.
12. The method of claim 1, wherein said plurality of probes are configured to contact a plurality of semiconductor devices under test.
13. The method of claim 1, wherein said probe card assembly comprises a probe card substrate and a plurality of electrically conductive vias extending therethrough.
14. A probe card assembly, comprising;
an interface assembly comprising at least one test electronics module for making electrical connections with a test apparatus;
a substrate having a first side and a second side opposite said first side, said substrate further comprising electrical contacts that are electrically connected to said test electronics modules and extend from said first side to probes located on and extending from said second side, said probes configured to electrically contact at least one semiconductor device; and
test electronics configured to receive as input signals received from any of said test apparatus and said semiconductor device, process said received signals there within, and output said processed received signals, at least a portion of said test electronics being located on said test electronics modules.
15. The probe card assembly of claim 14, wherein said test electronics comprise any of passive components, active components, and combinations thereof.
16. The probe card assembly of claim 14, wherein said test electronics comprise any of a power control module, a decoupling capacitor, a switching control circuit, a regulator, a controller, a pattern generator, a signal measurement circuit, a response detection circuit, a fail detection circuit, means for storing any of passfail information, a relay, a switch, means for determining any of a short circuit and an open circuit, means for testing any of a power pin and an IO pin of said semiconductor device, and means for functional testing of said semiconductor device.
17. The probe card assembly of claim 14, further comprising:
a system board configured between said at least one test electronics module and said substrate.
18. The probe card assembly of claim 14, further comprising:
an interposer configured any of or both of between said system board and said substrate and between said test electronics module and said system board.