All The Claims

1. A method for large-scale decontamination of biological microbes, consisting essentially of the steps of:
applying an acidic environment to large-scale biological spores contamination; and,
applying an amine oxide compound in combination with the acidic environment effective for large-scale decontamination of the biological microbes.
2. The method of claim 1, wherein the step of applying an acidic environment comprises application of an acidic solution.
3. The method of claim 1, wherein the step of applying an acidic environment comprises a pH of less than about 6.9.
4. The method of claim 3, wherein the step of applying an acidic environment comprises a pH of from about 3.0 to about 6.0.
5. The method of claim 4, wherein the step of applying an acidic environment comprises a pH of from about 4.0 to about 6.0.
6. The method of claim 2, wherein the acidic solution is selected from the group consisting of organic acids, inorganic acids and combinations thereof.
7. The method of claim 2, wherein the acidic solution is selected from the group consisting of oxalic acid, acetic acid, phosphoric acid, hydrochloric acid, sulfuric acid, carboxylic acids, and combinations thereof.
8. The method of claim 2, wherein the acidic solution is present in an amount of from about 1 mM to about 1,000 mM.
9. The method of claim 8, wherein the acidic solution is present in an amount of from about 20 mM to about 50 mM.
10. The method of claim 1, wherein the amine oxide is selected from the group consisting of decyl dimethyl amine oxide, cocoa dimethyl amine oxide, isoalkyl dimethyl amine oxide and combinations thereof.
11. The method of claim 1, further comprising the step of placing the applied acidic environment in a heated condition.
12. The method of claim 11, wherein the heated condition includes a moderately heated condition.
13. The method of claim 12, wherein the step of moderately heating the biological spores comprises a temperature of from about 25\xb0 C. to about 100\xb0 C.
14. The method of claim 13, wherein the step of moderately heating the biological spores comprises a temperature of from about 65\xb0 C. to about 85\xb0 C.
15. The method of claim 1, wherein the step of moderately heating the biological spores comprises an exothermic chemical reaction.
16. The method of claim 1, wherein the step of moderately heating the biological spores comprises an external heat source.
17. The method of claim 1, wherein the biological microbes comprises endospores.
18. The method of claim 1, wherein the biological microbes comprises Bacillus endospores.
19. The large-scale decontaminated microbe product produced by the method of claim 1.
20. A method for large-scale decontamination of biological microbes, comprising the steps of:
washing a biological microbe contaminant from a decontamination site into a waste water product;
applying an acidic environment to the contaminated wash product; and,
applying an amine oxide compound in combination with the acidic environment to the wash product effective for decontamination of the biological microbes within the wash product.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A through-hole layout apparatus comprising:
an extractor extracting an existing through-hole interconnecting an upper layer wiring and a lower layer wiring from design data for a semiconductor integrated circuit;
a calculator calculating, for each through-hole extracted by said extractor, a layout density of through-holes in a predetermined region centered on said through-hole;
a selector selecting a through-hole at a center of a predetermined region where said layout density calculated by said calculator is lower than a predetermined value as a target through-hole from among said through-holes extracted by the extractor; and
a through-hole adder determining, for each target through-hole selected by the selector, a first given position in a predetermined region centered on said target through-hole as a placement position at which a through-hole is to be added and adding a through-hole at said placement position on said design data.
2. The through-hole layout apparatus according to claim 1, wherein said first given position in said predetermined region is at a predetermined distance from said target through-hole in a predetermined direction in said predetermined region, is on an upper layer wiring that is connected to said target through-hole, and is a position where no through-hole is placed.
3. The through-hole layout apparatus according to claim 2, wherein if there is room for extending an lower layer wiring that is connected to said target through-hole to a position corresponding to said placement position, said through-hole adder extends said lower layer wiring to said position corresponding to said placement position and adds a through-hole interconnecting said upper layer wiring and said lower layer wiring at said placement position on said design data.
4. The through-hole layout apparatus according to claim 2, wherein if there is no room for extending an lower layer wiring that is connected to said target through-hole to a position corresponding to said placement position, said through-hole adder places an interlayer wiring at a position corresponding to said placement position between said upper layer wiring and said lower layer wiring and adds a through-hole interconnecting said upper layer wiring and said interlayer wiring at said placement position on said design data.
5. The through-hole layout apparatus according to claim 1, wherein:
said extractor extracts a through-hole from processed design data to which a through-hole has been added by said through-hole adder;
said calculator calculates, for each of through-holes extracted by said extractor, excluding a through-hole added by said through-hole adder, a layout density of through-holes in a predetermined region centered on said through-hole;
said selector selects a through-hole at the center of a predetermined region where said layout density calculated by said calculator is lower than a predetermined value as a target through-hole from among through-holes extracted by said extractor, excluding said through-holes added by said through-hole adder; and
said through-hole adder determines, for each target through-hole selected by said selector, a second given position in a predetermined region centered on said target through-hole as a placement position at which a through-hole is to be added and adds a through-hole at said placement position on said processed design data.
6. The through-hole layout apparatus according to claim 5, wherein said second given position in said predetermined region is a position at said predetermined distance from said target through-hole at said predetermined direction in said predetermined region and is a position where there is room for extending an upper layer wiring that is connected to said target through-hole, or a position which is on an upper layer wiring adjacent to said upper layer wiring and at which no through-hole is placed.
7. The through-hole layout apparatus according to claim 6, wherein if said placement position is a position at which there is room for extending said upper layer wiring that is connected to said target through-hole, said through-hole adder extends said upper layer wiring to said placement position and, if there is room for extending a lower layer wiring that is connected to said target through-hole to a position corresponding to said placement position, extends said lower layer wiring to said position corresponding to said placement position and adds a through-hole interconnecting said upper layer wiring and said lower layer wiring at said placement position on said processed design data.
8. The through-hole layout apparatus according to claim 6, wherein if said placement position is a position at which there is room for extending said upper layer wiring that is connected to said target through-hole, said through-hole adder extends said upper layer wiring to said placement position and, if there is no room for extending a lower layer wiring that is connected to said target through-hole to a position corresponding to said placement position, places an interlayer wiring at a position corresponding to said placement position between said upper layer wiring and said lower layer wiring and adds a through-hole interconnecting said upper layer wiring and said interlayer wiring at said placement position on said processed design data.
9. The through-hole layout apparatus according to claim 6, wherein if said placement position is on said adjacent upper layer wiring and is a position where no through-hole is placed, said through-hole adder places an interlayer wiring at a position corresponding to said placement position between said upper layer wiring and said interlayer wiring and adds a through-hole interconnecting said upper layer wiring and said lower layer wiring at said placement position on said processed design data.
10. A through-hole layout method performed by a through-hole layout apparatus, comprising:
extracting an existing through-hole interconnecting an upper layer wiring and a lower layer wiring from design data for a semiconductor integrated circuit;
calculating, for each extracted through-hole, a layout density of through-holes in a predetermined region centered on said through-hole;
selecting a through-hole at the center of a predetermined region where said calculated layout density is lower than a predetermined value as a target through-hole from among said extracted through-holes;
determining, for each selected target through-hole, a given position in a predetermined region centered on said target through-hole as a placement position at which a through-hole is to be added; and
adding a through-hole at said placement position on said design data.
11. The through-hole layout method according to claim 10, wherein said first given position in said predetermined region is at a predetermined distance from said target through-hole in a predetermined direction in said predetermined region, is on an upper layer wiring that is connected to said target through-hole, and is a position where no through-hole is placed.
12. The through-hole layout method according to claim 11, wherein, in adding a through-hole at said placement position, if there is room for extending an lower layer wiring that is connected to said target through-hole to a position corresponding to said placement position, said lower layer wiring is extended to a position corresponding to said placement position and a through-hole interconnecting said upper layer wiring and said lower layer wiring is added at said placement position on said design data.
13. The through-hole layout method according to claim 11, wherein, in adding a through-hole at said placement position, if there is no room for extending an lower layer wiring that is connected to said target through-hole to a position corresponding to said placement position, an interlayer wiring is placed at a position corresponding to said placement position between said upper layer wiring and said lower layer wiring and a through-hole interconnecting said upper layer wiring and said interlayer wiring is added at said placement position on said design data.
14. The through-hole layout method according to claim 10, wherein, in adding a through-hole in said placement position,
re-extraction is performed to extract a through-hole from processed design data to which a through-hole has been added;
recalculation is performed to calculate, for each of said through-holes extracted by said re-extraction excluding said through-hole added to said placement position, a layout density of through-holes in a predetermined region centered on said through-hole;
re-selection is performed to select a through-hole at the center of a predetermined region where said layout density calculated by said recalculation is lower than a predetermined value as a target through-hole from among through-holes extracted by said re-extraction excluding said through-hole added to said placement position; and
re-addition is performed by determining, for each target through-hole selected by said reselection, a second given position in a predetermined region centered on said target through-hole as a placement position at which a through-hole is to be added and adding a through-hole at said placement position on the processed design data.
15. The through-hole layout method according to claim 14, wherein said second given position in said predetermined region is a position at said predetermined distance from said target through-hole at said predetermined direction in said predetermined region and is a position where there is room for extending an upper layer wiring that is connected to said target through-hole, or a position which is on an upper layer wiring adjacent to said upper layer wiring and at which no through-hole is placed.
16. The through-hole layout method according to claim 15, wherein in performing said re-addition, if said placement position is a position at which there is room for extending said upper layer wiring that is connected to said target through-hole, said upper layer wiring is extended to said placement position and, if there is room for extending a lower layer wiring that is connected to said target through-hole to a position corresponding to said placement position, said lower layer wiring is extended to said position corresponding to said placement position and a through-hole interconnecting said upper layer wiring and said lower layer wiring is added at said placement position on said processed design data.
17. The through-hole layout method according to claim 15, wherein in performing said re-addition, if said placement position is a position at which there is room for extending said upper layer wiring that is connected to said target through-hole, said upper layer wiring is extended to said placement position and, if there is no room for extending a lower layer wiring that is connected to said target through-hole to a position corresponding to said placement position, an interlayer wiring is placed at a position corresponding to said placement position between said upper layer wiring and said lower layer wiring and a through-hole interconnecting said upper layer wiring and said interlayer wiring is added at said placement position on said processed design data.
18. The through-hole layout method according to claim 15, wherein in performing said re-addition, if said placement position is on said adjacent upper layer wiring and is a position where no through-hole is placed, an interlayer wiring is placed at a position corresponding to said placement position between said upper layer wiring and said lower layer wiring and a through-hole interconnecting said upper layer wiring and said interlayer wiring is added at said placement position on said processed design data.
19. A through-hole layout apparatus comprising:
an extractor means for extracting an existing through-hole interconnecting an upper layer wiring and a lower layer wiring from design data for a semiconductor integrated circuit;
a calculator means for calculating, for each through-hole extracted by said extractor, a layout density of through-holes in a predetermined region centered on said through-hole;
a selector means for selecting a through-hole at a center of a predetermined region where said layout density calculated by said calculator is lower than a predetermined value as a target through-hole from among said through-holes extracted by the extractor; and
a through-hole adder means for determining, for each target through-hole selected by the selector, a given position in a predetermined region centered on said target through-hole as a placement position at which a through-hole is to be added and adding a through-hole at said placement position on said design data.

1. An information processing apparatus that is capable of communicating with a web server and includes a web browser that displays an operation screen provided by the web server, the apparatus comprising:
an acceptance unit configured to accept an instruction for screen transition from a user;
a processing unit configured to execute a job instructed by the web server;
a management unit configured to manage a status of the job executed by the processing unit; and
a control unit configured to restrict, based on the status of the job managed by the management unit, acceptance of the instruction by the accepting unit while the processing unit is executing the job.
2. The information processing apparatus according to claim 1, wherein the screen transition is caused by operating a predetermined button displayed on the operation screen.
3. (canceled)
4. The information processing apparatus according to claim 1, further comprising:
a display control unit configured to display a confirmation screen for asking the user whether to perform screen transition,
wherein the control unit permits acceptance of the instruction by the acceptance unit if the user permits screen transition via the confirmation screen.
5. A control method for an information processing apparatus that is capable of communicating with a web server and includes a web browser that displays an operation screen provided by the web server, the method comprising:
accepting an instruction for screen transition from a user;
executing a job instructed by the web server;
managing a status of the executed job; and
controlling to restrict, based on the managed status of the executed job, acceptance of the instruction by the accepting step while the job is being executed.
6. A non-transitory computer-readable storage medium which stores a program for causing a computer to function as an information processing apparatus that is capable of communicating with a web server and includes a web browser that displays an operation screen provided by the web server, the program comprising:
an acceptance step of accepting an instruction for screen transition from a user;
a processing step of executing a job instructed by the web server;
a management step of managing a status of the executed job; and
a control step of restricting, based on the managed status of the job, acceptance of the instruction by the accepting step while the job is being executed.
7. An information processing apparatus that is capable of communicating with a web server and includes a web browser that displays an operation screen provided by the web server, the apparatus comprising:
an acceptance unit configured to accept an instruction for screen transition from a user;
a processing unit configured to execute processing requested by the web server in response to an operation performed by the user using the operation screen displayed by the web browser;
a determination unit configured to determine whether a prohibition request indicating to prohibit the screen transition has been provided by the web server together with the operation screen; and
a control unit configured to restrict acceptance of the instruction by the acceptance unit while the processing unit is executing the processing, if the determination unit determines that the prohibition request has been provided.
8. A control method for an information processing apparatus that is capable of communicating with a web server and includes a web browser that displays an operation screen provided by the web server, the method comprising:
accepting an instruction for screen transition from a user;
executing processing requested by the web server in response to an operation performed by the user using the operation screen displayed by the web browser;
determining whether a prohibition request indicating to prohibit the screen transition has been provided by the web server together with the operation screen; and
controlling to restrict acceptance of the instruction in the acceptance step while the processing is being executed, if it is determined in the determination that the prohibition request has been provided.
9. A non-transitory computer-readable storage medium which stores a program for causing a computer to function as an information processing apparatus that is capable of communicating with a web server and includes a web browser that displays an operation screen provided by the web server, the program comprising:
an acceptance step of accepting an instruction for screen transition from a user;
a processing step of executing processing requested by the web server in response to an operation performed by the user using the operation screen displayed by the web browser;
a determination step of determining whether a prohibition request indicating to prohibit the screen transition has been provided by the web server together with the operation screen; and
a control step of restricting acceptance of the instruction by the acceptance step while the processing is being executed, if it is determined in the determination step that the prohibition request has been provided.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A trench MOSFET with a plurality of transistor cells in active area and multiple trenched floating gates in termination area, comprising:
a substrate of a first conductivity type;
an epitaxial layer of said first conductivity type grown on said substrate, said epitaxial layer having a lower doping concentration than said substrate;
a plurality of source regions of said first conductivity type formed near top surface of said epitaxial layer only within said active area, said source regions having a doping concentration higher than said epitaxial layer;
a plurality of first type body regions of a second conductivity type formed beneath said source regions in said active area;
a plurality of second type body regions of said second conductivity type formed into said epitaxial layer from top surface of said epitaxial layer around outside of said active area including said termination area;
said source regions being not disposed in the top of said second type body regions;
an insulation layer formed on said epitaxial layer;
a plurality of first type gate trenches in active area surrounded by said source regions and said first type body regions, extending into said epitaxial layer and filled with gate conductive layer over gate oxide layer as first type trenched gates of said transistor cells for current conduction;
at least one second type trenched gate having gate oxide layer formed thereon, said second trenched gate being wider and deeper than said first type trenched gates, surrounded by said second type body region and extending into said epitaxial layer and filled with gate conductive layer as trenched gates for gate connection;
at least three third type trenched gates in parallel formed in termination area around outside of said active area having said gate oxide layer formed thereon, said third type trenched gates surrounded by said second type body region and extended into said epitaxial layer and filled with said gate conductive layer as trenched floating gates with floating voltage for sustaining breakdown voltage in termination area, said third type trenched gates having trench depth equal to or deeper than body junction of said second type body regions;
each said second type body region between two adjacent said trenched floating gates in termination area having floating voltage;
a plurality of trenched source-body contacts filled with metal plugs padded by a barrier layer, each penetrating through said insulation layer and one of said source regions and extending into one of said first type body regions between two adjacent said first type trenched gates, said metal plugs being connected to a first metal layer formed on said insulation layer as source metal;
at least one trenched gate contact filled with said metal plug padded by said barrier layer, penetrating through said insulation layer and extending into said gate conductive layer, said metal plug being connected to a second metal layer on said insulation layer serving as gate metal; and
a drain metal on rear side of said substrate.
2. The MOSFET of claim 1 further comprising a body contact region of said second conductivity type underneath each of said plurality of trenched source-body contact, said body contact region having a higher doping concentration than said first body region.
3. The MOSFET of claim 1, wherein said third type trenched gates as trenched floating gates in said termination area have same trench width and depth as said first type trenched gates in said active area.
4. The MOSFET of claim 1, wherein said third type trenched gates as trenched floating gates in said termination area have wider trench width than said first type trenched gates in said active area.
5. The MOSFET of claim 1, wherein the width of said third type trenched gates as trenched floating gates in termination area increases toward the edge of said termination area.
6. The MOSFET of claim 1, wherein the width of said third type trenched gates as trenched floating gates in termination area decreases toward the edge of said termination area.
7. The MOSFET of claim 1, wherein said first type trenched gates in active area are equal to or shallower than said first type body region.
8. The MOSFET of claim 1, wherein said first type trenched gates in active area are deeper than said first type body region.
9. The MOSFET of claim 7, wherein there is a doped region of said first conductivity type with doping concentration higher than said epitaxial layer wrapping each bottom of said plurality of said first type trenched gates in active area, said second type trenched gate for gate connection and said third type trenched gates in termination area.
10. The MOSFET of claim 1, wherein the trench space between every two adjacent of said third type trenched gates in termination area is equal.
11. The MOSFET of claim 1, wherein the trench space between every two adjacent of said third type trenched gates in termination area is increased toward the edge of said termination area.
12. The MOSFET of claim 1, wherein said metal plug is Tungsten (W) or Al alloys.
13. The MOSFET of claim 1, wherein said barrier layer is TiTiN or CoTiN or TaTiN.
14. The MOSFET of claim 1 further comprising a resistance reduction layer Ti or TiN padded between said source metal and metal plugs, and said gate metal and metal plugs.
15. The MOSFET of claim 1, wherein said source metal and said gate metal are Al alloys, Cu or NiAg.
16. The MOSFET of claim 1, wherein said plurality of transistor cells are closed cells.
17. The MOSFET of claim 1, wherein said plurality of transistor cells are stripe cells.
18. The MOSFET of claim 1, wherein said second type body regions between said second type trenched gate and adjacent said third type trenched gate are electrically connected to said source region.
19. The MOSFET of claim 1, wherein said second type regions between said second type trenched gate and adjacent said third type trenched gate is not electrically connected to said source regions and have floating voltage.
20. The MOSFET of claim 1 further comprising a trenched body contact filled with said metal plug padded by said barrier layer, penetrating through said insulation layer and extending into said second type body region between said first type trenched gate and adjacent said second type trenched gate, said metal plug being connected to said source metal.
21. The MOSFET of claim 20 further comprising a body contact region underneath each of said trenched body contact, said body contact region having said second conductivity type with higher doping concentration than said second type body regions.
22. The MOSFET of claim 1, there is no said trenched body contact of claim 20 into said second type body region between said first type trenched gates and adjacent said second type trenched gate.