All The Claims

1. An illumination system comprising:
a phosphor light source configured to emit light having a wavelength in a wavelength band \u0394\u03bbPHOSPHOR;
a second light source configured to emit light at a second wavelength \u03bb2 within an absorption band of the phosphor light source;
a third light source configured to emit light at a third wavelength \u03bb3;
a fourth light source configured to emit light at a fourth wavelength \u03bb4;
a controller configured to drive the second light source, the third light source and the fourth light source;
a first dichroic optical element configured to: 1) direct light emitted by the phosphor light source in the wavelength band \u0394\u03bbPHOSPHOR to an optical output of the illumination system, 2) direct light emitted by the third light source at the third wavelength \u03bb3 to the optical output of the illumination system, and 3) direct light emitted by the fourth light source at the fourth wavelength \u03bb4 to the optical output of the illumination system; and
a second dichroic optical element configured to: 1) direct the light emitted by the third light source at the third wavelength \u03bb3 to the first dichroic optical element, and 2) direct the light emitted by the fourth light source at the fourth wavelength \u03bb4 to the first dichroic optical element.
2. The illumination system of claim 1, wherein the first dichroic optical element is further configured to direct light emitted by the second light source at the second wavelength \u03bb2 onto the phosphor light source.
3. The illumination system of claim 1, further comprising a first light source configured to emit light at a first wavelength \u03bb1 onto the phosphor light source.
4. The illumination system of claim 3, wherein the phosphor light source is physically attached to the first light source.
5. The illumination system of claim 3, wherein the phosphor light source is physically separate from the first light source.
6. The illumination system of claim 5, wherein the phosphor light source is a ceramic phosphor or a single crystal phosphor.
7. The illumination system of claim 3, wherein the wavelength of the light emitted by the phosphor light source is longer than the first wavelength \u03bb1.
8. The illumination system of claim 3, wherein the controller is further configured to drive the first light source.
9. The illumination system of claim 3, wherein the first dichroic optical element is further configured to direct light emitted by the first light source at the first wavelength \u03bb1 along with the light emitted by the phosphor light source in the wavelength band \u0394\u03bbPHOSPHOR to the optical output of the illumination system.
10. The illumination system of claim 3, wherein the first, third and fourth light sources are light emitting diodes.
11. The illumination system of claim 3, wherein the controller is configured to drive the second light source to optically pump the phosphor light source without concurrently driving the first light source to optically pump the phosphor.
12. The illumination system of claim 3, wherein the light emitted by the first light source at the first wavelength, the light emitted by the phosphor light source in the wavelength band \u0394\u03bbPHOSPHOR, the light emitted by the second light source at the second wavelength, the light emitted by the third light source at the third wavelength, and the light emitted by the fourth light source at the fourth wavelength travel from the first dichroic optical element to the optical output along a common optical path.
13. The illumination system of claim 3, wherein the illumination system is switchable between two or more of the following operating modes:
a first operating mode in which only the first light source is energized to optically pump the phosphor light source;
a second operating mode in which only the second light source is energized to optically pump the phosphor light source; and
a third operating mode in which the first light source and the second light source are energized to optically pump the phosphor light source.
14. The illumination system of claim 13, wherein the illumination system is switchable between all three of the operating modes.
15. The illumination system of claim 13, wherein the controller is configured to implement any of the switching between the operating modes.
16. The illumination system of claim 15, further comprising a user interface device, wherein the controller is configured to implement the switching in response to an instruction from the user interface device.
17. The illumination system of claim 3, wherein the phosphor light source is configured to emit light in the wavelength band \u0394\u03bbPHOSPHOR only in response to first absorbing light from the first or second light sources.
18. The illumination system of claim 1, wherein the second light source is a laser.
19. The illumination system of claim 1, wherein the second light source is a light emitting diode.
20. The illumination system of claim 1, wherein the light emitted by the third light source at the third wavelength \u03bb3 and the light emitted by the fourth light source at the fourth wavelength \u03bb4 travel between the first dichroic optical element and the second dichroic optical element along a common optical path.
21. The illumination system of claim 1, wherein the first light source, the third light source and the fourth light source are light emitting diodes.
22. The illumination system of claim 1, further comprising:
a third dichroic optical element configured to 1) direct light emitted by the second light source at the second wavelength \u03bb2 onto the phosphor light source, and 2) direct light emitted by the phosphor toward the first dichroic optical element.
23. The illumination system of claim 22, further comprising:
an optical filter between the third dichroic optical element and the first dichroic optical element, wherein the optical filter is configured to filter out a portion of light emitted by the phosphor light source.
24. The illumination system of claim 1, wherein directing the light emitted by the phosphor light source in the wavelength band \u0394\u03bbPHOSPHOR to the optical output of the illumination system comprises transmitting the light emitted by the phosphor light source in the wavelength band \u0394\u03bbPHOSPHOR to the optical output of the illumination system with the first dichroic optical element,
wherein directing the light emitted by the third light source at the third wavelength \u03bb3 to the optical output of the illumination system comprises reflecting the light emitted by the third light source at the third wavelength \u03bb3 to the optical output of the illumination system with the first dichroic optical element,
wherein directing the light emitted by the fourth light source at the fourth wavelength \u03bb4 to the optical output of the illumination system comprises reflecting the fourth light source at the fourth wavelength \u03bb4 to the optical output of the illumination system with the first dichroic optical element,
wherein directing the light emitted by the third light source at the third wavelength \u03bb3 to the first dichroic optical element comprises transmitting the light emitted by the third light source at the third wavelength \u03bb3 to the first dichroic optical element with the second dichroic optical element, and
wherein directing the light emitted by the fourth light source at the fourth wavelength \u03bb4 to the first dichroic optical element comprises reflecting the light emitted by the fourth light source at the fourth wavelength \u03bb4 to the first dichroic optical element with the second dichroic element.
25. The illumination system of claim 1, wherein the first wavelength \u03bb1 is between 440 nm and 490 nm and \u0394\u03bbPHOSPHOR is between 500 nm and 750 nm.
26. The illumination system of claim 1, wherein the first wavelength \u03bb1 is between 445 nm and 475 nm and \u0394\u03bbPHOSPHOR is between 530 nm and 630 nm.
27. The illumination system of claim 1, wherein \u0394\u03bbPHOSPHOR is between 530 nm and 630 nm.
28. The illumination system of claim 1, wherein the second wavelength \u03bb2 is in a range selected from the group consisting of: 450 nm or less, 440 nm or less, and less than the first wavelength \u03bb1.
29. The illumination system of claim 1, wherein the first wavelength \u03bb1 is between 445 nm and 475 nm and the second wavelength \u03bb2 is 445 nm or less.
30. The illumination system of claim 1, wherein the third wavelength \u03bb3 is in the ultraviolet spectral region or the near ultraviolet spectral region.
31. The illumination system of claim 1, wherein each of the third wavelength \u03bb3 and the fourth wavelength \u03bb4 is in the near ultraviolet spectral region or the ultraviolet spectral region.
32. The illumination system of claim 1, wherein the second dichroic optical element has a band edge between the third wavelength \u03bb3 and the fourth wavelength \u03bb4.
33. An illumination system for fluorescence imaging and analysis, comprising:
a light source module comprising:
a first light source comprising a first light emitting device (LED) and a phosphor, the first LED for providing emission at a first wavelength \u03bb1 within an absorption band of the phosphor and the phosphor providing broadband light emission of longer wavelength comprising light in a wavelength band \u0394\u03bbPHOSPHOR; and
a second light source for providing light at a second wavelength \u03bb2, within the absorption band of the phosphor;

a controller for independently driving the first light source to generate emission at \u03bb1 and \u0394\u03bbPHOSPHOR and driving the laser and optically pumping the phosphor with the laser wavelength \u03bb2, to increase emission in the emission band of the phosphor \u0394\u03bbPHOSPHOR;
optical coupling means for coupling light emission to an optical output of the illumination system;
another light source comprising an LED emitting at a third wavelength \u03bb3, wherein the optical coupling means comprises a dichroic optical element having a band edge for reflecting the laser wavelength \u03bb2 onto the phosphor for optical pumping of the phosphor, for transmitting emission from the first LED and the phosphor, comprising \u03bb1 and \u0394\u03bbPHOSPHOR, and further for reflecting the third wavelength \u03bb3, for optically coupling light emission, comprising \u03bb1, \u0394\u03bbPHOSPHOR and \u03bb3, along a common optical axis to the optical output of the illumination system; and
yet another light source emitting at a fourth wavelength \u03bb4 and wherein the optical coupling means further comprises a second dichroic element for coupling emission comprising \u03bb3 and \u03bb4, via the first dichroic element, along the common optical axis to the optical output of the illumination system, the second dichroic element having a band edge between \u03bb3 and \u03bb4.
34. The system of claim 33, wherein the light at the second wavelength \u03bb2 is a laser emission or an LED light.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A voltage conversion circuit, comprising:
a switch circuit arranged so that a series circuit constituted of a P-type transistor and an N-type transistor is provided between a pair of power source lines in series;
a smoothing circuit for smoothing an output voltage derived from a junction of the P-type transistor and the N-type transistor of the switch circuit;
a pulse signal generating circuit for generating one or more pulse signals, each of which has a duty ratio for obtaining a desired output voltage, by using the output voltage smoothed by the smoothing circuit as a power source, so as to give the pulse signal to a control terminal of the P-type transistor and a control terminal of the N-type transistor;
a start-up control signal for generating a control signal which forces the P-type transistor to turn ON and giving the control signal to the control terminal of the P-type transistor during a predetermined period on start-up.
2. The voltage conversion circuit as set forth in claim 1, wherein the start-up control circuit includes:
a start-up signal generating circuit for generating a start-up signal which has a predetermined voltage level during the predetermined period on start-up; and
a switch control circuit, receiving the start-up signal and the pulse signal from the pulse signal generating circuit, which outputs a control signal whose voltage level causes the P-type transistor turn ON when the start-up signal has the predetermined voltage level, and outputs the pulse signal from the pulse signal generating circuit when the start-up signal does not have the predetermined voltage level.
3. The voltage conversion circuit as set forth in claim 1, wherein the pulse signal generating circuit includes:
a reference pulse signal generating circuit for generating a reference pulse signal in accordance with the output voltage from the smoothing circuit;
a delay circuit for delaying the reference pulse signal, which has been inputted, for the predetermined period; and
a delay time control circuit for setting a delay time of the delay circuit,
said voltage conversion circuit further comprising a step-up level shifter for increasing a voltage level of an output pulse signal of the delay circuit.
4. The voltage conversion circuit as set forth in claim 2, wherein the pulse signal generating circuit includes:
a reference pulse signal generating circuit for generating a reference pulse signal in accordance with the output voltage from the smoothing circuit;
a delay circuit for delaying the reference pulse signal, which has been inputted, for the predetermined period; and
a delay time control circuit for setting a delay time of the delay circuit,
said voltage conversion circuit further comprising a step-up level shifter for increasing a voltage level of an output pulse signal of the delay circuit.
5. The voltage conversion circuit as set forth in claim 1, wherein the start-up control circuit generates the control signal as a first control signal and also generates a second control signal for forcing the N-type transistor to turn OFF so as to give the second control signal to the control terminal of the N-type transistor during the predetermined period on start-up.
6. The voltage conversion circuit as set forth in claim 4, wherein the start-up control circuit includes:
a start-up signal generating circuit for generating a start-up signal having a predetermined voltage level during the predetermined period on start-up;
a first switch control circuit, receiving the start-up signal and one of the pulse signals from the pulse signal generating circuit as a first pulse signal for the P-type transistor, which outputs a first control signal whose voltage level causes the P-type transistor turn ON when the start-up signal has the predetermined voltage level, and outputs the first pulse signal from the pulse signal generating circuit when the start-up signal does not have the predetermined voltage level; and
a second switch control circuit, receiving the start-up signal and another of the pulse signals from the pulse signal generating circuit as a second pulse signal for the N-type transistor, which outputs a second control signal whose voltage level causes the N-type transistor turn ON when the start-up signal has the predetermined voltage level, and outputs the second pulse signal from the pulse signal generating circuit when the start-up signal does not have the predetermined voltage level.
7. The voltage conversion circuit as set forth in claim 5, wherein the pulse signal generating circuit includes:
a reference pulse signal generating circuit for generating a reference pulse signal in accordance with the output voltage from the smoothing circuit;
a delay circuit for delaying the reference pulse signal, which has been inputted, for the predetermined period; and
a delay time control circuit for setting a delay time of the delay circuit,
said voltage conversion circuit further comprising:
a switch timing control circuit for generating the pulse signals as first and second pulse signals in accordance with an output pulse signal of the delay circuit;
a first step-up level shifter for increasing a voltage level of the first pulse signal from the switch timing control circuit; and
a second step-up level shifter for increasing a voltage level of the second pulse signal from the switch timing control circuit.
8. The voltage conversion circuit as set forth in claim 6, wherein the pulse signal generating circuit includes:
a reference pulse signal generating circuit for generating a reference pulse signal in accordance with the output voltage from the smoothing circuit;
a delay circuit for delaying the reference pulse signal, which has been inputted, for the predetermined period; and
a delay time control circuit for setting a delay time of the delay circuit,
said voltage conversion circuit further comprising:
a switch timing control circuit for generating the first and second pulse signals in accordance with an output pulse signal of the delay circuit;
a first step-up level shifter for increasing a voltage level of the first pulse signal from the switch timing control circuit; and
a second step-up level shifter for increasing a voltage level of the second pulse signal from the switch timing control circuit.
9. A semiconductor integrated circuit device, comprising a voltage conversion circuit including:
a switch circuit arranged so that a series circuit of a P-type transistor and an N-type transistor is provided in series between a pair of power source lines;
a smoothing circuit for smoothing an output voltage derived from a junction of the P-type transistor and the N-type transistor of the switch circuit;
a pulse signal generating circuit for generating one or more pulse signals, each of which has a duty ratio for obtaining a desired output voltage, by using the output voltage smoothed by the smoothing circuit as a power source, so as to give the pulse signal to a control terminal of the P-type transistor and a control terminal of the N-type transistor; and
a start-up control signal for generating a control signal which forces the P-type transistor to turn ON and giving the control signal to the control terminal of the P-type transistor during a predetermined period on start-up.
10. The semiconductor integrated circuit device as set forth in claim 9, wherein the start-up control circuit includes:
a start-up signal generating circuit for generating a start-up signal which has a predetermined voltage level during the predetermined period on start-up; and
a switch control circuit, receiving the start-up signal and the pulse signal from the pulse signal generating circuit, which outputs a control signal whose voltage level causes the P-type transistor turn ON when the start-up signal has the predetermined voltage level, and outputs the pulse signal from the pulse signal generating circuit when the start-up signal does not have the predetermined voltage level.
11. The semiconductor integrated circuit device as set forth in claim 9, wherein the pulse signal generating circuit includes:
a reference pulse signal generating circuit for generating a reference pulse signal in accordance with the output voltage from the smoothing circuit;
a delay circuit for delaying the reference pulse signal, which has been inputted, for the predetermined period; and
a delay time control circuit for setting a delay time of the delay circuit,
said voltage conversion circuit further comprising a step-up level shifter for increasing a voltage level of an output pulse signal of the delay circuit.
12. The semiconductor integrated circuit device as set forth in claim 10, wherein the pulse signal generating circuit includes:
a reference pulse signal generating circuit for generating a reference pulse signal in accordance with the output voltage from the smoothing circuit;
a delay circuit for delaying the reference pulse signal, which has been inputted, for the predetermined period; and
a delay time control circuit for setting a delay time of the delay circuit,
said voltage conversion circuit further comprising a step-up level shifter for increasing a voltage level of an output pulse signal of the delay circuit.
13. The semiconductor integrated circuit device as set forth in claim 9, wherein the start-up control circuit generates the control signal as a first control signal and also generates a second control signal for forcing the N-type transistor to turn OFF so as to give the second control signal to the control terminal of the N-type transistor during the predetermined period on start-up.
14. The semiconductor integrated circuit device as set forth in claim 13, wherein the pulse signal generating circuit includes:
a start-up signal generating circuit for generating a start-up signal having a predetermined voltage level during the predetermined period on start-up;
a first switch control circuit, receiving the start-up signal and one of the pulse signals from the pulse signal generating circuit as a first pulse signal for the P-type transistor, which outputs a first control signal whose voltage level causes the P-type transistor turn ON when the start-up signal has the predetermined voltage level, and outputs the first pulse signal from the pulse signal generating circuit when the start-up signal does not have the predetermined voltage level; and
a second switch control circuit, receiving the start-up signal and another of the pulse signals from the pulse signal generating circuit as a second pulse signal for the N-type transistor, which outputs a second control signal whose voltage level causes the N-type transistor turn ON when the start-up signal has the predetermined voltage level, and outputs the second pulse signal from the pulse signal generating circuit when the start-up signal does not have the predetermined voltage level.
15. The semiconductor integrated circuit device as set forth in claim 13, wherein the pulse signal generating circuit includes:
a reference pulse signal generating circuit for generating a reference pulse signal in accordance with the output voltage from the smoothing circuit;
a delay circuit for delaying the reference pulse signal, which has been inputted, for the predetermined period; and
a delay time control circuit for setting a delay time of the delay circuit,
said voltage conversion circuit further comprising:
a switch timing control circuit for generating the pulse signals as first and second pulse signals in accordance with an output pulse signal of the delay circuit;
a first step-up level shifter for increasing a voltage level of the first pulse signal from the switch timing control circuit; and
a second step-up level shifter for increasing a voltage level of the second pulse signal from the switch timing control circuit.
16. The semiconductor integrated circuit device as set forth in claim 14, wherein the pulse signal generating circuit includes:
a reference pulse signal generating circuit for generating a reference pulse signal in accordance with the output voltage from the smoothing circuit;
a delay circuit for delaying the reference pulse signal, which has been inputted, for the predetermined period; and
a delay time control circuit for setting a delay time of the delay circuit,
said voltage conversion circuit further comprising:
a switch timing control circuit for generating the first and second pulse signals in accordance with an output pulse signal of the delay circuit;
a first step-up level shifter for increasing a voltage level of the first pulse signal from the switch timing control circuit; and
a second step-up level shifter for increasing a voltage level of the second pulse signal from the switch timing control circuit.
17. The semiconductor integrated circuit device as set forth in claim 9, wherein the voltage conversion circuit is used as a step-down circuit for generating a driving voltage of the semiconductor integrated circuit device in accordance with an external power source voltage.
18. The semiconductor integrated circuit device as set forth in claim 13, wherein the voltage conversion circuit is used as a step-down circuit for generating a driving voltage of the semiconductor integrated circuit device in accordance with an external power source voltage.
19. A portable terminal, comprising the semiconductor integrated circuit device as set forth in claim 9.
20. A portable terminal, comprising the semiconductor integrated circuit device as set forth in claim 13.

1. A method for reducing sensor redundancy in sensor-equipped devices, the method comprising:
identifying, via a master device, at least one device within an area;
querying, via the master device, the at least one device to determine at least one of a device status or application status for the at least one device;
determining, via the master device, a configuration of one or more sensors within the at least one device based at least in part on the querying; and
based at least in part on the determining, configuring, via the master device, the one or more sensors within the at least one device to balance quality of service across the master device and the at least one device.
2. The method of claim 1 wherein the at least one device comprises at least one of a smartphone, a tablet computer, a smart shoe, a smart watch, television, personal computer, or a smart glass.
3. The method of claim 1 wherein configuring the one or more sensors comprises switching a power state of the one or more sensors within the at least one device.
4. The method of claim 1 wherein configuring the one or more sensors comprises configuring one or more data processing attributes of the one or more sensors.
5. The method of claim 4 wherein the one or more data processing attributes comprises at least one of datapath, data accuracy, data format, or data interval.
6. The method of claim 1 wherein the area may be determined by at least one of a predetermined value, a dynamic value, or a determined context associated with the at least one device.
7. The method of claim 1 wherein the determining comprises determining a sensor implementation mapping of the at least one device.
8. The method of claim 1 further comprising time-synchronizing, via the master device, data from the one or more sensors within the at least one device with data from one or more sensors within the master device.
9. The method of claim 1 wherein the configuring is performed upon a predetermined interval or upon a predefined condition.
10. The method of claim 1 further comprising:
receiving, at the master device, a location request;
polling, via the master device, the or more sensors within the at least one device;
in response to the polling, receiving, from the at least one device, a location of the at least one device; and
responding, via the master device, to the location request with the location of the at least one device.
11. An apparatus for reducing sensor redundancy in sensor-equipped devices, the apparatus comprising:
a transceiver configured to send and receive a communication;
memory;
a processor coupled to the transceiver and the memory;
the processor configured to:
identify at least one device within an area;
query, via the transceiver, the at least one device to determine at least one of a device status or application status for the at least one device;
determine a configuration of one or more sensors within the at least one device based at least in part on the querying; and
based at least in part on the determining, configure the one or more sensors within the at least one device to balance quality of service across the apparatus and the at least one device.
12. The apparatus of claim 11 wherein the at least one device comprises at least one of a smartphone, a tablet computer, a smart shoe, a smart watch, television, personal computer, or a smart glass.
13. The apparatus of claim 11 wherein configuring the one or more sensors comprises switching a power state of the one or more sensors within the at least one device.
14. The apparatus of claim 11 wherein configuring the one or more sensors comprises configuring one or more data processing attributes of the one or more sensors.
15. The apparatus of claim 14 wherein the one or more data processing attributes comprises at least one of datapath, data accuracy, data format, or data interval.
16. The apparatus of claim 11 wherein the area may be determined by at least one of a predetermined value, a dynamic value, or a determined context associated with the at least one device.
17. The apparatus of claim 11 wherein the determining comprises determining a sensor implementation mapping of the at least one device.
18. The apparatus of claim 11 wherein the processor is further configured to time-synchronize data from the one or more sensors within the at least one device with data from one or more sensors within the apparatus.
19. The apparatus of claim 11 wherein the configuring is performed upon a predetermined interval or upon a predefined condition.
20. The apparatus of claim 11 wherein the processor is further configured to:
receiving a location request;
poll, via the transceiver, the or more sensors within the at least one device;
in response to the polling, receive via the transceiver, from the at least one device, a location of the at least one device; and
respond to the location request with the location of the at least one device.
21. An apparatus for reducing sensor redundancy in sensor-equipped devices, the apparatus comprising:
means for identifying, via a master device, at least one device within an area;
means for querying, via the master device, the at least one device to determine at least one of a device status or application status for the at least one device;
means for determining, via the master device, a configuration of one or more sensors within the at least one device based at least in part on the querying; and
based at least in part on the determining, means for configuring, via the master device, the one or more sensors within the at least one device to balance quality of service across the master device and the at least one device.
22. The apparatus of claim 21 wherein the means for configuring the one or more sensors comprises means for switching a power state of the one or more sensors within the at least one device.
23. The apparatus of claim 21 wherein the means for configuring the one or more sensors comprises means for configuring one or more data processing attributes of the one or more sensors.
24. The apparatus of claim 21 wherein the means for determining comprises means for determining a sensor implementation mapping of the at least one device.
25. The apparatus of claim 21 further comprising means for time-synchronizing, via the master device, data from the one or more sensors within the at least one device with data from one or more sensors within the master device.
26. A processor-readable non-transitory medium comprising processor readable instructions configured to cause a processor to:
identify at least one device within an area;
query the at least one device to determine at least one of a device status or application status for the at least one device;
determine a configuration of one or more sensors within the at least one device based at least in part on the querying; and
based at least in part on the determining, configure the one or more sensors within the at least one device to balance quality of service across a master device and the at least one device.
27. The processor-readable non-transitory medium of claim 26 wherein configuring the one or more sensors comprises switching a power state of the one or more sensors within the at least one device.
28. The processor-readable non-transitory medium of claim 26 wherein configuring the one or more sensors comprises configuring one or more data processing attributes of the one or more sensors.
29. The processor-readable non-transitory medium of claim 26 wherein the determining comprises determining a sensor implementation mapping of the at least one device.
30. The processor-readable non-transitory medium of claim 26 wherein the processor readable instructions are further configured to cause the processor to time-synchronize, via the master device, data from the one or more sensors within the at least one device with data from one or more sensors within the master device.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A flip-chip packaging process comprising:
providing a chip having thereon at least one metal pad surface;
providing a probe tip comprising a needle body and a stop cylinder having a recess for accommodating the needle body therein, the needle body being electrically connected to the stop cylinder via a resilient conductive material;
laterally moving the needle body of the probe tip to scratch a portion of the metal pad surface so as to form a protruding probe mark thereon;
pressing the protruding probe mark to a predetermined height with the stop cylinder;
forming a under bump metallurgy (UBM) over the metal pad surface; and
forming a bump over the UBM.
2. The flip-chip packaging process of claim 1 wherein the predetermined height is below 2 microns.
3. The flip-chip packaging process of claim 1 wherein the predetermined height is below 1 microns.
4. The flip-chip packaging process of claim 1 wherein the bump is solder bump.
5. The flip-chip packaging process of claim 1 wherein the metal pad is made of aluminum or copper and is formed on a chip.
6. The flip-chip packaging process of claim 1 wherein the needle body protrudes from the bottom of the stop cylinder by at least 1 micron.
7. The flip-chip packaging process of claim 1 wherein the resilient conductive material is conductive glue.
8. The flip-chip packaging process of claim 1 wherein the annual flat bottom has a width of about 20 microns to 30 microns.