All The Claims

What is claimed is:

1. A phase compensation circuit in a digital phase lock loop, comprising:
a first computation unit for computing the absolute value of the real part of a frequency domain signal sample;
a second computation unit for computing the absolute value of the imaginary part of said frequency domain signal sample;
an adder for computing the sum of the absolute value of the real part of said frequency domain signal sample and the absolute value of the imaginary part of said frequency domain signal sample;
a weighting circuit for multiplying the output of said adder with a ratio adjustment factor to generate a weighting factor;
a subtractor for computing the difference between the absolute value of the imaginary part of said frequency domain signal sample and the absolute value of the real part of said frequency domain signal sample to form a phase correction term; and
a multiplier for multiplying said weighting factor with said phase correction term to form a phase compensation value.
2. The phase compensation circuit as claimed in claim 1, wherein the absolute value of the real part of said frequency domain signal sample computed by said first computation unit is a probable value and the absolute value of the imaginary part of said frequency domain signal sample computed by said second computation unit is a probable value.
3. The phase compensation circuit as claimed in claim 1, wherein said phase correction term is computed as the absolute value of the imaginary part of said frequency domain sample signal minus the absolute value of the real part of said frequency domain sample signal if said frequency domain sample signal is located in the first or the third quadrant on a 2-D signal plane, and computed as the absolute value of the real part of said frequency domain sample signal minus the absolute value of the imaginary part of said frequency domain sample signal if said frequency domain sample signal is located in the second or the fourth quadrants on a 2-D signal plane.
4. The phase compensation circuit as claimed in claim 1, wherein said ratio adjustment factor is a value between 0 and 1.
5. The phase compensation circuit as claimed in claim 4, wherein said ratio adjustment factor is 2n and n is a value greater than 0 but smaller than the number of bits required in representing the sum computed by said adder.
6. A differential phase discriminator circuit, comprising:
a differential phase discriminator having a differential phase output;
a phase compensation circuit comprising a first computation unit for computing the absolute value of the real part of a frequency domain signal sample; a second computation unit for computing the absolute value of the imaginary part of said frequency domain signal sample; an adder for computing the sum of the absolute value of the real part of said frequency domain signal sample and the absolute value of the imaginary part of said frequency domain signal sample; a weighting circuit for multiplying the output of said adder with a ratio adjustment factor to generate a weighting factor; a subtractor for computing the difference between the absolute value of the imaginary part of said frequency domain signal sample and the absolute value of the real part of said frequency domain signal sample to form a phase correction term; and a multiplier for multiplying said weighting factor with said phase correction term to form a phase compensation value;
an adder summing said differential phase output and said phase compensation value to obtain a phase corrected discriminator output;
a low pass filter coupled to said adder; and
a voltage controlled oscillator coupled to said low pass filter.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method, comprising:
generating frame synchronization information for at least two air interface standards in a clock;
generating a system frame number for the frame synchronization information;
transferring synchronization bursts containing the frame synchronization information from the clock to processors over a serial bus using time-division multiplexing for synchronization bursts addressed to processors of different air interface standards;
extracting, in at least one processor, the frame synchronization information from a received synchronization burst of a respective air interface; and
changing, in the at least one processor, the frame number at a predetermined offset to a predetermined point of the received synchronization burst,
wherein the generating of the frame synchronization information, the generating of the system frame number, the transferring of the synchronization bursts, and the extracting of the frame synchronization information are performed in a base station.
2. The method of claim 1, further comprising:
utilizing the extracted frame synchronization information for air interface frame synchronization between different processors of at least one air interface standard.
3. The method of claim 1, further comprising:
utilizing the extracted frame synchronization information for bus synchronization between different processors of at least one air interface standard.
4. The method of claim 1, further comprising:
generating, in the at least one processor, independent synchronization information locked to the extracted synchronization information.
5. The method of claim 1, further comprising:
performing a frame synchronization information distribution on demand.
6. The method of claim 1, further comprising:
demanding, by the at least one processor, the frame synchronization information from the clock.
7. The method of claim 6, further comprising:
performing the demanding during a start-up of the processor.
8. The method of claim 1, further comprising:
performing a frame synchronization information distribution during a start-up of a base station.
9. The method of claim 1, further comprising:
performing a frame synchronization information distribution at predetermined time intervals.
10. The method of claim 1, further comprising:
performing a frame synchronization information distribution to the processors by broadcasting or multicasting.
11. The method of claim 1, further comprising:
inserting, in at least one synchronization burst, a start part, a mode part indicating whether the at least one synchronization burst is intended for frame synchronization of a specific air interface standard or for bus synchronization, and an end part.
12. The method of claim 11, further comprising:
inserting, in the at least one synchronization burst, a system frame number.
13. The method of claim 11, further comprising:
inserting, in the at least one synchronization burst, an error detection code.
14. The method of claim 1, further comprising:
generating, for the frame synchronization information, a frame clock.
15. The method of claim 1, further comprising:
providing the processors for at least one air interface standard comprising a radio frequency transceiver and a base band processor.
16. The method of claim 1, further comprising:
providing the processors for at least one air interface standard comprising radio frequency transceiver blocks and base band processing blocks; and
including the radio frequency transceiver blocks and the base band processing blocks in at least one special unit of a base station.
17. The method of claim 1, further comprising: including processors of two different air interface standards in at least one multi-standard unit of a base station.
18. A method, comprising:
generating frame synchronization information for at least two air interface standards in a clock;
generating, for the frame synchronization information, a frame clock;
generating a system frame number for the frame synchronization information;
transferring synchronization bursts containing the frame synchronization information from the clock to processors over a serial bus using time-division multiplexing for synchronization bursts addressed to processors of different air interface standards;
extracting, in at least one processor, the frame synchronization information from a received synchronization burst of a respective air interface standard;
changing, in the processor, the frame number at a predetermined offset to a predetermined point of the received synchronization burst;
distributing, to the processor, a system clock that is phase-locked with the frame clock; and
sampling the serial bus with a sampling rate derived from the system clock,
wherein the generating of the frame synchronization information, the generating of the system frame number, the transferring of the synchronization bursts, and the extracting of the frame synchronization information are performed in a base station.
19. An apparatus, comprising:
a clock configured to generate frame synchronization information for at least two air interface standards, wherein the clock is further configured to generate a system frame number for the frame synchronization information;
processors of different air interface standards, at least one of the processors configured to extract the frame synchronization information from a received synchronization burst of a respective air interface standard and to change the frame number at a predetermined offset to a predetermined point of the received synchronization burst; and
a serial bus configured to connect the clock and the processor, and also configured to transfer the synchronization burst containing the frame synchronization information from the clock to the processor using time-division multiplexing for the synchronization burst addressed to the processors of different air interface standards,
wherein the clock, the processors, and the serial bus are located in a base station.
20. The apparatus of claim 19, wherein:
at least one processor is configured to utilize the extracted frame synchronization information for air interface frame synchronization between different processor of at least one air interface standard.
21. The apparatus of claim 19, wherein:
at least one processor is configured to utilize the extracted frame synchronization information for bus synchronization between different processors of one air interface standard.
22. The apparatus of claim 19, wherein:
at least one processor is configured to generate independent synchronization information locked to the extracted synchronization information.
23. The apparatus of claim 19, wherein:
the clock is configured to perform the frame synchronization information distribution on demand.
24. The apparatus of claim 19, wherein:
at least one processor is configured to demand the frame synchronization information from the clock.
25. The apparatus of claim 24, wherein:
at least one processor is configured to make the demand during a start-up of the at least one processor.
26. The apparatus of claim 19, wherein:
the clock is configured to perform a frame synchronization distribution during a start-up of a base station.
27. The apparatus of claim 19, wherein:
the clock is configured to perform a frame synchronization information distribution at predetermined time intervals.
28. The apparatus of claim 19, wherein:
the clock is configured to perform a frame synchronization information distribution to the processors by broadcasting or multicasting.
29. The apparatus of claim 19, wherein:
the clock is configured to insert, in the synchronization burst, a start part, a mode part indicating whether the synchronization burst in intended for frame synchronization of a certain air interface standard or for bus synchronization, and an end part.
30. The apparatus of claim 29, wherein:
the clock is configured to insert, in the synchronization burst, a system frame number.
31. The apparatus of claim 29, wherein:
the clock is configured to insert, in the synchronization burst, an error detection code.
32. The apparatus of claim 19, wherein:
the clock is configured to generate for the frame synchronization information a frame clock.
33. The apparatus of claim 19, wherein the processors for at least one air interface standard comprise a radio frequency transceiver and a base band processor.
34. The apparatus of claim 19, wherein the processors for at least one air interface standard comprise radio frequency transceiver blocks and base band processing blocks, and the radio frequency transceiver blocks and the base band processing blocks are included in at least one special unit of a base station.
35. The apparatus of claim 19, wherein processors of two different air interface standards are included in one multi-standard unit of a base station.
36. An apparatus, comprising:
a clock configured to generate frame synchronization information for at least two air interface standards, wherein the clock is further configured to generate for the frame synchronization information a frame clock and to generate a system frame number for the frame synchronization information;
processors of different air interface standards, at least one of the processors configured to extract the frame synchronization information from a received synchronization burst of a respective air interface standard and to change the frame number at a predetermined offset to a predetermined point of the received synchronization burst; and
a serial bus configured to connect the clock and the processor, and also configured to transfer the synchronization burst containing the frame synchronization information from the clock to the processor using time-division multiplexing for the synchronization burst addressed to the processors of different air interface standards,
the clock is configured to distribute to the processor a system clock that is phase-locked with the frame clock; and
the processor is configured to sample the serial bus with a sampling rate derived from the system clock,
wherein the clock, the processors, and the serial bus are located in a base station.
37. A system, comprising:
a generator configured to generate frame synchronization information for at least two air interface standards in a clock, to generate a system frame number for the frame synchronization information;
a transmitter configured to transfer synchronization bursts containing the frame synchronization information from the clock to processors over a serial bus using time-division multiplexing for synchronization bursts addressed to processors of different air interface standards; and
an extractor configured to extract, in at least one processor, the frame synchronization information from a received synchronization burst of a respective air interface standard and to change the frame number at a predetermined offset to a predetermined point of the received synchronization burst,
wherein the generator, the transmitter, and the extractor are located in a base station.
38. The system of claim 37, further comprising:
a utilizing unit configured to utilize extracted frame synchronization information for air interface frame synchronization between different processors of at least one air interface standard.
39. The system of claim 37, further comprising:
a utilizing unit configured to utilize the extracted frame synchronization information for bus synchronization between different processors of at least one air interface standard.
40. The system of claim 37, further comprising:
a generator configured to generate in the at least one processor independent synchronization information locked to the extracted synchronization information.
41. An apparatus, comprising:
a clock generating means for generating frame synchronization information for at least two air interface standards and for generating a system frame number for the frame synchronization information;
a plurality of processing means of different air interface standards, at least one of the processing means for extracting the frame synchronization information from a received synchronization burst of a respective air interface standard and for changing the frame number at a predetermined offset to a predetermined point of the received synchronization burst; and
a serial bus means for connecting the clock generating means and the plurality of processing means, and for transferring the synchronization burst containing the frame synchronization information from the clock generating means to the plurality of processing means using time-division multiplexing for the synchronization burst addressed to the plurality of processing means of different air interface standards,
wherein the clock generating means, the plurality of processing means, and the serial bus means are located in a base station.
42. A computer program embodied on a computer-readable medium, the computer program configured to control a processor to perform operations comprising:
generating frame synchronization information for at least two air interface standards in a clock;
generating a system frame number for the frame synchronization information;
transferring synchronization bursts containing the frame synchronization information from the clock to processors over a serial bus using time-division multiplexing for synchronization bursts addressed to processors of different air interface standards;
extracting, in at least one processor, the frame synchronization information from a received synchronization burst of a respective air interface; and
changing, in the at least one processor, the frame number at a predetermined offset to a predetermined point of the received synchronization burst,
wherein the generating of the frame synchronization information, the generating of the system frame number, the transferring of the synchronization bursts, and the extracting of the frame synchronization information are performed in a base station.

1. A shunt switch comprising:
a transmission line,
a ground; and
a shunt line electrically coupling the transmission line and the ground,
wherein two or more of the shunt lines are arranged in parallel to one another, and an impedance between the two or more shunt lines is higher than an impedance of the transmission line.
2. The shunt switch according to claim 1, wherein
the shunt lines are configured of moving electrodes which are displaceable with respect to the transmission line andor the ground.
3. The shunt switch according to claim 2, wherein
the transmission line and a ground line which is set to a ground potential are arranged on a substrate,
a moving section which is formed as one unit with the substrate and is displaceable with respect to the transmission line andor the ground line is included, and two or more of the moving electrodes are arranged separately from one another on the moving section, and
the two or more moving electrodes are insulated from one another by an insulating film arranged on a surface of the moving section.
4. The shunt switch according to claim 3, wherein
the moving section is coupled to a pair of comb electrodes which are engaged with each other, and is displaceable by electrostatic force generated between the pair of comb electrodes.
5. The shunt switch according to claim 4, wherein
the moving section is displaceable in a horizontal direction with respect to a surface of the substrate.
6. The shunt switch according to claim 5, wherein
the transmission line is arranged on a leaf spring formed as one unit with the substrate,
the moving section includes a pushing projection facing a central part of the transmission line, and
the pushing projection is brought into contact with the leaf string in response to displacement of the moving section so as to deform the leaf spring, thereby the central part of the transmission line is brought into contact with the ground line.
7. The shunt switch according to claim 2, wherein
the moving electrodes are displaceable with respect to the transmission line andor the ground by deforming the moving electrodes.
8. The shunt switch according to claim 3, wherein
the moving section is coupled to a moving electrode for electrostatic drive with a flat spring in between, and is displaceable in a vertical direction with respect to a surface of the substrate by electrostatic force generated between the moving electrode for electrostatic drive and the ground line.
9. A semiconductor device comprising a shunt switch,
wherein the shunt switch includes a transmission line, a ground, and a shunt line electrically coupling the transmission line and the ground, and
two or more of the shunt lines are arranged in parallel to one another, and an impedance between the two or more shunt lines is higher than an impedance of the transmission line.
10. A module comprising a semiconductor device which includes a shunt switch,
wherein the shunt switch includes a transmission line, a ground, and a shunt line electrically coupling the transmission line and the ground, and
two or more of the shunt lines are arranged in parallel to one another, and an impedance between the two or more shunt lines is higher than an impedance of the transmission line.
11. An electronic device comprising a semiconductor device which includes a shunt switch,
wherein the shunt switch includes a transmission line, a ground, and a shunt line electrically coupling the transmission line and the ground, and
two or more of the shunt lines are arranged in parallel to one another, and an impedance between the two or more shunt lines is higher than an impedance of the transmission line.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of controlling a display device, comprising:
transmitting a pixel clock signal to the display device during a first state of the display device, wherein the display device is configured to use the pixel clock signal to control refresh of a display of the display device while the display device is in the first state; and
responsive to a determination that the display device has entered a second state, transmitting a heartbeat signal to the display device, the second state being a self-refresh state, wherein the display device is configured to use the heartbeat signal to control refresh of the display while the display device is in the second state.
2. The method of claim 1, further comprising:
detecting a static image; and
switching to the second state responsive to detecting the static image.
3. The method of claim 1, wherein the transmitting comprises:
transmitting the heartbeat signal to the display device over a main link or an auxiliary link.
4. The method of claim 1, further comprising:
responsive to a determination that the display device has entered the second state, activating a supplemental timing generator.
5. A method of operating a display device, comprising:
receiving a pixel clock signal from a display controller while the display device is in a first state, wherein the display device uses the pixel clock signal to control refresh of a display of the display device while the display device is in the first state;
switching the display device to a second state;
receiving a heartbeat signal from the display controller while the display device is in the second state; and
generating a timing signal based on a heartbeat signal, wherein the display device uses the timing signal to control refresh of the display while the display device is in the second state.
6. The method of claim 5, further comprising:
controlling drivers of the display device using the timing signal.
7. The method of claim 6, further comprising:
storing a frame received from the display controller; and
while the display device is in the second state, controlling the drivers to display the frame.
8. The method of claim 5, wherein switching comprises:
switching to the second state in response to a command received from the display controller.
9. The method of claim 5, further comprising:
receiving the heartbeat signal over a main link or an auxiliary link.
10. A display controller, comprising:
a static image detection module; and
a timing module configured to generate a timing signal in a first state of the display controller and a heartbeat signal in a second state of the display controller, wherein the display controller is configured to switch between the first and second states responsive to a signal received from the static image detection module;
wherein the display controller is configured to transmit the timing signal and the heartbeat signal to a display device, wherein the display device is configured to use the timing clock signal to control refresh of a display of the display device while the display controller is in the first state, and wherein the display device is configured to use the heartbeat signal to control refresh of the display while the display controller is in the second state.
11. The display controller of claim 10, wherein the second state is a self-refresh state.
12. The display controller of claim 10, wherein the static image detection module is configured to output the signal at a first value when an image to be displayed has become static over a number of frames.
13. The display controller of claim 10, wherein the timing module comprises:
a timing generator configured to generate the timing signal.
14. The display controller of claim 13, wherein the timing module further comprises:
a supplemental timing generator configured to generate the heartbeat signal, wherein the timing generator is configured to activate the supplemental timing generator when the display controller switches to the second state.
15. The display controller of claim 10, further comprising:
an interface module coupled to the timing module and configured to communicate with the display device over a plurality of lines, the lines comprising a main line and an auxiliary line.
16. The display controller of claim 15, wherein the interface module is configured to receive the heartbeat signal and to send the heartbeat signal to the display device over the auxiliary link.
17. A display device, comprising:
a self-refresh controller configured to control the display device to operate in a first state or a second state, wherein the first state is a self-refresh state;
drivers configured to drive respective pixels of a display of the display device; and
a controller configured to control the drivers based on a heartbeat signal received from a display controller when the display device is in the first state, wherein the drivers are controlled using a pixel clock signal received from the display controller while the display device is in the second state.
18. The display device of claim 17, wherein the controller comprises:
a timing generator configured to generate a timing signal based on the heartbeat signal.
19. The display device of claim 17, wherein the controller comprises:
a frame buffer configured to hold a frame to be displayed while the display device is in the first state.
20. The display device of claim 17, further comprising:
an interface configured to control the drivers with information received from the display controller when the display device operates in the second state, wherein the interface module is configured to receive the heartbeat signal and to transmit the heartbeat signal to the timing controller.
21. The display device of claim 20, wherein the interface is coupled to lines, the lines comprising a main line and an auxiliary line.
22. The display device of claim 21, wherein the interface is configured to receive the heartbeat signal over the main line.
23. A method of operating a display device, comprising:
receiving a pixel clock signal from a display controller during a first state of the display controller, wherein the display device is configured to use the pixel clock signal to control refresh of a display of the display device while the display controller is in the first state;
responsive to a determination that the display controller has entered a second state, transmitting a heartbeat signal to the display controller, wherein the second state is a self-refresh state, wherein the display controller is configured to use the heartbeat signal upon exiting from the second state to synchronize with the display device.
24. The method of claim 23, wherein the transmitting comprises:
transmitting the heartbeat signal to the display controller over an auxiliary link or a hot plug detect.
25. The method of claim 23, further comprising:
generating the heartbeat signal based on a timing signal.
26. The method of claim 25, further comprising:
controlling drivers of the display device using the timing signal.
27. The method of claim 26, further comprising:
storing a frame received from the display controller; and
while the display controller is in the second state, controlling the drivers to display the frame.
28. The method of claim 23, further comprising:
switching to a self-refresh state in response to a command received from the display controller.
29. A display controller, comprising:
a static image detection module configured to control the display controller to operate in a first state and a second state, wherein the second state is a self-refresh state; and
a timing module configured to generate a timing signal based on a heartbeat signal after exiting from the second state, wherein the timing module is configured to receive the heartbeat signal from a display device while the display controller is in the second state, wherein the timing module is configured to generate a pixel clock when the display controller is in the first state, and to transmit the pixel clock to the display device when the display controller is in the first state.
30. The display controller of claim 29, wherein the static image detection module is configured to output a signal at a first value when an image to be displayed has become static over a number of frames.
31. The display controller of claim 29, wherein the timing module comprises:
a timing generator configured to generate the timing signal.
32. The display controller of claim 29, wherein the timing module comprises:
a supplemental timing generator configured to generate the timing signal.
33. The display controller of claim 29, further comprising:
an interface module coupled to the timing module and configured to communicate with the display device over a plurality of lines, the lines comprising a main line and an auxiliary line.
34. A display device, comprising:
a self-refresh controller configured to control the display device to operate in a first state or a second state, wherein the first state is a self-refresh state;
drivers configured to drive respective pixels of the display device; and
a timing controller configured to control the drivers when the display device operates in the first state and to output a heartbeat signal when the display device operates in the first state, wherein the heartbeat signal is configured to be used by a display controller to synchronize the display controller with the display device, wherein the drivers are controlled using a pixel clock signal received from the display controller while the display device is in the second state.
35. The display device of claim 34, wherein the timing controller comprises:
a timing generator configured to generate a timing signal when the display device is in the first state.
36. The display device of claim 34, wherein the timing generator is configured to generate the heartbeat signal based on the timing signal.
37. The display device of claim 34, wherein the timing controller comprises:
a frame buffer configured to hold a frame to be displayed while the display device is in the first state.
38. The display device of claim 34, further comprising:
an interface module that is configured to transmit the heartbeat signal to the display controller using either an auxiliary link or a hot plug detect.