What is claimed is:
1. A phase compensation circuit in a digital phase lock loop, comprising:
a first computation unit for computing the absolute value of the real part of a frequency domain signal sample;
a second computation unit for computing the absolute value of the imaginary part of said frequency domain signal sample;
an adder for computing the sum of the absolute value of the real part of said frequency domain signal sample and the absolute value of the imaginary part of said frequency domain signal sample;
a weighting circuit for multiplying the output of said adder with a ratio adjustment factor to generate a weighting factor;
a subtractor for computing the difference between the absolute value of the imaginary part of said frequency domain signal sample and the absolute value of the real part of said frequency domain signal sample to form a phase correction term; and
a multiplier for multiplying said weighting factor with said phase correction term to form a phase compensation value.
2. The phase compensation circuit as claimed in claim 1, wherein the absolute value of the real part of said frequency domain signal sample computed by said first computation unit is a probable value and the absolute value of the imaginary part of said frequency domain signal sample computed by said second computation unit is a probable value.
3. The phase compensation circuit as claimed in claim 1, wherein said phase correction term is computed as the absolute value of the imaginary part of said frequency domain sample signal minus the absolute value of the real part of said frequency domain sample signal if said frequency domain sample signal is located in the first or the third quadrant on a 2-D signal plane, and computed as the absolute value of the real part of said frequency domain sample signal minus the absolute value of the imaginary part of said frequency domain sample signal if said frequency domain sample signal is located in the second or the fourth quadrants on a 2-D signal plane.
4. The phase compensation circuit as claimed in claim 1, wherein said ratio adjustment factor is a value between 0 and 1.
5. The phase compensation circuit as claimed in claim 4, wherein said ratio adjustment factor is 2n and n is a value greater than 0 but smaller than the number of bits required in representing the sum computed by said adder.
6. A differential phase discriminator circuit, comprising:
a differential phase discriminator having a differential phase output;
a phase compensation circuit comprising a first computation unit for computing the absolute value of the real part of a frequency domain signal sample; a second computation unit for computing the absolute value of the imaginary part of said frequency domain signal sample; an adder for computing the sum of the absolute value of the real part of said frequency domain signal sample and the absolute value of the imaginary part of said frequency domain signal sample; a weighting circuit for multiplying the output of said adder with a ratio adjustment factor to generate a weighting factor; a subtractor for computing the difference between the absolute value of the imaginary part of said frequency domain signal sample and the absolute value of the real part of said frequency domain signal sample to form a phase correction term; and a multiplier for multiplying said weighting factor with said phase correction term to form a phase compensation value;
an adder summing said differential phase output and said phase compensation value to obtain a phase corrected discriminator output;
a low pass filter coupled to said adder; and
a voltage controlled oscillator coupled to said low pass filter.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method, comprising:
generating frame synchronization information for at least two air interface standards in a clock;
generating a system frame number for the frame synchronization information;
transferring synchronization bursts containing the frame synchronization information from the clock to processors over a serial bus using time-division multiplexing for synchronization bursts addressed to processors of different air interface standards;
extracting, in at least one processor, the frame synchronization information from a received synchronization burst of a respective air interface; and
changing, in the at least one processor, the frame number at a predetermined offset to a predetermined point of the received synchronization burst,
wherein the generating of the frame synchronization information, the generating of the system frame number, the transferring of the synchronization bursts, and the extracting of the frame synchronization information are performed in a base station.
2. The method of claim 1, further comprising:
utilizing the extracted frame synchronization information for air interface frame synchronization between different processors of at least one air interface standard.
3. The method of claim 1, further comprising:
utilizing the extracted frame synchronization information for bus synchronization between different processors of at least one air interface standard.
4. The method of claim 1, further comprising:
generating, in the at least one processor, independent synchronization information locked to the extracted synchronization information.
5. The method of claim 1, further comprising:
performing a frame synchronization information distribution on demand.
6. The method of claim 1, further comprising:
demanding, by the at least one processor, the frame synchronization information from the clock.
7. The method of claim 6, further comprising:
performing the demanding during a start-up of the processor.
8. The method of claim 1, further comprising:
performing a frame synchronization information distribution during a start-up of a base station.
9. The method of claim 1, further comprising:
performing a frame synchronization information distribution at predetermined time intervals.
10. The method of claim 1, further comprising:
performing a frame synchronization information distribution to the processors by broadcasting or multicasting.
11. The method of claim 1, further comprising:
inserting, in at least one synchronization burst, a start part, a mode part indicating whether the at least one synchronization burst is intended for frame synchronization of a specific air interface standard or for bus synchronization, and an end part.
12. The method of claim 11, further comprising:
inserting, in the at least one synchronization burst, a system frame number.
13. The method of claim 11, further comprising:
inserting, in the at least one synchronization burst, an error detection code.
14. The method of claim 1, further comprising:
generating, for the frame synchronization information, a frame clock.
15. The method of claim 1, further comprising:
providing the processors for at least one air interface standard comprising a radio frequency transceiver and a base band processor.
16. The method of claim 1, further comprising:
providing the processors for at least one air interface standard comprising radio frequency transceiver blocks and base band processing blocks; and
including the radio frequency transceiver blocks and the base band processing blocks in at least one special unit of a base station.
17. The method of claim 1, further comprising: including processors of two different air interface standards in at least one multi-standard unit of a base station.
18. A method, comprising:
generating frame synchronization information for at least two air interface standards in a clock;
generating, for the frame synchronization information, a frame clock;
generating a system frame number for the frame synchronization information;
transferring synchronization bursts containing the frame synchronization information from the clock to processors over a serial bus using time-division multiplexing for synchronization bursts addressed to processors of different air interface standards;
extracting, in at least one processor, the frame synchronization information from a received synchronization burst of a respective air interface standard;
changing, in the processor, the frame number at a predetermined offset to a predetermined point of the received synchronization burst;
distributing, to the processor, a system clock that is phase-locked with the frame clock; and
sampling the serial bus with a sampling rate derived from the system clock,
wherein the generating of the frame synchronization information, the generating of the system frame number, the transferring of the synchronization bursts, and the extracting of the frame synchronization information are performed in a base station.
19. An apparatus, comprising:
a clock configured to generate frame synchronization information for at least two air interface standards, wherein the clock is further configured to generate a system frame number for the frame synchronization information;
processors of different air interface standards, at least one of the processors configured to extract the frame synchronization information from a received synchronization burst of a respective air interface standard and to change the frame number at a predetermined offset to a predetermined point of the received synchronization burst; and
a serial bus configured to connect the clock and the processor, and also configured to transfer the synchronization burst containing the frame synchronization information from the clock to the processor using time-division multiplexing for the synchronization burst addressed to the processors of different air interface standards,
wherein the clock, the processors, and the serial bus are located in a base station.
20. The apparatus of claim 19, wherein:
at least one processor is configured to utilize the extracted frame synchronization information for air interface frame synchronization between different processor of at least one air interface standard.
21. The apparatus of claim 19, wherein:
at least one processor is configured to utilize the extracted frame synchronization information for bus synchronization between different processors of one air interface standard.
22. The apparatus of claim 19, wherein:
at least one processor is configured to generate independent synchronization information locked to the extracted synchronization information.
23. The apparatus of claim 19, wherein:
the clock is configured to perform the frame synchronization information distribution on demand.
24. The apparatus of claim 19, wherein:
at least one processor is configured to demand the frame synchronization information from the clock.
25. The apparatus of claim 24, wherein:
at least one processor is configured to make the demand during a start-up of the at least one processor.
26. The apparatus of claim 19, wherein:
the clock is configured to perform a frame synchronization distribution during a start-up of a base station.
27. The apparatus of claim 19, wherein:
the clock is configured to perform a frame synchronization information distribution at predetermined time intervals.
28. The apparatus of claim 19, wherein:
the clock is configured to perform a frame synchronization information distribution to the processors by broadcasting or multicasting.
29. The apparatus of claim 19, wherein:
the clock is configured to insert, in the synchronization burst, a start part, a mode part indicating whether the synchronization burst in intended for frame synchronization of a certain air interface standard or for bus synchronization, and an end part.
30. The apparatus of claim 29, wherein:
the clock is configured to insert, in the synchronization burst, a system frame number.
31. The apparatus of claim 29, wherein:
the clock is configured to insert, in the synchronization burst, an error detection code.
32. The apparatus of claim 19, wherein:
the clock is configured to generate for the frame synchronization information a frame clock.
33. The apparatus of claim 19, wherein the processors for at least one air interface standard comprise a radio frequency transceiver and a base band processor.
34. The apparatus of claim 19, wherein the processors for at least one air interface standard comprise radio frequency transceiver blocks and base band processing blocks, and the radio frequency transceiver blocks and the base band processing blocks are included in at least one special unit of a base station.
35. The apparatus of claim 19, wherein processors of two different air interface standards are included in one multi-standard unit of a base station.
36. An apparatus, comprising:
a clock configured to generate frame synchronization information for at least two air interface standards, wherein the clock is further configured to generate for the frame synchronization information a frame clock and to generate a system frame number for the frame synchronization information;
processors of different air interface standards, at least one of the processors configured to extract the frame synchronization information from a received synchronization burst of a respective air interface standard and to change the frame number at a predetermined offset to a predetermined point of the received synchronization burst; and
a serial bus configured to connect the clock and the processor, and also configured to transfer the synchronization burst containing the frame synchronization information from the clock to the processor using time-division multiplexing for the synchronization burst addressed to the processors of different air interface standards,
the clock is configured to distribute to the processor a system clock that is phase-locked with the frame clock; and
the processor is configured to sample the serial bus with a sampling rate derived from the system clock,
wherein the clock, the processors, and the serial bus are located in a base station.
37. A system, comprising:
a generator configured to generate frame synchronization information for at least two air interface standards in a clock, to generate a system frame number for the frame synchronization information;
a transmitter configured to transfer synchronization bursts containing the frame synchronization information from the clock to processors over a serial bus using time-division multiplexing for synchronization bursts addressed to processors of different air interface standards; and
an extractor configured to extract, in at least one processor, the frame synchronization information from a received synchronization burst of a respective air interface standard and to change the frame number at a predetermined offset to a predetermined point of the received synchronization burst,
wherein the generator, the transmitter, and the extractor are located in a base station.
38. The system of claim 37, further comprising:
a utilizing unit configured to utilize extracted frame synchronization information for air interface frame synchronization between different processors of at least one air interface standard.
39. The system of claim 37, further comprising:
a utilizing unit configured to utilize the extracted frame synchronization information for bus synchronization between different processors of at least one air interface standard.
40. The system of claim 37, further comprising:
a generator configured to generate in the at least one processor independent synchronization information locked to the extracted synchronization information.
41. An apparatus, comprising:
a clock generating means for generating frame synchronization information for at least two air interface standards and for generating a system frame number for the frame synchronization information;
a plurality of processing means of different air interface standards, at least one of the processing means for extracting the frame synchronization information from a received synchronization burst of a respective air interface standard and for changing the frame number at a predetermined offset to a predetermined point of the received synchronization burst; and
a serial bus means for connecting the clock generating means and the plurality of processing means, and for transferring the synchronization burst containing the frame synchronization information from the clock generating means to the plurality of processing means using time-division multiplexing for the synchronization burst addressed to the plurality of processing means of different air interface standards,
wherein the clock generating means, the plurality of processing means, and the serial bus means are located in a base station.
42. A computer program embodied on a computer-readable medium, the computer program configured to control a processor to perform operations comprising:
generating frame synchronization information for at least two air interface standards in a clock;
generating a system frame number for the frame synchronization information;
transferring synchronization bursts containing the frame synchronization information from the clock to processors over a serial bus using time-division multiplexing for synchronization bursts addressed to processors of different air interface standards;
extracting, in at least one processor, the frame synchronization information from a received synchronization burst of a respective air interface; and
changing, in the at least one processor, the frame number at a predetermined offset to a predetermined point of the received synchronization burst,
wherein the generating of the frame synchronization information, the generating of the system frame number, the transferring of the synchronization bursts, and the extracting of the frame synchronization information are performed in a base station.