1. An ESD (Electrostatic Discharge) analysis device comprising:
a circuit simulation unit configured to execute a circuit simulation of design data of a semiconductor integrated circuit including a plurality of circuits of a plurality of power supply systems, to calculate potentials in a plurality of current paths between pads of different two of said plurality of power supply systems, when one of an ESD current and an ESD voltage is applied between said pads;
a border cell extraction unit configured to extract border cells from circuits of said different two of the plurality of power supply systems, wherein said circuits are included in said plurality of circuits, said border cells input andor output signals between said circuits; and
a check unit configured to check an ESD tolerance by calculating a potential difference between said border cells, based on said calculated potentials, said extracted border cells.
2. The ESD analysis device according to claim 1, wherein said check unit calculates said potential difference for each pair of said border cells.
3. The ESD analysis device according to claim 1, wherein said circuit simulation unit executes said circuit simulation of each pair of said pads of said different two of said plurality of power supply systems, and
said check unit checks said ESD tolerance by comparing a maximum value of said potential difference with a reference value in said each pair of said pads.
4. The ESD analysis device according to claim 1, wherein said circuit simulation unit executes said circuit simulation of each pair in said plurality of power supply systems, and
said check unit checks said ESD tolerance of said each pair in said plurality of power supply systems.
5. The ESD analysis device according to claim 1, further comprising:
a circuit element extraction unit configured to extract circuit elements of wiring resistances and power protection elements placed between said pads and between one of said pads and one of said border cells based on said design data,
wherein said circuit simulation unit executes said circuit simulation based on said extracted circuit elements.
6. The ESD analysis device according to claim 5, wherein said circuit element extraction unit extracts said circuit elements by assuming said wiring resistances and power protection elements to be resistors.
7. The ESD analysis device according to claim 6, wherein said circuit element extraction unit converts said power protection elements to said resistors based on previously calculated resistivity of said power protection elements and a size of said power protection elements.
8. The ESD analysis device according to claim 1, wherein said border cell extraction unit searches said border cells by an equipotential trace on a power supply wiring between each of cells and a power source in said semiconductor integrated circuit, and said equipotential trace on inputoutput signals between said cells.
9. A computer program product for ESD (Electrostatic Discharge) analysis, embodied on a non-transitory computer-readable medium and comprising code that, when executed, causes a computer to perform the following:
specifying a first pad and a second pad in a design data of a semiconductor integrated circuit which includes:
a first circuit connected to a first power supply wiring and a first common power supply wiring,
a second circuit connected to a second power supply wiring and a second common power supply wiring, and inputting and outputting signals to and from said first circuit,
said first pad connected to said first power supply wiring,
said second pad connected to said second power supply wiring,
a first power protection element placed between said first pad and said first common power supply wiring, and
a second power protection element placed between said second pad and said second common power supply wiring;
executing a circuit simulation of said design data to calculate potentials in a resistor network which indicates a plurality of current paths between said first pad and said second pad, based on said network and one of an ESD current and an ESD voltage applied between said first pad and said second pad;
extracting a first border cell from said first circuit and a second border cell from said second circuit, wherein said first border cell inputs and outputs signals to and from said second border cell;
calculating a potential difference between a potential at a connection portion of said first power supply wiring with said first border cell and a potential at a connection point of said second power supply wiring with said second border cell, based on said calculated potentials, said extracted first and second border cells; and
checking an ESD tolerance based on said calculated potential difference.
10. The computer program product according to claim 9, wherein said specifying step to said calculating step are performed for each pair of said first border cell and said second border cell.
11. The computer program product according to claim 9, wherein said executing step includes: replacing said first and second power protection elements with resistors in advance.
12. The computer program product according to claim 11, wherein said design data of the semiconductor integrated circuit further includes:
a third pad connected to a third power supply wiring, and
a third power protection element placed between said third power supply wiring and one of said first and second common power supply wirings, and
wherein said executing step includes:
replacing said third power protection element with a resistor of which resistance value is higher than that of each of said first and second power protection element in advance.
13. The computer program product according to claim 11, wherein said replacing step includes:
converting said first and second power protection elements to said resistors based on previously calculated resistivity of said first and second power protection elements and a size of said first and second power protection elements.
14. A method of designing a semiconductor device, comprising:
carrying out a logic synthesis process and an automatic layout process to generate a design data of a semiconductor integrated circuit which includes:
a first circuit connected to a first power supply wiring and a first common power supply wiring,
a second circuit connected to a second power supply wiring and a second common power supply wiring, and inputting and outputting signals to and from said first circuit,
a first pad connected to said first power supply wiring,
a second pad connected to said second power supply wiring,
a first power protection element placed between said first pad and said first common power supply wiring, and
a second power protection element placed between said second pad and said second common power supply wiring;
specifying said first pad and said second pad in said design data of the semiconductor integrated circuit;
executing a circuit simulation of said design data to calculate potentials in a resistor network which indicates a plurality of current paths between said first pad and said second pad, based on said network and one of an ESD current and an ESD voltage applied between said first pad and said second pad;
extracting a first border cell from said first circuit and a second border cell from said second circuit, wherein said first border cell inputs and outputs signals to and from said second border cell;
calculating a potential difference between a potential at a connection portion of said first power supply wiring with said first border cell and a potential at a connection point of said second power supply wiring with said second border cell, based on said calculated potentials, said extracted first and second border cells; and
checking, by a computer, an ESD tolerance based on said calculated potential difference.
15. The method of designing a semiconductor device, according to claim 14, wherein said specifying step to said calculating step are performed for each of all pairs of said first border cell and said second border cell.
16. The method of designing a semiconductor device, according to claim 14, wherein said executing step includes:
replacing said first and second power protection elements with resistors in advance.
17. The method of designing a semiconductor device, according to claim 16, wherein said design data of the semiconductor integrated circuit further includes:
a third pad connected to a third power supply wiring, and
a third power protection element placed between said third power supply wiring and one of said first and second common power supply wirings, and
wherein said executing step includes:
replacing said third power protection element with a resistor of which resistance value is higher than that of each of said first and second power protection element in advance.
18. The method of designing a semiconductor device, according to claim 16, wherein said replacing step includes:
converting said first and second power protection elements to said resistors based on previously calculated resistivity of said first and second power protection elements and a size of said first and second power protection elements.
19. The method of designing a semiconductor device, according to claim 16, wherein said carrying out step includes:
performing said specifying step to said checking step based on a design data after routing of power wirings which is generated after routing of power wirings in said automatic layout process.
20. The method of designing a semiconductor device, according to claim 19, wherein said carrying out step includes:
predicting a potential difference between said first border cell and said second border cell in a case where said first and second border cells are placed at respective positions of said first and second circuits by the ESD analysis,
storing positions of said first and second border cells in which said potential difference does not exceed an upper limit of a predetermined potential difference reference as a border cell layout position restriction data, and
placing said first and second border cells based on said border cell layout position restriction data.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A computer program product comprising:
a computer readable storage medium; and
computer usable code stored on the computer readable storage medium, where, if executed by a processor, the computer usable code causes a computer to:
detect a request to acquire a lock associated with a shared resource in a multi-threaded execution environment including a first thread and a second thread;
deny the request if a lock redundancy component that is to include the lock and at least one other lock is satisfied and an execution context component that is to include a function call chain to be associated with the lock and the at least one other lock is satisfied to permit access to the shared resource without acquiring the lock for the shared resource; and
grant the request if one or more of the lock redundancy component is not satisfied and the execution context component is not satisfied to allow access to the shared resource when the lock is acquired based on the grant of the request.
2. The computer program product of claim 1, wherein the lock redundancy component is to include the lock associated with the shared resource and one other lock associated with one other shared resource, wherein the lock associated with the shared resource is to be held by the second thread and the one other lock associated with the one other resource is to be held by the first thread prior to issuance of the request, wherein the first thread is to release the lock associated with the one other shared resource when the first thread no longer accesses the shared resource, and wherein a third thread is to acquire the lock associated with the one other shared resource.
3. The computer program product of claim 2, wherein each function of the function call chain is to utilize at least the one other lock.
4. The computer program product of claim 1, wherein, if executed, the computer usable code causes a computer to:
detect a release of a subject lock by a thread;
determine that a use of the subject lock by the thread is necessary when one or more shared resources are accessed while the subject lock is acquired and while no other locks are acquired, and is apparently unnecessary when the one or more shared resources are accessed while the subject lock is acquired and while other locks are acquired.
5. The computer program product of claim 4, wherein, if executed, the computer usable code causes a computer to:
identify one or more lines of code of the thread that acquire the subject lock; and
determine that the use of the subject lock by the one or more lines of code is one of necessary and apparently unnecessary.
6. The computer program product of claim 1, wherein, if executed, the computer usable code causes a computer to:
detect a request to acquire a subject lock by a thread;
continue a process by the thread without acquiring the subject lock when a use of the subject lock by the thread is determined to be apparently unnecessary and not necessary, wherein the use is necessary when one or more shared resources are accessed while the subject lock is acquired and while no other locks are acquired, and is apparently unnecessary when the one or more shared resources are accessed while the subject lock is acquired and while other locks are acquired.
7. The computer program product of claim 6, wherein, if executed, the computer usable code causes a computer to:
identify one or more lines of code of the thread that request to acquire the subject lock; and
continue the process by the one or more lines of code without acquiring the subject lock based on a determination that the use of the subject lock by the one or more lines of code is apparently unnecessary and is not necessary.
8. The computer program product of claim 6, wherein, if executed, the computer usable code causes a computer to:
determine that another thread has not acquired the subject lock;
grant the request to allow access to the shared resource by the thread when the subject lock is acquired by the thread based on a determination that the use of the subject lock by the thread is not apparently unnecessary and is necessary; and
track that the acquisition of the lock by the thread has not yet caused a task switch.
9. The computer program product of claim 6, wherein, if executed, the computer usable code causes a computer to:
determine that another thread has acquired the lock;
grant the request to allow access to the shared resource by the thread when the subject lock is acquired by the thread based on a determination that the use of the subject lock by the thread is not apparently unnecessary and is necessary; and
track that the acquisition of the lock by the thread is to cause a task switch.
10. A method comprising:
detecting a request to acquire a lock associated with a shared resource in a multi-threaded execution environment including a first thread and a second thread;
denying the request if a lock redundancy component that includes the lock and at least one other lock is satisfied and an execution context component that includes a function call chain associated with the lock and the at least one other lock is satisfied to permit access to the shared resource without acquiring the lock for the shared resource; and
granting the request if one or more of the lock redundancy component is not satisfied and the execution context component is not satisfied to allow access to the shared resource when the lock is acquired based on the grant of the request.
11. The method of claim 10, wherein the lock redundancy component includes the lock associated with the shared resource and one other lock associated with one other shared resource, wherein the lock associated with the shared resource is held by the second thread and the one other lock associated with the one other resource is held by the first thread prior to issuance of the request, wherein the first thread releases the lock associated with the one other shared resource when the first thread no longer accesses the shared resource, and wherein a third thread acquires the lock associated with the one other shared resource.
12. The method of claim 11, wherein each function of the function call chain utilizes at least the one other lock.
13. The method of claim 10, further including:
detecting a release of a subject lock by a thread;
determining that a use of the subject lock by the thread is necessary when one or more shared resources are accessed while the subject lock is acquired and while no other locks are acquired, and is apparently unnecessary when the one or more shared resources are accessed while the subject lock is acquired and while other locks are acquired.
14. The method of claim 13, further including:
identifying one or more lines of code of the thread that acquire the subject lock; and
determining that the use of the subject lock by the one or more lines of code is one of necessary and apparently unnecessary.
15. The method of claim 10, further including:
detecting a request to acquire a subject lock by a thread;
continuing a process by the thread without acquiring the subject lock when a use of the subject lock by the thread is determined to be apparently unnecessary and not necessary, wherein the use is necessary when one or more shared resources are accessed while the subject lock is acquired and while no other locks are acquired, and is apparently unnecessary when the one or more shared resources are accessed while the subject lock is acquired and while other locks are acquired.
16. The method of claim 15, further including:
identifying one or more lines of code of the thread that request to acquire the subject lock; and
continuing the process by the one or more lines of code without acquiring the subject lock based on a determination that the use of the subject lock by the one or more lines of code is apparently unnecessary and is not necessary.
17. The method of claim 15, further including:
determining that another thread has not acquired the subject lock;
granting the request to allow access to the shared resource by the thread when the subject lock is acquired by the thread based on a determination that the use of the subject lock by the thread is not apparently unnecessary and is necessary; and
tracking that the acquisition of the lock by the thread has not yet caused a task switch.
18. The method of claim 15, further including:
determining that another thread has acquired the lock;
granting the request to allow access to the shared resource by the thread when the subject lock is acquired by the thread based on a determination that the use of the subject lock by the thread is not apparently unnecessary and is necessary; and
tracking that the acquisition of the lock by the thread is to cause a task switch.