All The Claims

1. A bipolar plate for PEM fuel cells comprising a plastic structure having a surface zone including gas-transport channels, the plastic structure comprising a polymer blend which is filled with conductivity-enhancing carbon fillers and which includes at least two mutually nonmiscible blend polymers,
wherein the polymer blend includes at least one polyamide and at least one polyether ketone or polyether sulfone as blend polymers,
wherein the at least two blend polymers form a co-continuous structure and the carbon fillers are at a higher concentration in one of the blend polymers or in the phase between the blend polymers, or wherein a blend polymer in which the carbon fillers are at a higher concentration forms a continuously conductive matrix in which the at least one further blend polymer is intercalated,
wherein the polymer blend comprises from 45 to 85 wt % of blend polymers and from 15 to 65 wt % of carbon fillers, and
wherein the polymer blend contains as carbon fillers
from 1 to 30 wt % of conductive black,
from 5 to 60 wt % of carbon fibers, and
from 1 to 25 wt % of carbon nanotubes,
in each case based on the total weight of the polymer blend, and

the weight ratio, in the polymer blend, of polyamide to polyether ketonepolyether sulfone is from 1:1.6 to 4:1.
2. The bipolar plate as claimed in claim 1, wherein the carbon fillers are selected from conductive black, graphite, carbon fibers, carbon nanotubes and mixtures thereof.
3. A method of fabricating bipolar plates as claimed in claim 1 by preparing and shaping the polymer blend filled with conductivity-enhancing carbon fillers.
4. A PEM fuel cell comprising bipolar plates as claimed in claim 1.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A memory device comprising:
a substrate;
a data storage medium on the substrate; and
machine readable data stored in the data storage medium, the machine readable data having a first readability, the readability of at least a portion of the machine readable data modifiable by a limited expected lifetime so that following modification of readability, the modified portion of machine readable data has a second readability; and
wherein data having the first readability is readable by a first type of data read system and wherein data having the second readability is not readable by the first type of data read system.
2. The memory device of claim 1, wherein data having the second readability is readable by a second type of data read system.
3. (canceled)
4. (canceled)
5. (canceled)
6. (canceled)
7. (canceled)
8. (canceled)
9. The memory device of claim 1, wherein readability of at least one first portion of the machine readable data is modifiable by the limited expected lifetime, wherein readability of at least one second portion of the machine readable data is not modifiable by the limited expected lifetime, and wherein the at least one first portion contains read-support information needed for reading data of interest in the at least one second portion.
10. (canceled)
11. (canceled)
12. (canceled)
13. (canceled)
14. (canceled)
15. (canceled)
16. The memory device of claim 9, wherein machine readable data in the at least one first portion having the second readability is substantially unreadable, and wherein additional read-support information is stored in the at least one second portion and retrievable with a special purpose read system.
17. (canceled)
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45. A memory device comprising:
a data storage medium; and
machine readable data stored in the data storage medium, at least at least one first portion of the machine readable data having a limited expected lifetime after an initial read of data, during which the machine readable data can be read from the data storage medium by a first type of data read system, and following which the readability of the at least one first portion of the machine readable data is modified so that it is unreadable by the first type of data read system.
46. The memory device of claim 45, wherein following the limited expected lifetime, the at least one first portion of the machine readable data is readable by a second type of data read system
47. (canceled)
48. (canceled)
49. (canceled)
50. (canceled)
51. (canceled)
52. (canceled)
53. The memory device of claim 45, wherein the at least one first portion of the machine readable data contains read-support information necessary for reading data of interest in at least one second portion of machine readable data.
54. The memory device of claim 53, wherein the read-support information includes at least a portion of a decryption key.
55. (canceled)
56. (canceled)
57. (canceled)
58. The memory device of claim 53, wherein the at least one second portion includes additional read-support information needed for reading data of interest in the at least one second portion.
59. (canceled)
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69. A data storage device comprising:
a data storage medium capable of having machine readable data stored therein, the data storage medium capable of producing a data signal in a data read device in response to an interrogation activity by the data read device, the data storage medium including:
at least one modifiable portion capable of producing a data signal within a first signal range at the start of a limited read period characterized by a limited expected lifetime or limited temporal duration, and modifiable to produce a read signal falling within a second signal range subsequent to the limited read period.
70. The data storage device of claim 69, wherein a data signal within the first signal range is readable by a general purpose read device and wherein a data signal within the second signal range is readable by a special purpose read device but not by a general purpose read device.
71. (canceled)
72. (canceled)
73. (canceled)
74. (canceled)
75. The memory device of claim 1, wherein machine readable data having the second readability has at least one of a reduced signal-to-noise ratio relative, an increased bit error rate, or a reduced redundancy relative to machine readable data having the first readability.
76. The memory device of claim 1, wherein the limited expected lifetime is defined by at least one of a limited number of readings of the machine readable data from the memory device, a limited number of uses of the memory device, or a limited time interval following an initial use of the device.
77. The memory device of claim 9, wherein machine readable data in the at least one first portion having the second readability has at least one of a reduced signal-to-noise ratio, an increased bit error rate or a reduced redundancy relative to machine readable data having the first readability.
78. The memory device of claim 9, wherein the read-support information includes at least one of a decryption key or index information.
79. The memory device of claim 16, wherein the data storage medium is an optical data storage medium, and wherein the additional read-support information is stored in at least one of the optical data storage medium at a different optical wavelength than the data of interest, the optical data storage medium at a different spatial frequency than the data of interest, a magnetic data storage medium included in the memory device, at least one resonant circuit included in the memory device, at least one RFID included in the memory device, or a bar code on the memory device.
80. The memory device of claim 16, wherein the data storage medium is a magnetic data storage medium, and wherein the additional read-support information is stored at least one of in the magnetic data storage medium at a different spatial frequency than the data of interest, an optical data storage medium included in the memory device, at least one resonant circuit included in the memory device, at least one RFID included in the memory device, or a bar code on the memory device.
81. The memory device of claim 16, wherein the additional read-support information is retrievable by a special purpose read system including one or more of special purpose software or special purpose hardware.
82. The memory device of claim 16, wherein the additional read-support information includes at least one copy of at least a portion of the read-support information in the at least one first portion.
83. The memory device of claim 16, wherein the additional read-support information is stored in the at least one second portion in encrypted form or distributed among multiple locations in the at least one second portion.
84. The memory device of claim 83, wherein the additional read-support information is encrypted by at least one of public key encryption method, a private key encryption method, a Diff-Hellman encryption method, an RSA encryption method, an EIGaml encryption method, a DSS encryption method, an Elliptic curve encryption method, a Paillier cryptosystem encryption method, a Password-authenticated Key agreement encryption method, or a DES encryption method.
85. The memory device of claim 1, wherein readability of the machine readable data is modifiable through one or more of degradation of the data storage medium, degradation of the substrate, or erasure or writing over of at least a portion of the machine readable data.
86. The memory device of claim 46, wherein during the limited expected lifetime, the at least one first portion of the machine readable data is readable by an optical data read system or a magnetic data read system.
87. The memory device of claim 86, wherein following the limited expected lifetime, the at least one first portion of the machine readable data is readable by an optical data read system operating at a reduced scan speed relative to a general purpose optical data read system or an optical data read system performing signal averaging on the data signal.
88. The memory device of claim 86, wherein following the limited expected lifetime, the at least one first portion of the machine readable data is readable by a magnetic data read system operating at a reduced scan speed relative to a general purpose magnetic data read system or a magnetic data read system performing signal averaging on the data signal.
89. The memory device of claim 54, wherein the decryption key is a private key or a public key.
90. The memory device of claim 53, wherein one or more copies of the read-support information are stored on the memory device in a form retrievable from the at least one first portion through the use of special purpose software or special purpose hardware.
91. The memory device of claim 90, wherein the special purpose software includes a function, a HASH function, a table lookup function, or a decryption algorithm.
92. The data storage device of claim 69, wherein data signals within the first signal range are characterized by a first signal-to-noise ratio or first bit data error rate and data signals within the second signal range are characterized by a second signal-to-noise ratio or second bit data error rate.
93. The data storage device of claim 69, including a data storage medium capable of producing a data signal in at least one of an optical data read device or a magnetic data read device.

1. A method of modifying an operation of an integrated circuit device, comprising:
identifying a first type of integrated circuit element, a second type of integrated circuit element and a third type of integrated circuit element, wherein operational characteristics of the first type of integrated circuit element are to be modified, operational characteristics of the third type of integrated circuit element are to be modified, and operational characteristics of the second type of integrated circuit element are to remain constant;
depositing a first stress inducing film on the first, second and third type of integrated circuit element;
applying a first masking layer to the first and second type of integrated circuit elements;
stripping the first stress inducing film from the third type of integrated circuit element, wherein the first masking layer is applied prior to stripping the first stress inducing film from the third type of integrated circuit element and wherein the first stress inducing film applies a first stress to the first type of integrated circuit element to thereby change an operational characteristic of the first type of integrated circuit element; and
depositing a second stress inducing film on the third type of integrated circuit element, wherein the second stress inducing film induces a second stress to the third type of integrated circuit element to thereby change an operational characteristic of the third type of integrated circuit element.
2. The method of claim 1, wherein the first type of integrated circuit element is a nFET device whose operation is to be modified, the second type of integrated circuit element is a pFET device whose operation is not to be modified, and the third type of integrated circuit element is a pFET device whose operation is to be modified.
3. The method of claim 1, further comprising:
relaxing a surface of the second type of integrated circuit element so as to relax the first stress applied to the second type of integrated circuit element, wherein the relaxing of the first stress applied to the second type of integrated circuit element causes the operational characteristics of the second type of integrated circuit element to be substantially unchanged.
4. The method of claim 3, wherein the surface of the second type of integrated circuit element is relaxed by performing ion implantation.
5. The method of claim 1, wherein the first stress inducing film is a compressive stress inducing film and the second stress inducing film is a tensile stress inducing film.
6. The method of claim 1, wherein the first masking layer is a combination of a first mask associated with the first type of integrated circuit element and a second mask associated with the second type of integrated circuit element.
7. The method of claim 1, further comprising:
applying the second stress inducing film to the first, second and third type of integrated circuit elements; and
stripping the first masking layer and the second stress inducing film from the first and second type of integrated circuit elements.
8. The method of claim 3, wherein relaxing the surface of the second type of integrated circuit element comprises:
masking the first type of integrated circuit element using a first mask;
masking the third type of integrated circuit element using a second mask; and
performing ion implantation to the second type of integrated circuit device based on the design masking layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A piezoelectric resonator device, in which a package having an internal space is made up of a base and a lid, and a piezoelectric resonator plate is held on the base inside the internal space, wherein an +X axial direction of the piezoelectric resonator plate in the internal space is set and wherein the piezoelectric resonator plate is made up of a base component and a plurality of leg components that protrude from the base component, excitation electrodes having different potential are formed on the leg components, lead electrodes that are drawn from the excitation electrodes in order to electrically connect the excitation electrodes with external electrodes at the base component are formed on the base component and the leg components, and a groove is formed in a front main face of the base component from at least one side face in the .+\u2212.X axial directions, wherein no grooves are formed in the rear main face.
2. The piezoelectric resonator device according to claim 1, wherein the piezoelectric resonator plate is provided with an identification portion visible from a plan view perspective for identifying the +X axial direction.
3. The piezoelectric resonator device according to claim 2, wherein the piezoelectric resonator plate is made up of a base component and a plurality of leg components that protrude from the base component, and the identification portion is provided to protruding ends of the leg components.
4. The piezoelectric resonator device according to claim 3, wherein the protruding ends each include a protruding end face and .+\u2212.X axial side faces, and the identification portion is a slit formed extending from the protruding end face to the -X axial side face.
5. The piezoelectric resonator device according to claim 1, wherein a plurality of the grooves are formed in the front main face of the base component in the .+\u2212.Y axial directions.
6. The piezoelectric resonator device according to claim 5, wherein the length of at least one of the grooves in the .+\u2212.X axial directions is greater than the length in the .+\u2212.X axial directions of the other grooves adjacent on the .+\u2212.Y axial direction sides.
7. The piezoelectric resonator device according to claim 1, wherein the lead electrodes and external electrodes are electrically connected at opposing locations on a rear main face of the base component across from the locations where the grooves are formed in the front main face.
8. The piezoelectric resonator device according to claim 2, wherein the piezoelectric resonator plate is made up of a base component and a plurality of leg components that protrude from the base component, excitation electrodes having different potential are formed on the leg components, lead electrodes that are drawn from the excitation electrodes in order to electrically connect the excitation electrodes with external electrodes at the base component are formed on the base component and the leg components, and a groove is formed in a front main face of the base component from at least one side face in the .+\u2212.X axial directions.
9. The piezoelectric resonator device according to claim 3, wherein the piezoelectric resonator plate is made up of a base component and a plurality of leg components that protrude from the base component, excitation electrodes having different potential are formed on the leg components, lead electrodes that are drawn from the excitation electrodes in order to electrically connect the excitation electrodes with external electrodes at the base component are formed on the base component and the leg components, and a groove is formed in a front main face of the base component from at least one side face in the .+\u2212.X axial directions.
10. The piezoelectric resonator device according to claim 4, wherein the piezoelectric resonator plate is made up of a base component and a plurality of leg components that protrude from the base component, excitation electrodes having different potential are formed on the leg components, lead electrodes that are drawn from the excitation electrodes in order to electrically connect the excitation electrodes with external electrodes at the base component are formed on the base component and the leg components, and a groove is formed in a front main face of the base component from at least one side face in the .+\u2212.X axial directions.
11. The piezoelectric resonator device according to claim 5, wherein the lead electrodes and external electrodes are electrically connected at opposing locations on a rear main face of the base component across from the locations where the grooves are formed in the front main face.
12. The piezoelectric resonator device according to claim 6, wherein the lead electrodes and external electrodes are electrically connected at opposing locations on a rear main face of the base component across from the locations where the grooves are formed in the front main face.
13. The piezoelectric resonator device according to claim 8, wherein the lead electrodes and external electrodes are electrically connected at opposing locations on a rear main face of the base component across from the locations where the grooves are formed in the front main face.
14. The piezoelectric resonator device according to claim 9, wherein the lead electrodes and external electrodes are electrically connected at opposing locations on a rear main face of the base component across from the locations where the grooves are formed in the front main face.
15. The piezoelectric resonator device according to claim 10, wherein the lead electrodes and external electrodes are electrically connected at opposing locations on a rear main face of the base component across from the locations where the grooves are formed in the front main face.
16. The piezoelectric resonator device according to claim 8, wherein a plurality of the grooves are formed in the front main face of the base component in the .+\u2212.Y axial directions.
17. The piezoelectric resonator device according to claim 9, wherein a plurality of the grooves are formed in the front main face of the base component in the .+\u2212.Y axial directions.