All The Claims

1. A housing assembly, comprising:
a primary housing, having a first external contour and an opening formed on the primary housing;
a secondary housing, having a second external contour; and
a moving mechanism, connecting the secondary housing to the primary housing so that the secondary housing is adapted to move between a sheltering position and an open position, relative to the primary housing; wherein when the secondary housing moves to the open position, the primary housing defines a space with the secondary housing and when the secondary housing moves to the sheltering position, the secondary housing is adapted to at least partially cover the opening, and wherein the first external contour and the second external contour are in combination to form a third external contour.
2. The housing assembly of claim 1, wherein the primary housing includes a side wall, the opening is disposed on the side wall, and the secondary housing is adapted to completely cover the opening when the secondary housing is located in the sheltering position.
3. The housing assembly of claim 1, wherein the primary housing includes a top, the opening is formed on the top, and the secondary housing is adapted to completely cover the opening when the secondary housing is located in the sheltering position.
4. The housing assembly of claim 1, wherein the primary housing further comprises another opening and the housing assembly further comprises another secondary housing, and wherein the primary housing includes two opposite side walls on which the two openings are formed, respectively, and the two secondary housings are adapted to completely cover the two openings, respectively, when both of the secondary housings are located in their respective sheltering positions.
5. The housing assembly of claim 1, wherein the primary housing further comprises another opening and the housing assembly further comprises another secondary housing, and wherein the primary housing includes a side wall and a top, the two openings are formed on the side wall and the top, respectively, and the two secondary housings are adapted to completely cover the two openings, respectively, when the secondary housings are located in their respective sheltering positions.
6. The housing assembly of claim 1, wherein the moving mechanism is a pivoting mechanism, disposed on a side edge of the secondary housing so that the secondary housing is adapted to move pivotally between the sheltering position and the open position.
7. The housing assembly of claim 1, wherein the moving mechanism is a linkage mechanism, disposed on a side edge of the secondary housing so that the secondary housing is adapted to shift in a linear displacement between the sheltering position and the open position.
8. The housing assembly of claim 1, wherein the moving mechanism electrically moves the secondary housing.
9. The housing assembly of claim 1, wherein the moving mechanism manually moves the secondary housing.
10. The housing assembly of claim 1, wherein the first external contour is substantially the same as the third external contour.
11. The housing assembly of claim 1, wherein the first external contour is substantially different from the third external contour.
12. A projection device, comprising:
a housing assembly, including:
a primary housing, having an opening formed on the primary housing;
a secondary housing, adapted to at least partially cover the opening when the secondary housing is located in a sheltering position; and
a moving mechanism, connecting the secondary housing to the primary housing so that the secondary housing is adapted to move between the sheltering position and an open position, relative to the primary housing; wherein when the secondary housing moves to the open position, the primary housing defines a space with the secondary housing; and

a cooling assembly, disposed in the primary housing, adapted to dissipate heat generated by the projection device outward through the opening and the space.
13. The projection device of claim 12, further comprising a light source disposed within the primary housing, wherein the secondary housing is adapted to block scattered light emitted from the light source via the opening when the secondary housing is located in the open position.
14. The projection device of claim 12, wherein the primary housing has a first external contour and the secondary housing has a second external contour, and wherein the first external contour and the second external contour are in combination to form a third external contour when the secondary housing is located in the sheltering position.
15. The projection device of claim 12, wherein the primary housing includes a side wall, the opening is disposed on the side wall, and the secondary housing is adapted to completely cover the opening.
16. The projection device of claim 12, wherein the primary housing includes a top, the opening is formed on the top, and the secondary housing is adapted to completely cover the opening.
17. The projection device of claim 12, wherein the primary housing further comprises another opening and the housing assembly further comprises another secondary housing, and wherein the primary housing includes two opposite side walls on which, the two openings are formed respectively, and the two secondary housing are adapted to completely cover the openings.
18. The projection device of claim 12, wherein the primary housing further comprises another opening and the housing assembly further comprises another secondary housing, and wherein the primary housing includes a side wall and a top, the two openings are formed on the side wall and the top, respectively, and the two secondary housing are located in their respective sheltering positions.
19. The projection device of claim 12, wherein the moving mechanism is a pivoting mechanism, disposed on a side edge of the secondary housing so that the secondary housing is adapted to move pivotally between the sheltering position and the open position.
20. The projection device of claim 12, wherein the moving mechanism is a linkage mechanism, disposed on a side edge of the secondary housing so that the secondary housing is adapted to shift in a linear displacement between the sheltering position and the open position.
21. The projection device of claim 12, wherein the moving mechanism electrically moves the secondary housing.
22. The projection device of claim 12, wherein the moving mechanism manually moves the secondary housing.
23. The projection device of claim 12, wherein the first external contour is substantially the same as the third external contour.
24. The projection device of claim 12, wherein the first external contour is substantially different from the third external contour.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A process comprising:
in response to requests from a manager for connections to applications executing on servers, authenticating of said manager by agents executing on said servers;
in response to said authenticating, establishing connections to said applications by said agents; and
in response to said establishing, providing by said agents to said manager said connections to said applications.
2. A process as recited in claim 1 wherein said authentication involves using a same certificate by plural agents.
3. A process as recited in claim 1 further comprising:
said servers authenticating said manager; and
in response to said authenticating, said manager installing said agents on said servers.
4. A process as recited in claim 3 further comprising said agents listening for said manager on specified virtual ports and not on other virtual ports.
5. A process as recited in claim 1 further comprising said manager updating said applications using said connections.
6. A system comprising storage media encoded with code that, when executed by a processor, implements an agent, said agent including:
a manager interface to interface with a remote manager to receive or fulfill a request by said manager for access to an application executing on a same server as said agent, said manager interface including an authenticator for authenticating said manager; and
an application interface to provide a connection between said agent and said application so that said manager interface can provide a connection between said manager and said application.
7. A system as recited in claim 6 further comprising said processor.
8. A system as recited in claim 6 wherein said code further implements said application, said application including a user authenticator for authenticating a user requesting access to said application, said agent being configured to bypass said user authenticator.
9. A system as recited in claim 6 wherein said code further implements an operating system executing on said server, said operating system including an authenticator to authenticate said manager for the purpose of installing said agent.
10. A system as recited in claim 6 wherein said code further implements plural additional agents, each of said agents having an authenticator relying on a common certificate to authorize said manager.
11. A system comprising storage media encoded with code that, when executed, causes a processor to:
respond to a manager request for a connection to an application executing on a server by authenticating of said manager;
establish a connection to said application; and
provide said connection to said manager.
12. A system as recited in claim 11 further comprising said processor.
13. A system as recited in claim 11 wherein said connection enables said manager to update said application.
14. A system as recited in claim 11 wherein said authenticating involves using a certificate.
15. A system as recited in claim 11 wherein said code further causes said processor to:
authenticate said manager using an operating system; and
installing said agent on said server.

1. A method for line speed interconnect processing, comprising:
receiving initial inputs from an input communications path;
performing a pre-sorting of the initial inputs by using a first stage interconnect parallel processor to create intermediate inputs;
performing the final combining and splitting of the intermediate inputs by using a second stage interconnect parallel processor to create resulting outputs; and
transmitting the resulting outputs out of the second stage at line speed.
2. The method of claim 1, wherein the first stage interconnect processor functions by performing a presorting and pre-clustering process on the initial inputs in parallel to identify candidates among the initial inputs to be checked for pairing.
3. The method of claim 1, wherein the second stage interconnect processor functions by performing position shuffling, pairing, and splitting of the intermediate inputs in parallel to create the resulting outputs at line speed.
4. The method of claim 1, wherein the line speed interconnect processing is implemented in a networking architecture, wherein the initial inputs comprise networking packets.
5. The method of claim 1, wherein the line speed interconnect processing is implemented in a cache accessing architecture, wherein the initial inputs comprise access requests to data of cache lines.
6. The method of claim 1, wherein the line speed interconnect processing is implemented in an arbitration architecture, wherein the initial inputs comprise streams that utilize output bandwidth, and wherein the arbitration architecture arbitrates amongst the input streams using frequency andor time multiplexing in parallel to create resulting output streams.
7. The method of claim 1, wherein the line speed interconnect processing is implemented in a computer instruction architecture decoder, wherein the initial inputs comprise computer instructions that will be combined or split in parallel into machine instructions.
8. The method of claim 1, wherein the line speed interconnect processing is implemented in a DRAM accessing architecture, wherein the initial inputs comprise accesses to DRAM pages that will be paired or split in parallel into optimized resulting accesses to DRAM pages.
9. A non-transitory computer readable memory having computer readable code which when executed by a computer system causes the computer system to implement a method for line speed interconnect processing, comprising:
receiving initial inputs from an input communications path;
performing a pre-sorting of the initial inputs by using a first stage interconnect parallel processor to create intermediate inputs;
performing the final combining and splitting of the intermediate inputs by using a second stage interconnect parallel processor to create resulting outputs; and
transmitting the resulting outputs out of the second stage at line speed.
10. The computer readable memory of claim 9, wherein the first stage interconnect processor functions by performing a presorting and pre-clustering process on the initial inputs in parallel to identify candidates among the initial inputs to be checked for pairing.
11. The computer readable memory of claim 9, wherein the second stage interconnect processor functions by performing position shuffling, pairing, and splitting of the intermediate inputs in parallel to create the resulting outputs at line speed.
12. The computer readable memory of claim 9, wherein the line speed interconnect processing is implemented in a networking architecture, wherein the initial inputs comprise networking packets.
13. The computer readable memory of claim 9, wherein the line speed interconnect processing is implemented in a cache accessing architecture, wherein the initial inputs comprise access requests to data of cache lines.
14. The computer readable memory of claim 9, wherein the line speed interconnect processing is implemented in an arbitration architecture, wherein the initial inputs comprise streams that utilize output bandwidth, and wherein the arbitration architecture arbitrates amongst the input streams using frequency andor time multiplexing in parallel to create resulting output streams.
15. The computer readable memory of claim 9, wherein the line speed interconnect processing is implemented in a computer instruction architecture decoder, wherein the initial inputs comprise computer instructions that will be combined or split in parallel into machine instructions.
16. The computer readable memory of claim 9, wherein the line speed interconnect processing is implemented in a DRAM accessing architecture, wherein the initial inputs comprise accesses to DRAM pages that will be paired or split in parallel into optimized resulting accesses to DRAM pages.
17. A computer system, comprising:
a system memory;
a central processor unit coupled to the system memory, wherein the central processor unit executes computer readable code and causes the computer system to implement a method for line speed interconnect processing, comprising:
receiving initial inputs from an input communications path;
performing a pre-sorting of the initial inputs by using a first stage interconnect parallel processor to create intermediate inputs;
performing the final combining and splitting of the intermediate inputs by using a second stage interconnect parallel processor to create resulting outputs; and
transmitting the resulting outputs out of the second stage at line speed.
18. The computer system of claim 17, wherein the first stage interconnect processor functions by performing a presorting and pre-clustering process on the initial inputs in parallel to identify candidates among the initial inputs to be checked for pairing.
19. The computer system of claim 17, wherein the second stage interconnect processor functions by performing position shuffling, pairing, and splitting of the intermediate inputs in parallel to create the resulting outputs at line speed.
20. The computer system of claim 17, wherein the line speed interconnect processing is implemented in a networking architecture, wherein the initial inputs comprise networking packets.
21. The computer system of claim 17, wherein the line speed interconnect processing is implemented in a cache accessing architecture, wherein the initial inputs comprise access requests to data of cache lines.
22. The computer system of claim 17, wherein the line speed interconnect processing is implemented in an arbitration architecture, wherein the initial inputs comprise streams that utilize output bandwidth, and wherein the arbitration architecture arbitrates amongst the input streams using frequency andor time multiplexing in parallel to create resulting output streams.
23. The computer system of claim 17, wherein the line speed interconnect processing is implemented in a computer instruction architecture decoder, wherein the initial inputs comprise computer instructions that will be combined or split in parallel into machine instructions.
24. The computer system of claim 17, wherein the line speed interconnect processing is implemented in a DRAM accessing architecture, wherein the initial inputs comprise accesses to DRAM pages that will be paired or split in parallel into optimized resulting accesses to DRAM pages.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. Siglec inhibitor with the formula:
3
whereby
X signifies a negatively charged group such as a carboxy, phosphate or sulphate group or a derivative of them;
Y signifies an H atom, an alkyl or aryl group, a hydroxy group, a glycan, a polymer carrier molecule or a derivative of them;
Z is selected from O, N, C and S;
R1 signifies an H atom, a hydroxy group or a derivative of them;
R2 signifies a hydroxy or amino group or a derivative of them;
R3 signifies a hydroxy group or a derivative of it;
R4 signifies a hydroxy group or a derivative of it;
R5 signifies a substituted or unsubstituted amino group, whereby the substituent is selected from a substituted or unsubstituted formyl, alkanoyl, cycloalkanoyl, aryl-carbonyl, heteroaryl-carbonyl, alkyl, aryl, cycloalkyl or heteroaryl group, whereby these residues can also include one or more unsaturated bonds, whereby R4 acts as H acceptor and R5 as H donor;
R6 signifies an H atom or an alkyl group, a charged group or a derivative of them;
R6 signifies an H atom or an alky group, a charged group or a derivative of them, whereby at least one substituent is selected from R6 and R6 is a hydrophobic group, preferably an H atom or a methyl group; and
R7 signifies an H atom or any group, preferably a group for improving the pharmacological properties of the siglec inhibitor.
2. Siglec inhibitor according to claim 1, whereby the alkanoyl group is selected from an ethanoyl, propanoyl, butanoyl, pentanoyl, hexanoyl, heptanoyl, octanoyl, nonanoyl and decanoyl group, preferably hexanoyl.
3. Siglec inhibitor according to claim 1, whereby the cycloalkanoyl group is selected from a C3 to C6 cycloalkanoyl group, preferably cyclohexanoyl.
4. Siglec inhibitor according to claim 1, whereby the aryl-carbonyl group is selected from a C4 to C15 aryl-carbonyl group, preferably a benzoyl group, naphthoyl group or an anthracen-carbonyl group.
5. Siglec inhibitor according to claim 1, whereby the heteroaryl-carbonyl group is selected from a pyridyl-carbonyl, chinaldine-carbonyl and thiophenyl-carbonyl group.
6. Siglec inhibitor according to claim 1, whereby the alkyl group is selected from a C1-C20 alkyl group, preferably from a methyl, ethyl, propyl, butyl, pentyl and hexyl group.
7. Siglec inhibitor according to claim 1, whereby the cycloalkyl group is selected from a C3-C6 cycloalkyl group.
8. Siglec inhibitor according to claim 1, whereby the aryl group is selected from a phenyl, naphthyl, anthracen group.
9. Siglec inhibitor according to claim 1, whereby the heteroaryl group is selected from a pyridyl and thiophenyl group.
10. Siglec inhibitor according to claim 1, whereby
X signifies a carboxy group, which should be present in an axial position;
Y signifies an H atom, an O-methyl, O-benzyl group or a derivative of a hydroxy group;
Z signifies an O atom;
R1 signifies a hydroxy group;
R2 signifies an amino-acetyl group;
R3 signifies a hydroxy group;
R4 signifies a hydroxy group;
R6 signifies an H atom;
R6 signifies an H atom; and
R7 signifies an H atom.
11. Method of increasing the binding selectivity of siglec inhibitors comprising the introduction of a substituent selected from the residues for R5 according to one of the claims 1 to 10 in position R5 of neuraminic acid or derivatives of it.
12. Method for producing siglec inhibitors with increased affinity for a siglec molecule comprising:
a) introduction of a substituent selected from the residues for R5 according to one of the claims 1 to 10 in position R5 of neuraminic acid or derivatives of it;
b) determination of the affinity of the product according to a) for a siglec molecule;
c) selection of the products with increased affinity;
d) where applicable, further substitution of the selected product according to c) in positions different from position R5, preferably in position R2.
13. Pharmaceutical composition comprising a siglec inhibitor according to one of the claims 1 to 10 and a pharmacologically compatible carrier.
14. Application of a siglec inhibitor according to one of the claims 1 to 10 in the treatment of Siglec mediated diseases.
15. Application of a siglec inhibitor according to one of the claims 1 to 10 in the regulation of the B cell dependent immune response.
16. Application of a siglec inhibitor according to claim 15 in the treatment of allergies, auto-immune diseases and chronic inflammations.
17. Application of a siglec inhibitor according to one of the claims 1 to 10 in the improvement of the regeneration capability of damaged nerves.
18. Application of a siglec inhibitor according to claim 17 in the treatment of paraplegia and multiple sclerosis.
19. Application of a siglec inhibitor according to one of the claims 1 to 10 in the regulation of the cytotoxic activity of NK cells.
20. Application of a siglec inhibitor according to claim 19 in the treatment of cancer diseases.
21. Application of a siglec inhibitor according to claim 19 in the treatment of virus diseases.
22. Application according to claim 15 for increasing the B cell response, in particular in immune-impaired patients.