All The Claims

1. A method comprising:
providing an oscillator;
generating an analog input signal to control a frequency of the oscillator;
generating a digital input signal to control the frequency of the oscillator;
converting the analog signal into a digital signal;
selecting one of the digital input signal and the digital signal; and
controlling the frequency of the oscillator in response to the selected one of the digital input signal and the digital signal.
2. The method of claim 1, wherein the analog signal indicates the frequency of the oscillator.
3. The method of claim 1, further comprising:
updating the frequency in response to a timing of a burst operation.
4. The method of claim 3, further comprising:
in response to the burst operation, enabling an analog-to-digital converter to generate the digital signal.
5. The method of claim 1, further comprising:
providing a first input interface of a transceiver to receive the digital input signal; and
providing a second input interface of the transceiver to receive the analog input signal.
6. The method of claim 5, wherein selecting one of the digital input signal and the digital signal involves selecting between the first and second input interfaces.
7. An apparatus comprising:
a first interface to receive a digital input signal indicative of a frequency for an oscillator;
a second interface to receive an analog input signal indicative of a frequency for the oscillator;
an analog-to-digital converter to convert the analog input signal into a digital signal;
circuitry to select one of the digital input signal and the digital signal; and
a circuit to control the frequency of the oscillator in response to the selected one of the digital input signal and the digital signal.
8. The apparatus of claim 7, wherein the analog signal indicates the frequency for the oscillator.
9. The apparatus of claim 8, wherein the circuit updates the frequency in response to a timing of a burst operation.
10. The apparatus of claim 9, wherein in response to the burst operation, the circuit samples the analog signal and converts the sampled analog signal into the digital signal.
11. The apparatus of claim 9, wherein in response to the burst operation, the circuit enables the analog-to-digital converter to generate the digital signal.
12. The apparatus of claim 7, further comprising a fine tuning register and a coarse tuning register, and wherein the circuit stores the selected one of the digital input signal and the digital signal in one of the fine tuning register and the coarse tuning register, and the circuit produces a digital frequency control signal, responsive to the stored signal, to control the frequency of the oscillator.
13. The apparatus of claim 7, wherein the apparatus has a digital input mode in which the digital input signal is used to control the frequency of the oscillator and the apparatus has an analog input mode in which the analog input signal is used to control the frequency of the oscillator.
14. The apparatus of claim 7, wherein the apparatus comprises a transceiver.
15. A system comprising:
an oscillator;
a first interface to receive a digital input signal indicative of a frequency for the oscillator;
a second interface to receive an analog input signal indicative of a frequency for the oscillator;
an analog-to-digital converter to convert the analog input signal into a digital signal;
circuitry to select one of the digital input signal and the digital signal; and
a circuit to control the frequency of the oscillator in response to the selected one of the digital input signal and the digital signal.
16. The system of claim 15, wherein the analog signal indicates the frequency for the oscillator.
17. The system of claim 16, wherein the circuit updates the frequency in response to a timing of a burst operation.
18. The system of claim 17, wherein in response to the burst operation, the circuit samples the analog signal and converts the sampled analog signal into the digital signal.
19. The system of claim 17, wherein in response to the burst operation, the circuit enables the analog-to-digital converter to generate the digital signal.
20. The system of claim 15, further comprising a fine tuning register and a coarse tuning register, and wherein the circuit stores the selected one of the digital input signal and the digital signal in one of the fine tuning register and the coarse tuning register, and the circuit produces a digital frequency control signal, responsive to the stored signal, to control the frequency of the oscillator.
21. The system of claim 15, wherein the system has a digital input mode in which the digital input signal is used to control the frequency of the oscillator and the apparatus has an analog input mode in which the analog input signal is used to control the frequency of the oscillator.
22. The system of claim 15, wherein the system comprises a wireless communication system.
23. The system of claim 15, wherein the system comprises at least one of a personal digital assistant and a cellular telephone.
24. A wireless system comprising:
a transceiver including:
an oscillator;
a first interface to receive a digital input signal indicative of a frequency for the oscillator;
a second interface to receive an analog input signal indicative of a frequency for the oscillator;
an analog-to-digital converter to convert the analog input signal into a digital signal;
circuitry to select one of the digital input signal and the digital signal; and
a circuit to control the frequency of the oscillator in response to the selected one of the digital input signal and the digital signal; and

a processor to provide the digital input signal and the analog input signal to the transceiver.
25. The wireless system of claim 24, wherein the transceiver further includes a fine tuning register and a coarse tuning register, and wherein the circuit stores the selected one of the digital input signal and the digital signal in one of the fine tuning register and the coarse tuning register, and the circuit produces a digital frequency control signal, responsive to the stored signal, to control the frequency of the oscillator.
26. The wireless system of claim 24, wherein the oscillator provides a reference signal having the frequency and the transceiver further comprises a demodulator synchronized to the reference signal.
27. A transceiver comprising:
an oscillator;
a first external interface to receive a digital input signal indicative of a frequency for the oscillator;
a second external interface to receive an analog input signal indicative of the frequency for the oscillator;
an analog-to-digital converter to convert the analog input signal into a digital signal;
circuitry to select one of the digital input signal and the digital signal; and
a circuit to control the frequency of the oscillator in response to the selected one of the digital input signal and the digital signal.
28. The transceiver of claim 27, wherein the transceiver is located inside a single semiconductor package, and the first external interface comprises at least one external pin of the package.
29. The transceiver of claim 27, wherein the transceiver is located inside a single semiconductor package, and the second external interface comprises at least one external pin of the package.
30. The transceiver of claim 27, further comprising:
a monolithic substrate, wherein
the first external interface, the second external interface and the oscillator are all fabricated in the substrate.
31. The transceiver of claim 27, further comprising a fine tuning register and a coarse tuning register, and wherein the circuit stores the selected one of the digital input signal and the digital signal in one of the fine tuning register and the coarse tuning register, and the circuit produces a digital frequency control signal, responsive to the stored signal, to control the frequency of the oscillator.
32. The transceiver of claim 27, wherein the transceiver has a digital input mode in which the digital input signal is used to control the frequency of the oscillator and the apparatus has an analog input mode in which the analog input signal is used to control the frequency of the oscillator.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A window comprising;
a pane; and
a geometrically patterned grid embedded in the pane, the grid comprising an electrically conductive material and operable to attenuate radio frequency (RF) energy.
2. The window of claim 1 wherein the grid is electrically connected to ground.
3. The window of claim 1 wherein the grid is comprised of generally square openings.
4. The window of claim 1 wherein the grid is comprised of generally triangular openings.
5. The window of claim 1 wherein the grid is comprised of at least one fractal-derived shape.
6. A method of attenuating radio frequency (RF) energy in a window comprising:
providing a pane;
forming a geometrically patterned grid of electrically conductive material;
embedding a geometrically patterned grid in the pane;
receiving RF energy at the pane; and
attenuating the received RF energy utilizing the grid.
7. The method of claim 6 further comprising electrically connecting the grid to ground.
8. The method of claim 6 wherein forming a geometrically patterned grid comprises forming the grid of generally square openings.
9. The method of claim 6 wherein forming a geometrically patterned grid comprises forming the grid of generally triangular openings.
10. The method of claim 6 wherein forming a geometrically patterned grid comprises forming of at least one fractal-derived shape.

1. A cold storage-based computing system, comprising:
a memory device including a target memory region;
a plurality of processors;
a shared memory controller coupled to the plurality of processors and the memory device, the shared memory controller including:
a write monitor to detect a pending write operation directed to the target memory region,
a degradation detector coupled to the write monitor, the degradation detector to determine whether the target memory region satisfies a degradation condition in response to the pending write operation; and
a cold storage migrator coupled to the degradation detector and the target memory region, the cold storage migrator to reconfigure the target memory region as a cold storage region if the target memory region satisfies the degradation condition.
2. The system of claim 1, wherein the degradation detector includes:
a write counter to update a number of write operations directed to the target memory region based on the pending write operation; and
a trigger unit to compare the number of write operations to an offset value, wherein the degradation condition is to be satisfied of the number of write operations exceeds the offset value.
3. The system of claim 1, wherein the shared memory controller further includes a cold storage reporter coupled to the cold storage migrator, the cold storage reporter to expose the cold storage region to an operating system as part of a contiguous cold storage pool.
4. The system of claim 1, wherein the cold storage migrator includes a mode adjuster to change a mode of operation for the target memory region from a volatile mode to a non-volatile mode.
5. The system of claim 1, wherein the write monitor is to detect one or more of a data processing write, a refresh write or a disturbance integrity write.
6. The system of claim 1, wherein the shared memory controller further includes a replacement memory migrator coupled to the degradation detector, the replacement memory migrator to re-map the pending write operation to a replacement memory region if the target memory region satisfies the degradation condition.
7. A method of operating a memory controller, comprising:
detecting a pending write operation directed to a target memory region;
determining whether the target memory region satisfies a degradation condition in response to the pending write operation; and
reconfiguring the target memory region as a cold storage region if the target memory region satisfies the degradation condition.
8. The method of claim 7, wherein determining whether the target memory region satisfies the degradation condition includes:
updating a number of write operations directed to the target memory region based on the pending write operation; and
comparing the number of write operations to an offset value, wherein the degradation condition is satisfied if the number of write operations exceeds the offset value.
9. The method of claim 7, further including exposing the cold storage region to an operating system as part of a contiguous cold storage pool.
10. The method of claim 7, wherein reconfiguring the target memory region includes changing a mode of operation for the target memory region from a volatile mode to a non-volatile mode.
11. The method of claim 7, wherein detecting the pending write operation includes detecting one or more of a data processing write, a refresh write or a disturbance integrity write.
12. The method of claim 7, further including re-mapping the pending write operation to a replacement memory region if the target memory region satisfies the degradation condition.
13. At least one computer readable storage medium comprising a set of instructions which, when executed by a memory controller, cause the memory controller to:
detect a pending write operation directed to a target memory region;
determine whether the target memory region satisfies a degradation condition in response to the pending write operation; and
reconfigure the target memory region as a cold storage region if the target memory region satisfies the degradation condition.
14. The at least one computer readable storage medium of claim 13, wherein the instructions, when executed, cause the memory controller to:
update a number of write operations directed to the target memory region based on the pending write operation; and
compare the number of write operations to an offset value, wherein the degradation condition is to be satisfied if the number of write operations exceeds the offset value.
15. The at least one computer readable storage medium of claim 13, wherein the instructions, when executed, cause the memory controller to expose the cold storage region to an operating system as part of a contiguous cold storage pool.
16. The at least one computer readable storage medium of claim 13, wherein the instructions, when executed, cause the memory controller to change a mode of operation for the target memory region from a volatile mode to a non-volatile mode to reconfigure the target memory region.
17. The at least one computer readable storage medium of claim 13, wherein one or more of a data processing write, a refresh write or a disturbance integrity write are detected.
18. The at least one computer readable storage medium of claim 13, wherein the instructions, when executed, cause the memory controller to re-map the pending write operation to a replacement memory region if the target memory region satisfies the degradation condition.
19. A memory controller, comprising:
a write monitor to detect a pending write operation directed to a target memory region;
a degradation detector coupled to the write monitor, the degradation detector to determine whether the target memory region satisfies a degradation condition in response to the pending write operation; and
a cold storage migrator coupled to the degradation detector and the target memory region, the cold storage migrator to reconfigure the target memory region as a cold storage region if the target memory region satisfies the degradation condition.
20. The memory controller of claim 19, wherein the degradation detector includes:
a write counter to update a number of write operations directed to the target memory region based on the pending write operation; and
a trigger unit to compare the number of write operations to an offset value, wherein the degradation condition is to be satisfied if the number of write operations exceeds the offset value.
21. The memory controller of claim 19, further including a cold storage reporter coupled to the cold storage migrator, the cold storage reporter to expose the cold storage region to an operating system as part of a contiguous cold storage pool.
22. The memory controller of claim 19, wherein the cold storage migrator includes a mode adjuster to change a mode of operation for the target memory region from a volatile mode to a non-volatile mode.
23. The memory controller of claim 19, wherein the write monitor is to detect one or more of a data processing write, a refresh write or a disturbance integrity write.
24. The memory controller of claim 19, further including a replacement memory migrator coupled to the degradation detector, the replacement memory migrator to re-map the pending write operation to a replacement memory region if the target memory region satisfies the degradation condition.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor device comprising:
a memory element including a channel formation region, source and drain regions, a region for accumulating charges, and a control gate
wherein each of the source and drain regions is electrically connected to an erasing line through a semiconductor impurity region, and
wherein the source and drain regions are diode-connected to the erasing line.
2. The semiconductor device according to claim 1, wherein the memory element is provided over an insulating surface.
3. The semiconductor device according to claim 1, wherein the channel formation region, the source and drain regions, and the semiconductor impurity region are included in one semiconductor film.
4. The semiconductor device according to claim 1, wherein the source and drain regions and the semiconductor impurity region form PN junctions.
5. The semiconductor device according to claim 1, further comprising a first transistor and a second transistor,
wherein the control gate is electrically connected to a word line,
wherein one of the source and drain regions of the memory element is electrically connected to a source line through the first transistor, and
wherein the other of the source and drain regions of the memory element is electrically connected to a bit line through the second transistor.
6. The semiconductor device according to claim 1 wherein the channel formation region further comprises silicon or germanium.
7. A semiconductor device comprising:
a memory element including a channel formation region, source and drain regions, a region for accumulating charges, and a control gate
wherein:
each of the source and drain regions is electrically connected to an erasing line through a semiconductor impurity region,
a conductivity type of the source and drain regions is different from that of the semiconductor impurity region,
the source and drain regions include an impurity element at a higher concentration than the semiconductor impurity region, and
wherein the source and drain regions are diode-connected to the erasing line.
8. The semiconductor device according to claim 7, wherein the memory element is provided over an insulating surface.
9. The semiconductor device according to claim 7, wherein the channel formation region, the source and drain regions, and the semiconductor impurity region are included in one semiconductor film.
10. The semiconductor device according to claim 7, wherein the source and drain regions and the semiconductor impurity region form PN junctions.
11. The semiconductor device according to claim 7, further comprising a first transistor and a second transistor,
wherein the control gate is electrically connected to a word line,
wherein one of the source and drain regions of the memory element is electrically connected to a source line through the first transistor, and
wherein the other of the source and drain regions of the memory element is electrically connected to a bit line through the second transistor.
12. The semiconductor device according to claim 7, wherein the channel formation region further comprises silicon or germanium.
13. A semiconductor device comprising:
a memory element including a channel formation region, source and drain regions, a region for accumulating charges, and a control gate
wherein:
each of the source and drain regions is electrically connected to an erasing line through a semiconductor impurity region,
a conductivity type of the source and drain regions is different from that of the semiconductor impurity region,
the source and drain regions include an impurity element at a higher concentration than the semiconductor impurity region,
the source and drain regions are electrically connected to the semiconductor impurity region through a semiconductor region,
the source and drain regions and the semiconductor impurity region include the impurity element at a higher concentration than the semiconductor region, and
wherein the source and drain regions are diode-connected to the erasing line.
14. The semiconductor device according to claim 13, wherein the memory element is provided over an insulating surface.
15. The semiconductor device according to claim 13, wherein the channel formation region, the source and drain regions, and the semiconductor impurity region are included in one semiconductor film.
16. The semiconductor device according to claim 13, wherein the source and drain regions, the semiconductor impurity region and the semiconductor region form PIN junctions.
17. The semiconductor device according to claim 13, further comprising a first transistor and a second transistor,
wherein the control gate is electrically connected to a word line,
wherein one of the source and drain regions of the memory element is electrically connected to a source line through the first transistor, and
wherein the other of the source and drain regions of the memory element is electrically connected to a bit line through the second transistor.
18. The semiconductor device according to claim 13, wherein the channel formation region further comprises silicon or germanium.