All The Claims

1. A computer-implemented method for navigating into a three-dimensional scene, the method comprising the steps of:
displaying a graphical tool having the shape of a parallelepiped represented in isometric projection, each of its six sides being associated with an orthographic view of the scene, the three background sides being unfolded for them to be visible, the graphical tool being arranged so that all faces are accurately selectable by the user;
selecting one side of the graphical tool; and
displaying the orthographic view associated to the selected side.
2. The method according to claim 1, wherein the graphical tool has the shape of a cube.
3. The method according to claim 1, wherein the graphical tool is superimposed over the three-dimensional scene.
4. The method according to claim 1, wherein the each background side is unfold in a way that it keeps a connecting edge in common with one of its four neighbouring sides.
5. The method according to claim 4, wherein the connecting edges do not meet each other.
6. The method according to claim 1, wherein the graphical tool is displayed in a window and is motionless in this window.
7. The method according to anyone claim 1, wherein a preview of the orthographic views is printed on the sides of the graphical tool.
8. The method according to claim 7, wherein the preview is highlighted when the cursor reaches its associated side.
9. The method according to claim 7, wherein the preview is rotated is order to make it more readable for the user.
10. The method according to claim 1, wherein the background sides are unfolded such that their displayed areas are maximized.
11. A computer program product comprising:
a computer readable medium storing a computer program for navigating into a three dimensional scene; and
the computer program comprising code means to take the steps of:
displaying a graphical tool having the shape of a parallelepiped represented in isometric projection, each of its six sides being associated with an orthographic view of the scene, the three background sides being unfolded for them to be visible, the graphical tool being arranged so that all faces are accurately selectable by the user;
selecting one side of the graphical tool; and
displaying the orthographic view associated to the selected side.
12. A computer apparatus comprising:
means for navigating into a three dimensional scene; and
means for implementing the steps of:
displaying a graphical tool having the shape of a parallelepiped represented in isometric projection, each of its six sides being associated with an orthographic view of the scene, the three background sides being unfolded for them to be visible, the graphical tool being arranged so that all faces are accurately selectable by the user;
selecting one side of the graphical tool; and
displaying the orthographic view associated to the selected side.
The claims below are in addition to those above.
All refrences to claims which appear below refer to the numbering after this setence.

1. An adhesion structure including:
an electrically conductive member containing aluminum as a main component; and
an electrically conductive adhesive adhering to the electrically conductive member, the adhesive having a conductive filler mixed therein,
wherein the electrically conductive adhesive contains 40% to 50% of the filler in volume ratio to a binder, and
wherein the value of resistance between the electrically conductive member and the conductive adhesive after curing is 10 ohms or less.
2. An adhesion structure according to claim 1, wherein a resistance component due to an oxide film formed on a surface of the electrically conductive member is reduced by applying a resistance lowering voltage between the electrically conductive member and the electrically conductive adhesive.
3. An adhesion structure according to claim 2, wherein electric energy supplied when the resistance lowering voltage is being applied therebetween is in a range of 0.08 J to 4 J relative to the application quantity of 1 mg to 10 mg of the electrically conductive adhesive.
4. A disk drive device including:
a hub, made of an electrically conductive material, which supports a recording disk;
a shaft, made of an electrically conductive material, which rotates together with the hub, the shaft being fixed to a rotation center of the hub;
a shaft holding member which has a space for housing at least part of the shaft and has a conductor in the at least part thereof; and
a base member, made of an electrically conductive material, which supports the shaft holding member,
wherein the base member is an electrically conductive member containing aluminum as a main component,
wherein the base member and the conductor of the shaft holding member are connected through the medium of an electrically conductive adhesive having a conductive filler mixed therein,
wherein the electrically conductive adhesive contains 40% to 50% of the filler in volume ratio to a binder, and
wherein the value of resistance between the hub and the base member after curing of the electrically conductive adhesive is 10 ohms or less.
5. A disk drive device according to claim 4, wherein a resistance component due to an oxide film formed on a surface of the base member is reduced by applying a resistance lowering voltage between and the conductor of the shaft holding member and the base member connected through the medium of the electrically conductive adhesive.
6. A disk drive device according to claim 5, wherein electric energy supplied when the resistance lowering voltage is being applied therebetween is in a range of 0.08 J to 4 J relative to the application quantity of 1 mg to 10 mg of the electrically conductive adhesive.
7. An adhesion method including:
applying an electrically conductive adhesive, having a conductive filler mixed therein, to an electrically conductive member containing aluminum as a main component so as to adhere to the electrically conductive member in an electrically conductive manner; and
applying a resistance lowering voltage between the electrically conductive member and the electrically conductive adhesive after curing the electrically conductive adhesive so as to reduce a resistance component due to an oxide film formed on a surface of the electrically conductive member.
8. An adhesion method according to claim 7, wherein electric energy supplied when the resistance lowering voltage is being applied therebetween is in a range of 0.08 J to 4 J relative to the application quantity of 1 mg to 10 mg of the electrically conductive adhesive.
9. A method for manufacturing an electrically conductive hub which supports a recording disk, an electrically conductive shaft, fixed to a rotation center of the hub, which rotates together with the hub, a shaft holding member which has a space for housing at least part of the shaft and has a conductor in the at least part thereof, and an electrically conductive base member which supports the shaft holding member, the method including:
applying an electrically conductive adhesive, having a conductive filler mixed therein, to a conductor of the shaft holding member and the electrically conductive base;
curing the electrically conductive adhesive; and
applying a resistance lowering voltage between the conductor and the electrically conductive base after curing the electrically conductive adhesive so as to reduce a resistance component due to an oxide film formed on a surface of the electrically conductive base member.
10. An adhesion method according to claim 9, wherein electric energy supplied when the resistance lowering voltage is being applied therebetween is in a range of 0.08 J to 4 J relative to the application quantity of 1 mg to 10 mg of the electrically conductive adhesive.

1. A mobile radio communication device, comprising:
a short range wireless receiver, configured to receive data from another mobile radio communication device; and
a cellular wireless transmitter, configured to transmit to a mobile radio base station of a cellular mobile radio communication system information related to a set of cells of the cellular mobile radio communication system as a set of candidate cells for communication of the other mobile radio communication device with the cellular mobile radio communication system.
2. The mobile radio communication device of claim 1,
wherein the information comprises information related to a tracking area of the other mobile radio communication device.
3. The mobile radio communication device of claim 2,
wherein the information comprises a tracking area update request.
4. The mobile radio communication device of claim 1,
wherein the short range wireless receiver is further configured to receive the information from the other mobile radio communication device.
5. The mobile radio communication device of claim 1,
wherein the short range wireless receiver is further configured to receive an instruction from the other mobile radio communication device.
6. The mobile radio communication device of claim 1,
wherein the set of cells comprises a set of cells of the cellular mobile radio communication system as a set of candidate cells for communication of the mobile radio communication device with the cellular mobile radio communication system.
7. The mobile radio communication device of claim 1,
wherein the mobile radio communication device is a relaying mobile radio communication device in an opportunistic network comprising the other mobile radio communication device.
8. A mobile radio communication device, comprising:
a short range wireless transmitter, configured to transmit to another mobile radio communication device information related to a set of cells of a cellular mobile radio communication system as a set of candidate cells for communication of the mobile radio communication device with the cellular mobile radio communication system.
9. The mobile radio communication device of claim 8,
wherein the information comprises information related to a tracking area of the mobile radio communication device.
10. The mobile radio communication device of claim 9,
wherein the information comprises a tracking area update request.
11. The mobile radio communication device of claim 9,
wherein the information comprises a request for the other mobile radio communication device to generate a tracking area update request for the mobile radio communication device.
12. The mobile radio communication device of claim 8,
wherein the mobile radio communication device is a mobile radio communication device in an opportunistic network comprising the other mobile radio communication device as a relaying mobile radio communication device.
13. A server, comprising:
a receiver, configured to receive from a first mobile radio communication device information related to a set of cells of a cellular mobile radio communication system as a set of candidate cells for communication of a second mobile radio communication device with the cellular mobile radio communication system.
14. The server of claim 13,
wherein the information comprises information related to a tracking area of the second mobile radio communication device.
15. The server of claim 14,
wherein the information comprises a tracking area update request.
16. The server of claim 20, further comprising:
a storage configured to store tracking area information related to the second mobile radio communication device;
wherein the storage is further configured to store a plurality of routes to the second mobile radio communication device.
17. The server of claim 16,
wherein the plurality of routes comprises a route to the second mobile radio communication device via the first mobile radio communication device.
18. A mobile radio communication device, comprising:
a cellular wireless receiver, configured to receive from a cellular mobile radio communication system information indicating that data for another mobile radio communication device is available in the cellular mobile radio communication system; and
a short range wireless transmitter, configured to transmit to the other mobile radio communication device the received information.
19. The mobile radio communication device of claim 18,
wherein the information comprises paging information for the other mobile radio communication device.
20. The mobile radio communication device of claim 18,
wherein the mobile radio communication device is a relaying mobile radio communication device in an opportunistic network comprising the other mobile radio communication device.
21. A mobile radio communication device, comprising:
a short range wireless receiver, configured to receive from another mobile radio communication device information indicating that data for the mobile radio communication device is available in a cellular mobile radio communication system.
22. The mobile radio communication device of claim 21,
wherein the information comprises paging information for the mobile radio communication device.
23. The mobile radio communication device of claim 21, further comprising:
a transceiver configured to communicate with the cellular wireless radio communication system upon reception of the information by the short range wireless receiver.
24. The mobile radio communication device of claim 21,
wherein the mobile radio communication device is a mobile radio communication device in an opportunistic network comprising the other mobile radio communication device as a relaying mobile radio communication device.
25. A server, comprising:
a transmitter, configured to transmit to a first mobile radio communication device information indicating that data for a second mobile radio communication device is available in a cellular mobile radio communication system.
The claims below are in addition to those above.
All refrences to claims which appear below refer to the numbering after this setence.

What is claimed is:

1. A serial access memory comprising:
a first memory array including a plurality of first memory cells, a plurality of first sense amplifiers and a plurality of pairs of first bit lines connected to the first memory cells and the first sense amplifiers;
a second memory array including a plurality of second memory cells, a plurality of second sense amplifiers and a plurality of pairs of second bit lines connected to the second memory cells and the second sense amplifiers;
a plurality of pairs of column lines each of which is connected to one of the pairs of first bit lines and one of the pairs of the second bit lines;
a plurality of write registers each of which is connected to one of the pairs of column lines;
a write address accessing circuit connected to said write registers for selecting one of said write registers;
a plurality of read registers each of which is connected to one of the pairs of column lines;
a read address accessing circuit connected to said read registers for selecting one of said read registers;
an input circuit connected to said write registers; and
an output circuit connected to said read registers.
2. A serial access memory according to claim 1, further comprising,
a first X address accessing circuit connected to the first memory cells in a direction substantially perpendicular to the first bit lines, and
a second X address accessing circuit connected to the second memory cells in a direction substantially perpendicular to the second bit lines.
3. A serial access memory according to claim 1, further comprising,
a plurality of additional read registers each of which is connected to one of the pairs of column lines,
an additional read address accessing circuit connected to said additional read registers for selecting one of said read registers, and
an additional output circuit connected to said additional read registers.
4. A serial access memory according to claim 1, further comprising,
a plurality of first transfer circuits each of which is connected between one of said pairs of column lines and one of said pairs of first bit line’s, said first transfer circuits connecting said column lines to said first bit lines in response to a first control signal, and
a plurality of second transfer circuits each of which is connected between one of said pairs of column lines and one of said pairs of second bit lines, said second transfer circuits connecting said column lines to said second bit lines in response to a second control signal.
5. A serial access memory according to claim 1, further comprising,
a plurality of third transfer circuits each of which is connected between one of said pairs of column lines and one of said read registers, said third transfer circuits connecting said column lines to said read registers in response to a third control signal, and
a plurality of fourth transfer circuits each of which is connected between one of said read registers and said output circuit, said fourth transfer circuits connecting said read registers to said output circuit in response to a fourth control signal.
6. A serial access memory according to claim 1, further comprising,
a plurality of fifth transfer circuits each of which is connected between one of said pairs of column lines and one of said write registers, said fifth transfer circuits connecting said column lines to said write registers in response to a fifth control signal, and
a plurality of sixth transfer circuits each of which is connected between one of said write registers and said input circuit, said sixth transfer circuits connecting said write registers to said output circuit in response to a sixth control signal.
7. A serial access memory according to claim 1, wherein one of said read registers is connected to one column line of one of said pairs of column lines, and one of said write registers is connected to the other column line of one of said pairs of column lines.
8. A serial access memory comprising:
a first memory array including a plurality of first memory cells, a plurality of first sense amplifiers and a plurality of first and second pairs of bit lines connected to the first memory cells and the first sense amplifiers;
a second memory array including a plurality of second memory cells, a plurality of second sense amplifiers and a plurality of third and fourth pairs of bit lines connected to the second memory cells and the second sense amplifiers;
a plurality of pairs of first column lines each of which is connected to one of the first pairs of bit lines and one of the third pairs of the bit lines;
a plurality of pairs of second column lines each of which is connected to one of the second pairs of bit lines and one of the fourth pairs of the bit lines;
a plurality of write registers;
a plurality of first transfer circuits each of which is connected between one of said first column lines to one of said write registers, said first transfer circuits connecting the first column lines to said write registers in response to a first control signal;
a plurality of second transfer circuits each of which is connected between one of said second column lines to one of said write registers, said second transfer circuits connecting the second column lines to said write registers in response to a second control signal;
a write address accessing circuit connected to said write registers for selecting one of said write registers;
a plurality of read registers;
a plurality of third transfer circuits each of which is connected between one of said first column lines to one of said read registers, said third transfer circuits connecting the first column lines to said read registers in response to a third control signal;
a plurality of fourth transfer circuits each of which is connected between one of said second column lines to one of said read registers, said fourth transfer circuits connecting the second column lines to said read registers in response to a fourth control signal;
a read address accessing circuit connected to said read registers for selecting one of said read registers;
an input circuit connected to said write registers; and
an output circuit connected to said read registers.
9. A serial access memory according to claim 8, further comprising,
a first X address accessing circuit connected to the first memory cells in a direction substantially perpendicular to said first and second pairs of bit lines, and
a second X address accessing circuit connected to the second memory cells in a direction substantially perpendicular to said third and fourth pairs of bit lines.
10. A serial access memory according to claim 8, wherein each of said write registers and read registers is located between one of said first column lines.
11. A serial access memory according to claim 8, further comprising,
a plurality of fifth transfer circuits each of which is connected between one of said pairs of first column lines and one of said pairs of first bit lines, said fifth transfer circuits connecting said column lines to said first bit lines in response to a fifth control signal,
a plurality of sixth transfer circuits each of which is connected between one of said pairs of first column lines and one of said pairs of third bit lines, said sixth transfer circuits connecting said third column lines to said third bit lines in response to a sixth control signal.
12. A serial access memory according to claim 8, further comprising,
a plurality of seventh transfer circuits each of which is connected between one of said pairs of second column lines and one of said pairs of second bit lines, said seventh transfer circuits connecting said second column lines to said second bit lines in response to a seventh control signal,
a plurality of eighth transfer circuits each of which is connected between one of said pairs of second column lines and one of said pairs of fourth bit lines, said eighth transfer circuits connecting said second column lines to said fourth bit lines in response to an eighth control signal.
13. A serial access memory according to claim 8, further 4.9 comprising,
a plurality of ninth transfer circuits each of which is connected between one of said input circuit and one of said write registers, said ninth transfer circuits connecting said input circuit to said write registers in response to a ninth control signal, and
a plurality of tenth transfer circuits each of which is connected between said output circuit and one of said read registers, said tenth transfer circuits connecting said output circuit to said read registers in response to a tenth control signal.
14. A serial access memory comprising:
a first memory array including a plurality of first memory cells, a plurality of first sense amplifiers and a plurality of first and second pairs of bit lines connected to the first memory cells and the first sense amplifiers;
a second memory array including a plurality of second memory cells, a plurality of second sense amplifiers and a plurality of third and fourth pairs of bit lines connected to the second memory cells and the second sense amplifiers;
a plurality of pairs of column lines each of which is connected to one of said first pairs of bit lines, one of said second pairs of bit lines, one of said third pairs of bit lines and one of said fourth pairs of bit lines;
a plurality of first transfer circuits each of which is connected between one of said column lines to one of said first pairs of bit lines, said first transfer circuits connecting the column lines to said first pairs of bit lines in response to a first control signal;
a plurality of second transfer circuits each of which is connected between one of said column lines to one of said second pairs of bit lines, said first transfer circuits connecting the column lines to said second pairs of bit lines in response to a second control signal;
a plurality of third transfer circuits each of which is connected between one of said column lines to one of said third pairs of bit lines, said first transfer circuits connecting the column lines to said third pairs of bit lines in response to a third control signal;
a plurality of fourth transfer circuits each of which is connected between one of said column lines to one of said fourth pairs of bit lines, said first transfer circuits connecting the column lines to said fourth pairs of bit lines response to a fourth control signal;
a plurality of write registers;
a write address accessing circuit connected to said write registers for electing one of said write registers;
a plurality of read registers;
a read address accessing circuit connected to said read registers for selecting one of said read registers;
an input circuit connected to said write registers; and
an output circuit connected to said read registers.
15. A serial access memory according to claim 14, further comprising,
a first X address accessing circuit connected to the first memory cells in a direction substantially perpendicular to the first and second bit lines, and
a second X address accessing circuit connected to the second memory cells in a direction substantially perpendicular to the third and fourth bit lines.
16. A serial access memory according to claim 14, wherein each of said write registers and read registers is located between one of said pairs of column lines.
17. A serial access memory according to claim 14, further comprising,
a plurality of fifth transfer circuits each of which is connected between one of said input circuit and one of said write registers, said fifth transfer circuits connecting said input circuit to said write registers in response to a fifth control signal, and
a plurality of sixth transfer circuits each of which is connected between said output circuit and one of said read registers, said sixth transfer circuits connecting said output circuit to said read registers in response to a sixth control signal.
18. A serial access memory according to claim 14, further comprising,
a plurality of seventh transfer circuits each of which is connected between one of said pairs of column lines and one of said write registers, said seventh transfer circuits connecting said column lines to said write registers in response to a seventh control signal, and
a plurality of eighth transfer circuits each of which is connected between said pairs of column lines and one of said read registers, said eighth transfer circuits connecting said column lines to said read registers in response to an eighth control signal.
19. A serial access memory according to claim 14, further comprising a division circuit connected to said column lines, said division circuit electrically dividing said first memory array from said second memory array in response to a divisional signal.